mapping = {
    "ReadMemory8"     : "read_memory8",
    "ReadMemory16"    : "read_memory16",
    "ReadMemory32"    : "read_memory32",
    "WriteMemory8"    : "write_memory8",
    "WriteMemory16"   : "write_memory16",
    "WriteMemory32"   : "write_memory32",
    "ZeroExtend1"     : "zero_extend1",
    "ZeroExtend4"     : "zero_extend4",
    "ZeroExtend5"     : "zero_extend5",
    "ZeroExtend8"     : "zero_extend8",
    "ZeroExtend16"    : "zero_extend16",
    "ZeroExtend32"    : "zero_extend32",
    "SignedSaturate32": "signed_saturate32",
    "SignedSaturate48": "signed_saturate48",
    "SignExtend8"     : "sign_extend8",
    "SignExtend12"    : "sign_extend12",
    "SignExtend16"    : "sign_extend16",
    "SignExtend32"    : "sign_extend32",
    "Register"        : "_register",
    "Bit"             : "bit",

    "MACH"            : "state->mach",
    "MACL"            : "state->macl",
    "PR"              : "state->pr[0]",
    "PR’"             : "state->pr[1]",
    "PR’’"            : "state->pr[2]",
    "PC"              : "state->pc[0]",
    "PC’"             : "state->pc[1]",
    "PC’’"            : "state->pc[2]",
    "FPSCR"           : "state->fpscr.value",
    "FPUL"            : "state->fpul",

    "SR"              : "state->sr.value",
    "SSR"             : "state->ssr",
    "SPC"             : "state->spc",
    "GBR"             : "state->gbr",
    "VBR"             : "state->vbr",
    "SGR"             : "state->sgr",
    "DBR"             : "state->dbr",

    "R0"              : "REG(state, 0)",
    "Rm"              : "REG(state, m)",
    "Rm_BANK"         : "REG_BANK(state, m)",
    "Rn"              : "REG(state, n)",
    "Rn_BANK"         : "REG_BANK(state, n)",

    "T"               : "state->sr.bits.t",
    "S"               : "state->sr.bits.s",
    "Q"               : "state->sr.bits.q",
    "M"               : "state->sr.bits.m",
    "MD"              : "state->sr.bits.md",

    "NOP"             : "",

    "BREAK"           : "BREAK",
    "FIRSTWRITE"      : "FIRSTWRITE",
    "FPUDIS"          : "FPUDIS",
    "FPUEXC"          : "FPUEXC",
    "ILLSLOT"         : "ILLSLOT",
    "RADDERR"         : "RADDERR",
    "READPROT"        : "READPROT",
    "RESINST"         : "RESINST",
    "RTLBMISS"        : "RTLBMISS",
    "SLOTFPUDIS"      : "SLOTFPUDIS",
    "TRAP"            : "TRAP",
    "WADDERR"         : "WADDERR",
    "WRITEPROT"       : "WRITEPROT",
    "WTLBMISS"        : "WTLBMISS",

    "IsDelaySlot"     : "is_delay_slot",
    "SLEEP"           : "sleep",
    "OCBP"            : "ocbp",

    "ASID"            : "ASID",
    "VPN"             : "VPN",
    "PPN"             : "PPN",
    "SZ0"             : "SZ0",
    "SZ1"             : "SZ1",
    "SH"              : "SH",
    "WT"              : "WT",
    "C"               : "C",
    "D"               : "D",
    "V"               : "V",

    "ALLOCO"          : "ALLOCO",
    "MMU"             : "MMU",
    "MMUCR"           : "MMUCR",
    "OCBI"            : "OCBI",
    "OCBWB"           : "OCBWB",
    "PREF"            : "PREF",
    "PTEH"            : "PTEH",
    "PTEL"            : "PTEL",
    "URC"             : "URC",
    "UTLB"            : "UTLB",

    "AddressUnavailable": "address_unavailable",
    "DataAccessMiss"  : "data_access_miss",
    "DirtyBit"        : "dirty_bit",
    "ReadProhibited"  : "read_prohibited",
    "WriteProhibited" : "write_prohibited",

    "FR0"             : "FR_(state, 0)",
    "FRm"             : "FR_(state, m)",
    "FRn"             : "FR_(state, n)",
    "FP2m"            : "FP2_(state, m)",
    "FP2n"            : "FP2_(state, n)",
    "DR2m"            : "DR2_(state, m)",
    "DR2n"            : "DR2_(state, n)",
    "XD2m"            : "XD2_(state, m)",
    "XD2n"            : "XD2_(state, n)",
    "FV4n"            : "FV4_(state, n)",
    "FV4m"            : "FV4_(state, m)",
    "XMTRX"           : "XMTRX(state)",

    "FR"              : "fr",
    "SZ"              : "sz",

    "ReadMemoryPair32"    : "read_memory_pair32",
    "WriteMemoryPair32"   : "write_memory_pair32",

    "FloatRegister32"      : "float_register32",
    "FloatRegister64"      : "float_register64",
    "FloatRegisterPair32"  : "float_register_pair32",
    "FloatRegisterVector32": "float_register_vector32",
    "FloatValue32"         : "float_value32",
    "FloatValue64"         : "float_value64",
    "FloatValuePair32"     : "float_value_pair32",
    "FloatValueVector32"   : "float_value_vector32",
    "FloatValueMatrix32"   : "float_value_matrix32",

    "FADD_S"              : "fadd_s",
    "FADD_D"              : "fadd_d",
    "FSUB_S"              : "fsub_s",
    "FSUB_D"              : "fsub_d",
    "FMUL_S"              : "fmul_s",
    "FMUL_D"              : "fmul_d",
    "FDIV_S"              : "fdiv_s",
    "FDIV_D"              : "fdiv_d",

    "FABS_S"              : "fabs_s",
    "FABS_D"              : "fabs_d",
    "FNEG_S"              : "fneg_s",
    "FNEG_D"              : "fneg_d",
    "FSQRT_S"             : "fsqrt_s",
    "FSQRT_D"             : "fsqrt_d",

    "FCMPEQ_S"            : "fcmpeq_s",
    "FCMPEQ_D"            : "fcmpeq_d",
    "FCMPGT_S"            : "fcmpgt_s",
    "FCMPGT_D"            : "fcmpgt_d",

    "FCNV_SD"             : "fcnv_sd",
    "FCNV_DS"             : "fcnv_ds",
    "FTRC_SL"             : "ftrc_sl",
    "FTRC_DL"             : "ftrc_dl",
    "FLOAT_LS"            : "float_ls",
    "FLOAT_LD"            : "float_ld",

    "FMAC_S"              : "fmac_s",
    "FIPR_S"              : "fipr_s",
    "FTRV_S"              : "ftrv_s",

    "FpuIsDisabled"       : "fpu_is_disabled",
    "FpuFlagI"            : "fpu_flag_i",
    "FpuFlagU"            : "fpu_flag_u",
    "FpuFlagO"            : "fpu_flag_o",
    "FpuFlagZ"            : "fpu_flag_z",
    "FpuFlagV"            : "fpu_flag_v",
    "FpuCauseI"           : "fpu_cause_i",
    "FpuCauseU"           : "fpu_cause_u",
    "FpuCauseO"           : "fpu_cause_o",
    "FpuCauseZ"           : "fpu_cause_z",
    "FpuCauseV"           : "fpu_cause_v",
    "FpuCauseE"           : "fpu_cause_e",
    "FpuEnableI"          : "fpu_enable_i",
    "FpuEnableU"          : "fpu_enable_u",
    "FpuEnableO"          : "fpu_enable_o",
    "FpuEnableZ"          : "fpu_enable_z",
    "FpuEnableV"          : "fpu_enable_v",
}