Compare commits
2 Commits
8722f30eb6
...
1c64abef6b
| Author | SHA1 | Date | |
|---|---|---|---|
| 1c64abef6b | |||
| bb69101282 |
@ -1,5 +1,5 @@
|
||||
0111nnnniiiiiiii
|
||||
imm ← SignExtend8(i);
|
||||
imm ← SignExtend8(s);
|
||||
op2 ← SignExtend32(Rn);
|
||||
op2 ← op2 + imm;
|
||||
Rn ← Register(op2);
|
||||
@ -3,7 +3,7 @@ t ← ZeroExtend1(T);
|
||||
pc ← SignExtend32(PC);
|
||||
newpc ← SignExtend32(PC’);
|
||||
delayedpc ← SignExtend32(PC’’);
|
||||
label ← SignExtend8(d) << 1;
|
||||
label ← SignExtend8(s) << 1;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
IF (t = 0)
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
t ← ZeroExtend1(T);
|
||||
pc ← SignExtend32(PC);
|
||||
delayedpc ← SignExtend32(PC’’);
|
||||
label ← SignExtend8(d) << 1;
|
||||
label ← SignExtend8(s) << 1;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
IF (t = 0)
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
1010dddddddddddd
|
||||
pc ← SignExtend32(PC);
|
||||
label ← SignExtend12(d) << 1;
|
||||
label ← SignExtend12(s) << 1;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
temp ← ZeroExtend32(pc + 4 + label);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
1011dddddddddddd
|
||||
pc ← SignExtend32(PC);
|
||||
label ← SignExtend12(d) << 1;
|
||||
label ← SignExtend12(s) << 1;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
delayedpr ← pc + 4;
|
||||
|
||||
@ -3,7 +3,7 @@ t ← ZeroExtend1(T);
|
||||
pc ← SignExtend32(PC);
|
||||
newpc ← SignExtend32(PC’);
|
||||
delayedpc ← SignExtend32(PC’’);
|
||||
label ← SignExtend8(d) << 1;
|
||||
label ← SignExtend8(s) << 1;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
IF (t = 1)
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
t ← ZeroExtend1(T);
|
||||
pc ← SignExtend32(PC);
|
||||
delayedpc ← SignExtend32(PC’’);
|
||||
label ← SignExtend8(d) << 1;
|
||||
label ← SignExtend8(s) << 1;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
IF (t = 1)
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
10001000iiiiiiii
|
||||
r0 ← SignExtend32(R0);
|
||||
imm ← SignExtend8(i);
|
||||
imm ← SignExtend8(s);
|
||||
t ← INT (r0 = imm);
|
||||
T ← Bit(t);
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
op1 ← SignExtend32(Rm);
|
||||
op2 ← SignExtend32(Rn);
|
||||
q ← op2< 31 FOR 1 >;
|
||||
_m ← op1< 31 FOR 1 >;
|
||||
t ← _m ⊕ q;
|
||||
m ← op1< 31 FOR 1 >;
|
||||
t ← m ⊕ q;
|
||||
Q ← Bit(q);
|
||||
M ← Bit(_m);
|
||||
M ← Bit(m);
|
||||
T ← Bit(t);
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
0000000000011001
|
||||
q ← 0;
|
||||
_m ← 0;
|
||||
m ← 0;
|
||||
t ← 0;
|
||||
Q ← Bit(q);
|
||||
M ← Bit(_m);
|
||||
M ← Bit(m);
|
||||
T ← Bit(t);
|
||||
|
||||
@ -1,18 +1,18 @@
|
||||
0011nnnnmmmm0100
|
||||
q ← ZeroExtend1(Q);
|
||||
_m ← ZeroExtend1(M);
|
||||
m ← ZeroExtend1(M);
|
||||
t ← ZeroExtend1(T);
|
||||
op1 ← ZeroExtend32(SignExtend32(Rm));
|
||||
op2 ← ZeroExtend32(SignExtend32(Rn));
|
||||
oldq ← q;
|
||||
q ← op2< 31 FOR 1 >;
|
||||
op2 ← ZeroExtend32(op2 << 1) ∨ t;
|
||||
IF (oldq = _m)
|
||||
IF (oldq = m)
|
||||
op2 ← op2 - op1;
|
||||
ELSE
|
||||
op2 ← op2 + op1;
|
||||
q ← (q ⊕ _m) ⊕ op2< 32 FOR 1 >;
|
||||
t ← 1 - (q ⊕ _m);
|
||||
q ← (q ⊕ m) ⊕ op2< 32 FOR 1 >;
|
||||
t ← 1 - (q ⊕ m);
|
||||
Rn ← Register(op2);
|
||||
Q ← Bit(q);
|
||||
T ← Bit(t);
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
1111001111111101
|
||||
Available only when PR=0
|
||||
sr ← ZeroExtend32(SR);
|
||||
sz ← ZeroExtend1(FPSCR.SZ);
|
||||
sz ← ZeroExtend1(SR.SZ);
|
||||
IF (FpuIsDisabled(sr) AND IsDelaySlot())
|
||||
THROW SLOTFPUDIS;
|
||||
IF (FpuIsDisabled(sr))
|
||||
THROW FPUDIS;
|
||||
sz ← sz ⊕ 1;
|
||||
FPSCR.SZ ← Bit(sz);
|
||||
SR.SZ ← Bit(sz);
|
||||
|
||||
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
op1 ← SignExtend32(Rm);
|
||||
dbr ← op1;
|
||||
dbr← op1;
|
||||
DBR ← Register(dbr);
|
||||
|
||||
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
op1 ← SignExtend32(Rm);
|
||||
vbr ← op1;
|
||||
vbr← op1;
|
||||
VBR ← Register(vbr);
|
||||
|
||||
@ -5,4 +5,8 @@ IF (FpuIsDisabled(sr) AND IsDelaySlot())
|
||||
THROW SLOTFPUDIS;
|
||||
IF (FpuIsDisabled(sr))
|
||||
THROW FPUDIS;
|
||||
FPSCR ← ZeroExtend32(op1);
|
||||
fps, pr, sz, fr ← UnpackFPSCR(op1);
|
||||
FPSCR ← ZeroExtend32(fps);
|
||||
SR.PR ← Bit(pr);
|
||||
SR.SZ ← Bit(sz);
|
||||
SR.FR ← Bit(fr);
|
||||
|
||||
@ -7,6 +7,10 @@ IF (FpuIsDisabled(sr))
|
||||
THROW FPUDIS;
|
||||
address ← ZeroExtend32(op1);
|
||||
value ← ReadMemory32(address);
|
||||
fps, pr, sz, fr ← UnpackFPSCR(value);
|
||||
op1 ← op1 + 4;
|
||||
Rm ← Register(op1);
|
||||
FPSCR ← ZeroExtend32(value);
|
||||
FPSCR ← ZeroExtend32(fps);
|
||||
SR.PR ← Bit(pr);
|
||||
SR.SZ ← Bit(sz);
|
||||
SR.FR ← Bit(fr);
|
||||
|
||||
20
sh4/LDTLB
20
sh4/LDTLB
@ -2,13 +2,13 @@
|
||||
md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
UTLB[MMUCR.URC].ASID ← PTEH.ASID;
|
||||
UTLB[MMUCR.URC].VPN ← PTEH.VPN;
|
||||
UTLB[MMUCR.URC].PPN ← PTEH.PPN;
|
||||
UTLB[MMUCR.URC].SZ ← PTEL.SZ1<<1 + PTEL.SZ0;
|
||||
UTLB[MMUCR.URC].SH ← PTEL.SH;
|
||||
UTLB[MMUCR.URC].PR ← PTEL.PR;
|
||||
UTLB[MMUCR.URC].WT ← PTEL.WT;
|
||||
UTLB[MMUCR.URC].C ← PTEL.C;
|
||||
UTLB[MMUCR.URC].D ← PTEL.D;
|
||||
UTLB[MMUCR.URC].V ← PTEL.V;
|
||||
UTLB[MMUCR.URC].ASID ← PTEH.ASID
|
||||
UTLB[MMUCR.URC].VPN ← PTEH.VPN
|
||||
UTLB[MMUCR.URC].PPN ← PTEH.PPN
|
||||
UTLB[MMUCR.URC].SZ ← PTEL.SZ1<<1 + PTEL.SZ0
|
||||
UTLB[MMUCR.URC].SH ← PTEL.SH
|
||||
UTLB[MMUCR.URC].PR ← PTEL.PR
|
||||
UTLB[MMUCR.URC].WT ← PTEL.WT
|
||||
UTLB[MMUCR.URC].C ← PTEL.C
|
||||
UTLB[MMUCR.URC].D ← PTEL.D
|
||||
UTLB[MMUCR.URC].V ← PTEL.V
|
||||
|
||||
@ -23,8 +23,7 @@ IF (((result ⊕ mac) ∧ (result ⊕ mul))< 63 FOR 1 > = 1)
|
||||
IF (mac< 63 FOR 1 > = 0)
|
||||
result ← (1 << 47) - 1;
|
||||
ELSE
|
||||
result ← - (1 << 47);
|
||||
ELSE
|
||||
ELSE result ← - (1 << 47);
|
||||
result ← SignedSaturate48(result);
|
||||
macl ← result;
|
||||
mach ← result >> 32;
|
||||
|
||||
@ -16,7 +16,6 @@ n_address ← n_address + 2;
|
||||
value1 ← SignExtend16(ReadMemory16(ZeroExtend32(m_address)));
|
||||
m_address ← m_address + 2;
|
||||
mul ← value2 × value1;
|
||||
result ← 0;
|
||||
IF (s = 1)
|
||||
{
|
||||
macl ← SignExtend32(macl) + mul;
|
||||
@ -24,7 +23,7 @@ temp ← SignedSaturate32(macl);
|
||||
IF (macl = temp)
|
||||
result ← (mach << 32) ∨ ZeroExtend32(macl);
|
||||
ELSE
|
||||
result ← (1 << 32) ∨ ZeroExtend32(temp);
|
||||
result ← (0x1 << 32) ∨ ZeroExtend32(temp);
|
||||
}
|
||||
ELSE
|
||||
result ← ((mach << 32) + macl) + mul;
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
1110nnnniiiiiiii
|
||||
imm ← SignExtend8(i);
|
||||
imm ← SignExtend8(s);
|
||||
op2 ← imm;
|
||||
Rn ← Register(op2);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
11000100dddddddd
|
||||
gbr ← SignExtend32(GBR);
|
||||
disp ← ZeroExtend8(d);
|
||||
disp ← ZeroExtend8(i);
|
||||
address ← ZeroExtend32(disp + gbr);
|
||||
r0 ← SignExtend8(ReadMemory8(address));
|
||||
R0 ← Register(r0);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
10000100mmmmdddd
|
||||
disp ← ZeroExtend4(d);
|
||||
disp ← ZeroExtend4(i);
|
||||
op2 ← SignExtend32(Rm);
|
||||
address ← ZeroExtend32(disp + op2);
|
||||
r0 ← SignExtend8(ReadMemory8(address));
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
11000000dddddddd
|
||||
gbr ← SignExtend32(GBR);
|
||||
r0 ← SignExtend32(R0);
|
||||
disp ← ZeroExtend8(d);
|
||||
disp ← ZeroExtend8(i);
|
||||
address ← ZeroExtend32(disp + gbr);
|
||||
WriteMemory8(address, r0);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
10000000nnnndddd
|
||||
r0 ← SignExtend32(R0);
|
||||
disp ← ZeroExtend4(d);
|
||||
disp ← ZeroExtend4(i);
|
||||
op2 ← SignExtend32(Rn);
|
||||
address ← ZeroExtend32(disp + op2);
|
||||
WriteMemory8(address, r0);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
11000110dddddddd
|
||||
gbr ← SignExtend32(GBR);
|
||||
disp ← ZeroExtend8(d) << 2;
|
||||
disp ← ZeroExtend8(i) << 2;
|
||||
address ← ZeroExtend32(disp + gbr);
|
||||
r0 ← SignExtend32(ReadMemory32(address));
|
||||
R0 ← Register(r0);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
1101nnnndddddddd
|
||||
pc ← SignExtend32(PC);
|
||||
disp ← ZeroExtend8(d) << 2;
|
||||
disp ← ZeroExtend8(i) << 2;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
address ← ZeroExtend32(disp + ((pc + 4) ∧ (~ 0x3)));
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
0101nnnnmmmmdddd
|
||||
disp ← ZeroExtend4(d) << 2;
|
||||
disp ← ZeroExtend4(i) << 2;
|
||||
op2 ← SignExtend32(Rm);
|
||||
address ← ZeroExtend32(disp + op2);
|
||||
op3 ← SignExtend32(ReadMemory32(address));
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
11000010dddddddd
|
||||
gbr ← SignExtend32(GBR);
|
||||
r0 ← SignExtend32(R0);
|
||||
disp ← ZeroExtend8(d) << 2;
|
||||
disp ← ZeroExtend8(i) << 2;
|
||||
address ← ZeroExtend32(disp + gbr);
|
||||
WriteMemory32(address, r0);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
0001nnnnmmmmdddd
|
||||
op1 ← SignExtend32(Rm);
|
||||
disp ← ZeroExtend4(d) << 2;
|
||||
disp ← ZeroExtend4(i) << 2;
|
||||
op3 ← SignExtend32(Rn);
|
||||
address ← ZeroExtend32(disp + op3);
|
||||
WriteMemory32(address, op1);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
11000101dddddddd
|
||||
gbr ← SignExtend32(GBR);
|
||||
disp ← ZeroExtend8(d) << 1;
|
||||
disp ← ZeroExtend8(i) << 1;
|
||||
address ← ZeroExtend32(disp + gbr);
|
||||
r0 ← SignExtend16(ReadMemory16(address));
|
||||
R0 ← Register(r0);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
1001nnnndddddddd
|
||||
pc ← SignExtend32(PC);
|
||||
disp ← ZeroExtend8(d) << 1;
|
||||
disp ← ZeroExtend8(i) << 1;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
address ← ZeroExtend32(disp + (pc + 4));
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
10000101mmmmdddd
|
||||
disp ← ZeroExtend4(d) << 1;
|
||||
disp ← ZeroExtend4(i) << 1;
|
||||
op2 ← SignExtend32(Rm);
|
||||
address ← ZeroExtend32(disp + op2);
|
||||
r0 ← SignExtend16(ReadMemory16(address));
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
11000001dddddddd
|
||||
gbr ← SignExtend32(GBR);
|
||||
r0 ← SignExtend32(R0);
|
||||
disp ← ZeroExtend8(d) << 1;
|
||||
disp ← ZeroExtend8(i) << 1;
|
||||
address ← ZeroExtend32(disp + gbr);
|
||||
WriteMemory16(address, r0);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
10000001nnnndddd
|
||||
r0 ← SignExtend32(R0);
|
||||
disp ← ZeroExtend4(d) << 1;
|
||||
disp ← ZeroExtend4(i) << 1;
|
||||
op2 ← SignExtend32(Rn);
|
||||
address ← ZeroExtend32(disp + op2);
|
||||
WriteMemory16(address, r0);
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
11000111dddddddd
|
||||
pc ← SignExtend32(PC);
|
||||
disp ← ZeroExtend8(d) << 2;
|
||||
disp ← ZeroExtend8(i) << 2;
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
r0 ← disp + ((pc + 4) ∧ (~ 0x3));
|
||||
|
||||
@ -8,7 +8,7 @@ THROW WTLBMISS, op1;
|
||||
IF (MMU() AND WriteProhibited(op1))
|
||||
THROW WRITEPROT, op1;
|
||||
IF (MMU() AND NOT DirtyBit(op1))
|
||||
THROW FIRSTWRITE, op1;
|
||||
THROW FIRSTWRITE, op1
|
||||
ALLOCO(op1);
|
||||
address ← ZeroExtend32(op1);
|
||||
WriteMemory32(op1, r0);
|
||||
|
||||
@ -7,5 +7,5 @@ THROW WTLBMISS, op1;
|
||||
IF (MMU() AND WriteProhibited(op1))
|
||||
THROW WRITEPROT, op1;
|
||||
IF (MMU() AND NOT DirtyBit(op1))
|
||||
THROW FIRSTWRITE, op1;
|
||||
THROW FIRSTWRITE, op1
|
||||
OCBI(op1);
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
0000nnnn10000011
|
||||
op1 ← SignExtend32(Rn);
|
||||
IF (AddressUnavailable(op1))
|
||||
THROW RADDERR, op1;
|
||||
THROW RADDERR, op1
|
||||
IF (NOT (MMU() AND DataAccessMiss(op1)))
|
||||
IF (NOT (MMU() AND ReadProhibited(op1)))
|
||||
PREF(op1);
|
||||
|
||||
2
sh4/RTE
2
sh4/RTE
@ -3,7 +3,7 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
ssr ← SignExtend32(SSR);
|
||||
pc ← SignExtend32(PC);
|
||||
pc ← SignExtend32(PC)
|
||||
IF (IsDelaySlot())
|
||||
THROW ILLSLOT;
|
||||
target ← pc;
|
||||
|
||||
@ -2,4 +2,4 @@
|
||||
md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
SLEEP();
|
||||
SLEEP()
|
||||
|
||||
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
dbr ← SignExtend32(DBR);
|
||||
op1 ← dbr;
|
||||
op1 ← dbr
|
||||
Rn ← Register(op1);
|
||||
|
||||
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
sgr ← SignExtend32(SGR);
|
||||
op1 ← sgr;
|
||||
op1 ← sgr
|
||||
Rn ← Register(op1);
|
||||
|
||||
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
spc ← SignExtend32(SPC);
|
||||
op1 ← spc;
|
||||
op1 ← spc
|
||||
Rn ← Register(op1);
|
||||
|
||||
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
sr ← SignExtend32(SR);
|
||||
op1 ← sr;
|
||||
op1 ← sr
|
||||
Rn ← Register(op1);
|
||||
|
||||
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
ssr ← SignExtend32(SSR);
|
||||
op1 ← ssr;
|
||||
op1 ← ssr
|
||||
Rn ← Register(op1);
|
||||
|
||||
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
|
||||
IF (md = 0)
|
||||
THROW RESINST;
|
||||
vbr ← SignExtend32(VBR);
|
||||
op1 ← vbr;
|
||||
op1 ← vbr
|
||||
Rn ← Register(op1);
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
0100nnnn00011011
|
||||
op1 ← SignExtend32(Rn);
|
||||
address ← ZeroExtend32(op1);
|
||||
OCBP(address);
|
||||
OCBP(address)
|
||||
value ← ZeroExtend8(ReadMemory8(address));
|
||||
t ← INT (value = 0);
|
||||
value ← value ∨ (1 << 7);
|
||||
|
||||
18
syntax.txt
18
syntax.txt
@ -12,20 +12,16 @@ identifier-contine:
|
||||
primary-expression:
|
||||
identifier
|
||||
constant
|
||||
string-literal
|
||||
"(" expression ")"
|
||||
|
||||
postfix-expression:
|
||||
primary-expression
|
||||
postfix-expression "[" expression "]"
|
||||
postfix-expression "(" argument-expression-list? ")"
|
||||
postfix-expression "<" for-expression ">"
|
||||
postfix-expression "." identifier
|
||||
postfix-expression "<" primary-expression "FOR" primary-expression ">"
|
||||
postfix-expression "<" primary-expression ">"
|
||||
|
||||
for-expression:
|
||||
primary-expression
|
||||
primary-expression "FOR" primary-expression
|
||||
|
||||
argument-expression-list:
|
||||
assignment-expression-list:
|
||||
assignment-expression
|
||||
argument-expression-list "," assignment-expression
|
||||
|
||||
@ -90,7 +86,7 @@ logical-OR-expression:
|
||||
|
||||
assignment-expression:
|
||||
logical-OR-expression
|
||||
unary-expression "←" assignment-expression
|
||||
identifier "←" assignment-expression
|
||||
|
||||
expression:
|
||||
assignment-expression
|
||||
@ -107,7 +103,6 @@ unlabeled-statement:
|
||||
primary-block:
|
||||
compound-statement
|
||||
selection-statement
|
||||
throw-statement
|
||||
|
||||
secondary-block:
|
||||
statement
|
||||
@ -128,6 +123,3 @@ expression-statement:
|
||||
selection-statement:
|
||||
"IF" "(" expression ")" secondary-block
|
||||
"IF" "(" expression ")" secondary-block "ELSE" secondary-block
|
||||
|
||||
throw-statement:
|
||||
"THROW" secondary-block
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user