diff --git a/ast_to_c_source.py b/ast_to_c_source.py
new file mode 100644
index 0000000..35c0b3f
--- /dev/null
+++ b/ast_to_c_source.py
@@ -0,0 +1,278 @@
+from dataclasses import dataclass
+
+from parser import Tree
+from lexer import Identifier, Punctuator, IntegerConstant
+import identifier_substitution
+
+def argument_list(tree):
+    yield from generate(tree.children[0])
+    yield ", "
+    yield from generate(tree.children[1])
+
+def assignment_list(tree):
+    yield from generate(tree.children[0])
+    yield ", "
+    yield from generate(tree.children[1])
+
+def assignment(tree):
+    yield from generate(tree.children[0])
+    yield " = "
+    yield from generate(tree.children[1])
+
+def bit_extraction(tree):
+    yield "bit_extract("
+    yield from generate(tree.children[0])
+    yield ", "
+    yield from generate(tree.children[1])
+    yield ")"
+
+def bitwise_and(tree):
+    yield from generate(tree.children[0])
+    yield " & "
+    yield from generate(tree.children[1])
+
+def bitwise_or(tree):
+    yield from generate(tree.children[0])
+    yield " | "
+    yield from generate(tree.children[1])
+
+def bitwise_xor(tree):
+    yield from generate(tree.children[0])
+    yield " ^ "
+    yield from generate(tree.children[1])
+
+def block_item_list(tree):
+    yield from generate(tree.children[0])
+    yield from generate(tree.children[1])
+
+def compound_statement(tree):
+    yield "\n{\n"
+    if tree.children:
+        yield from generate(tree.children[0])
+    yield "}\n"
+
+def expression_statement(tree):
+    yield from generate(tree.children[0])
+    yield ";\n"
+
+def for_expression(tree):
+    yield from generate(tree.children[0])
+    yield ", "
+    if len(tree.children) > 1:
+        yield from generate(tree.children[1])
+    else:
+        yield "1"
+
+def function_call(tree):
+    assert len(tree.children) in {1, 2}
+    yield from generate(tree.children[0])
+    yield "("
+    if len(tree.children) == 2:
+        yield from generate(tree.children[1])
+    yield ")"
+
+def grouping(tree):
+    yield "("
+    yield from generate(tree.children[0])
+    yield ")"
+
+def _if(tree):
+    yield "if ("
+    yield from generate(tree.children[0])
+    yield ") "
+    yield from generate(tree.children[1])
+
+def if_else(tree):
+    yield "if ("
+    yield from generate(tree.children[0])
+    yield ") "
+    yield from generate(tree.children[1])
+    yield "else "
+    yield from generate(tree.children[2])
+
+def logical_and(tree):
+    yield from generate(tree.children[0])
+    yield " && "
+    yield from generate(tree.children[1])
+
+def logical_or(tree):
+    yield from generate(tree.children[0])
+    yield " || "
+    yield from generate(tree.children[1])
+
+def member(tree):
+    yield from generate(tree.children[0])
+    yield "."
+    yield from generate(tree.children[1])
+
+def subscript(tree):
+    yield from generate(tree.children[0])
+    yield "["
+    yield from generate(tree.children[1])
+    yield "]"
+
+def throw(tree):
+    yield "return "
+    yield from generate(tree.children[0])
+    yield "(state);\n"
+
+def throw_arg(tree):
+    yield "return "
+    yield from generate(tree.children[0])
+    yield "(state, "
+    yield from generate(tree.children[1])
+    yield ");\n"
+
+def unary_complement(tree):
+    yield from "~"
+    yield from generate(tree.children[0])
+
+def unary_int(tree):
+    yield "unary_int("
+    yield from generate(tree.children[0])
+    yield ")"
+
+def unary_negation(tree):
+    yield "-"
+    yield from generate(tree.children[0])
+
+def unary_not(tree):
+    yield "!"
+    yield from generate(tree.children[0])
+
+#
+def addition(tree):
+    yield from generate(tree.children[0])
+    yield " + "
+    yield from generate(tree.children[1])
+
+def division(tree):
+    yield from generate(tree.children[0])
+    yield " / "
+    yield from generate(tree.children[1])
+
+def equality_equal(tree):
+    yield from generate(tree.children[0])
+    yield " == "
+    yield from generate(tree.children[1])
+
+def equality_not_equal(tree):
+    yield from generate(tree.children[0])
+    yield " != "
+    yield from generate(tree.children[1])
+
+def greater_than(tree):
+    yield from generate(tree.children[0])
+    yield " > "
+    yield from generate(tree.children[1])
+
+def greater_than_equal(tree):
+    yield from generate(tree.children[0])
+    yield " >= "
+    yield from generate(tree.children[1])
+
+def left_shift(tree):
+    yield from generate(tree.children[0])
+    # hack for left shift by LHS constant
+    if type(tree.children[0]) is IntegerConstant:
+        yield "LL"
+    yield " << "
+    yield from generate(tree.children[1])
+
+def less_than(tree):
+    yield from generate(tree.children[0])
+    yield " < "
+    yield from generate(tree.children[1])
+
+def less_than_equal(tree):
+    yield from generate(tree.children[0])
+    yield " <= "
+    yield from generate(tree.children[1])
+
+def multiplication(tree):
+    yield from generate(tree.children[0])
+    yield " * "
+    yield from generate(tree.children[1])
+
+def right_shift(tree):
+    yield from generate(tree.children[0])
+    yield " >> "
+    yield from generate(tree.children[1])
+
+def subtraction(tree):
+    yield from generate(tree.children[0])
+    yield " - "
+    yield from generate(tree.children[1])
+
+def declaration(tree):
+    assert len(tree.children) >= 2, tree
+    yield from generate(tree.children[0])
+    yield " "
+    for child in tree.children[1:-1]:
+        yield from generate(child)
+        yield ", "
+    yield from generate(tree.children[-1])
+
+def unary_reference(tree):
+    yield "&"
+    assert len(tree.children) == 1
+    yield from generate(tree.children[0])
+
+def identifier(token):
+    yield token.token
+
+def constant(elem):
+    yield elem.token.lower()
+
+def generate(elem):
+    mapping = {
+        "argument_list": argument_list,
+        "assignment_list": assignment_list,
+        "assignment": assignment,
+        "bit_extraction": bit_extraction,
+        "bitwise_and": bitwise_and,
+        "bitwise_or": bitwise_or,
+        "bitwise_xor": bitwise_xor,
+        "block_item_list": block_item_list,
+        "compound_statement": compound_statement,
+        "expression_statement": expression_statement,
+        "for_expression": for_expression,
+        "function_call": function_call,
+        "grouping": grouping,
+        "if": _if,
+        "if_else": if_else,
+        "logical_and": logical_and,
+        "logical_or": logical_or,
+        "member": member,
+        "subscript": subscript,
+        "throw": throw,
+        "throw_arg": throw_arg,
+        "unary_complement": unary_complement,
+        "unary_int": unary_int,
+        "unary_negation": unary_negation,
+        "unary_not": unary_not,
+        #
+        "addition": addition,
+        "division": division,
+        "equality_equal": equality_equal,
+        "equality_not_equal": equality_not_equal,
+        "greater_than": greater_than,
+        "greater_than_equal": greater_than_equal,
+        "left_shift": left_shift,
+        "less_than": less_than,
+        "less_than_equal": less_than_equal,
+        "multiplication": multiplication,
+        "right_shift": right_shift,
+        "subtraction": subtraction,
+        #
+        "declaration": declaration,
+        "unary_reference": unary_reference,
+    }
+    if type(elem) is Tree:
+        yield from mapping[elem.operation](elem)
+    elif type(elem) is Identifier:
+        yield from identifier(elem)
+    elif type(elem) is IntegerConstant:
+        yield from constant(elem)
+    else:
+        assert False, type(elem)
diff --git a/ast_transformers.py b/ast_transformers.py
new file mode 100644
index 0000000..a9b2294
--- /dev/null
+++ b/ast_transformers.py
@@ -0,0 +1,194 @@
+from pprint import pprint
+
+from parser import Tree
+from lexer import Identifier, Punctuator, IntegerConstant
+
+import identifier_substitution
+
+def find_locals__walk_assignment_lhs(tree):
+    if type(tree) is Tree:
+        for child in tree.children:
+            yield from find_locals__walk_assignment_lhs(child)
+    elif type(tree) is Identifier:
+        token = tree
+        if token.token not in {'m', 'n', 'i', 'd'}:
+            if token.token.lower() == token.token:
+                assert token.token not in identifier_substitution.mapping, token.token
+                yield token.token
+
+def find_locals__walk_assignment(tree):
+    if type(tree) is Tree:
+        if tree.operation == "assignment":
+            yield from find_locals__walk_assignment_lhs(tree.children[0])
+            for child in tree.children[1:]:
+                yield from find_locals__walk_assignment(child)
+        else:
+            for child in tree.children:
+                yield from find_locals__walk_assignment(child)
+
+def transform_assignment_list__collect_identifiers(tree, operation):
+    if type(tree) == Tree:
+        assert tree.operation == operation, pprint(tree)
+        for child in tree.children:
+            yield from transform_assignment_list__collect_identifiers(child, operation)
+    elif type(tree) == Identifier:
+        yield tree.token
+
+def transform_assignment_list__assignment(tree):
+    assert tree.operation == "assignment", tree
+    # first, collect the lhs
+    if type(tree.children[0]) is not Tree or tree.children[0].operation != 'assignment_list':
+        return tree
+
+    lhs = transform_assignment_list__collect_identifiers(tree.children[0], "assignment_list")
+
+    assert tree.children[1].operation == "function_call", (tree.children[1].operation, pprint(tree))
+    function_call = tree.children[1]
+    rhs = list(transform_assignment_list__collect_identifiers(function_call.children[1], "argument_list"))
+
+    common = []
+    lhs_only = []
+    for l_token in lhs:
+        if l_token in rhs:
+            common.append(l_token)
+        else:
+            lhs_only.append(l_token)
+
+    def gen_argument_list(tree):
+        if type(tree) is Tree:
+            assert tree.operation == 'argument_list'
+            return Tree(
+                operation=tree.operation,
+                children=[gen_argument_list(child) for child in tree.children]
+            )
+        elif type(tree) is Identifier:
+            if tree.token in common:
+                return Tree(
+                    operation="unary_reference",
+                    children=[tree]
+                )
+            else:
+                return tree
+        else:
+            return tree
+
+    def gen_function_call():
+        return Tree(
+            operation="function_call",
+            children=[
+                function_call.children[0],
+                gen_argument_list(function_call.children[1]),
+            ]
+        )
+
+    if len(lhs_only) == 0:
+        return gen_function_call()
+    elif len(lhs_only) == 1:
+        return Tree(
+            operation="assignment",
+            children=[Identifier(line=-1, token=lhs_only[0]), gen_function_call()]
+        )
+    else:
+        assert False, (lhs_only, common, pprint(tree))
+
+def transform_assignment_list(tree):
+    if type(tree) is Tree:
+        if tree.operation == "assignment":
+            return transform_assignment_list__assignment(tree)
+        else:
+            return Tree(
+                operation=tree.operation,
+                children=[
+                    transform_assignment_list(child)
+                    for child in tree.children
+                ]
+            )
+    else:
+        return tree
+
+def transform_local_declarations(statements):
+    all_locals = []
+    for statement in statements:
+        all_locals.extend(find_locals__walk_assignment(statement))
+
+    set_locals = []
+    for local in all_locals:
+        if not any(s.token == local for s in set_locals):
+            set_locals.append(Identifier(line=-1, token=local))
+
+    if set_locals:
+        yield Tree(operation="expression_statement",
+                   children=[Tree(operation="declaration",
+                                  children=[Identifier(line=-1, token="int64_t"), *set_locals])])
+
+def transform_identifiers(tree):
+    if type(tree) is Tree:
+        return Tree(
+            operation=tree.operation,
+            children=[transform_identifiers(child) for child in tree.children]
+        )
+    elif type(tree) is Identifier:
+        token = tree
+        if token.token in identifier_substitution.mapping:
+            return Identifier(
+                line=token.line,
+                token=identifier_substitution.mapping[token.token]
+            )
+        else:
+            return token
+    else:
+        return tree
+
+require_extra_arguments = {
+    "IsDelaySlot": "state",
+    "SLEEP": "state",
+    "OCBP" : "state",
+    "WriteMemory8" : "map",
+    "WriteMemory16": "map",
+    "WriteMemory32": "map",
+    "ReadMemory8"  : "map",
+    "ReadMemory16" : "map",
+    "ReadMemory32" : "map",
+}
+
+def transform_function_arguments(tree):
+    def arguments(arg):
+        identifier = Identifier(line=tree.children[0].line, token=arg)
+        if len(tree.children) == 1:
+            return identifier
+        else:
+            assert len(tree.children) == 2, tree
+            return Tree(
+                operation='argument_list',
+                children=[
+                    identifier,
+                    transform_function_arguments(tree.children[1])
+                ]
+            )
+
+    if type(tree) is Tree:
+        if tree.operation == "function_call":
+            assert type(tree.children[0]) is Identifier
+            if tree.children[0].token in require_extra_arguments:
+                return Tree(
+                    operation=tree.operation,
+                    children=[
+                        tree.children[0],
+                        arguments(require_extra_arguments[tree.children[0].token])
+                    ]
+                )
+        return Tree(
+            operation=tree.operation,
+            children=[transform_function_arguments(child) for child in tree.children]
+        )
+    else:
+        return tree
+
+def transform_statements(statements):
+    yield from transform_local_declarations(statements)
+
+    for statement in statements:
+        statement = transform_assignment_list(statement)
+        statement = transform_function_arguments(statement)
+        statement = transform_identifiers(statement)
+        yield statement
diff --git a/bitfield.py b/bitfield.py
deleted file mode 100644
index 3eb40e2..0000000
--- a/bitfield.py
+++ /dev/null
@@ -1,74 +0,0 @@
-sr_bits = (
-    ("T"    , 0 , 1),   # true/false condition
-    ("S"    , 1 , 1),   # saturation
-    ("IMASK", 4 , 4),   # interrupt mask level, 4 bits
-    ("Q"    , 8 , 1),   # state for divide step
-    ("M"    , 9 , 1),   # state for divide step
-    ("FD"   , 15, 1),  # FPU disable
-    ("BL"   , 28, 1),  # Exception/interrupt block bit
-    ("RB"   , 29, 1),  # General register bank specifier in privileged mode
-    ("MD"   , 30, 1),  # Processor mode
-)
-
-#define FPSCR__RM                      (1 << 0 ) /* Rounding mode */
-#define FPSCR__FLAG_INEXACT            (1 << 2 )
-#define FPSCR__FLAG_UNDERFLOW          (1 << 3 )
-#define FPSCR__FLAG_OVERFLOW           (1 << 4 )
-#define FPSCR__FLAG_DIVISION_BY_ZERO   (1 << 5 )
-#define FPSCR__FLAG_INVALID_OPERATION  (1 << 6 )
-#define FPSCR__ENABLE_INEXACT          (1 << 7 )
-#define FPSCR__ENABLE_UNDERFLOW        (1 << 8 )
-#define FPSCR__ENABLE_OVERFLOW         (1 << 9 )
-#define FPSCR__ENABLE_DIVISION_BY_ZERO (1 << 10)
-#define FPSCR__ENABLE_INVALID          (1 << 11)
-#define FPSCR__CAUSE_INEXACT           (1 << 12)
-#define FPSCR__CAUSE_UNDERFLOW         (1 << 13)
-#define FPSCR__CAUSE_OVERFLOW          (1 << 14)
-#define FPSCR__CAUSE_DIVISION_BY_ZERO  (1 << 15)
-#define FPSCR__CAUSE_INVALID           (1 << 16)
-#define FPSCR__CAUSE_FPU_ERROR         (1 << 17)
-#define FPSCR__DN                      (1 << 18) /* Denormalization mode */
-#define FPSCR__PR                      (1 << 19) /* Precision mode */
-#define FPSCR__SZ                      (1 << 20) /* Transfer size mode */
-#define FPSCR__FR                      (1 << 21) /* Floating-point register bank */
-
-def generate_bitfield(bits, start=0, end=31):
-    res = 0
-    current = start
-    for name, index, length in bits:
-        if index != current:
-            size = index - current
-            yield f"_res{res}", size
-            res += 1
-        yield name, length
-        current = index + 1
-
-    end_len = end + 1
-    if current != end_len:
-        yield f"_res{res}", end_len - current
-
-def generate_bitfield_little(bits):
-    return generate_bitfield(bits)
-
-def generate_bitfield_big(bits):
-    return reversed(list(generate_bitfield(bits)))
-
-def generate(struct_name, bits):
-    yield "#pragma once"
-    yield ""
-    yield "#include <stdint.h>"
-    yield ""
-    yield f"struct {struct_name} {{"
-    yield "#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__"
-    for name, size in generate_bitfield_little(bits):
-        yield f"  uint32_t {name.lower()} : {size};"
-    yield "#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__"
-    for name, size in generate_bitfield_big(bits):
-        yield f"  uint32_t {name.lower()} : {size};"
-    yield "#else"
-    yield '# error "unsupported endianness"'
-    yield "#endif"
-    yield "};"
-
-if __name__ == "__main__":
-    print('\n'.join(generate("sr_bits", sr_bits)))
diff --git a/build.sh b/build.sh
index 813ace2..ce045a1 100644
--- a/build.sh
+++ b/build.sh
@@ -1,3 +1,3 @@
-PYTHONPATH=python/ python transform.py c/impl.c c/impl.h
+PYTHONPATH=python/ python generate_impl.py c/impl.c c/impl.h
 PYTHONPATH=python/ python generate_decoder.py c/decode_execute.c c/decode_print.c
-PYTHONPATH=python/ python bitfield.py > c/sr_bits.h
+PYTHONPATH=python/ python generate_bits.py > c/status_bits.h
diff --git a/c/impl.c b/c/impl.c
index b270534..aaa872f 100644
--- a/c/impl.c
+++ b/c/impl.c
@@ -6,8 +6,9 @@
 /* MOV #imm,Rn */
 void mov__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i, const uint32_t n)
 {
-  int64_t imm = sign_extend8(i);
-  int64_t op2 = imm;
+  int64_t imm, op2;
+  imm = sign_extend8(i);
+  op2 = imm;
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -17,11 +18,12 @@ void mov__immediate(struct architectural_state * state, struct memory_map * map,
 /* MOV.W @(disp,PC),Rn */
 void mov_w__pc_relative_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d, const uint32_t n)
 {
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t disp = zero_extend8(d) << 1;
+  int64_t pc, disp, address, op2;
+  pc = sign_extend32(state->pc[0]);
+  disp = zero_extend8(d) << 1;
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t address = zero_extend32(disp + (pc + 4));
-  int64_t op2 = sign_extend16(read_memory16(map, address));
+  address = zero_extend32(disp + (pc + 4));
+  op2 = sign_extend16(read_memory16(map, address));
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -31,11 +33,12 @@ void mov_w__pc_relative_with_displacement(struct architectural_state * state, st
 /* MOV.L @(disp,PC),Rn */
 void mov_l__pc_relative_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d, const uint32_t n)
 {
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t disp = zero_extend8(d) << 2;
+  int64_t pc, disp, address, op2;
+  pc = sign_extend32(state->pc[0]);
+  disp = zero_extend8(d) << 2;
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t address = zero_extend32(disp + ((pc + 4) & (~0x3)));
-  int64_t op2 = sign_extend32(read_memory32(map, address));
+  address = zero_extend32(disp + ((pc + 4) & (~0x3)));
+  op2 = sign_extend32(read_memory32(map, address));
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -45,8 +48,9 @@ void mov_l__pc_relative_with_displacement(struct architectural_state * state, st
 /* MOV Rm,Rn */
 void mov__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = op1;
+  int64_t op1, op2;
+  op1 = zero_extend32(REG(state, m));
+  op2 = op1;
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -56,9 +60,10 @@ void mov__source_and_destination_operands(struct architectural_state * state, st
 /* MOV.B Rm,@Rn */
 void mov_b__store_register_direct_data_transfer(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op2);
+  int64_t op1, op2, address;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(op2);
   write_memory8(map, address, op1);
 
   state->is_delay_slot = false;
@@ -68,9 +73,10 @@ void mov_b__store_register_direct_data_transfer(struct architectural_state * sta
 /* MOV.W Rm,@Rn */
 void mov_w__store_register_direct_data_transfer(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op2);
+  int64_t op1, op2, address;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(op2);
   write_memory16(map, address, op1);
 
   state->is_delay_slot = false;
@@ -80,9 +86,10 @@ void mov_w__store_register_direct_data_transfer(struct architectural_state * sta
 /* MOV.L Rm,@Rn */
 void mov_l__store_register_direct_data_transfer(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op2);
+  int64_t op1, op2, address;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(op2);
   write_memory32(map, address, op1);
 
   state->is_delay_slot = false;
@@ -92,9 +99,10 @@ void mov_l__store_register_direct_data_transfer(struct architectural_state * sta
 /* MOV.B @Rm,Rn */
 void mov_b__load_register_direct_data_transfer(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t op2 = sign_extend8(read_memory8(map, address));
+  int64_t op1, address, op2;
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  op2 = sign_extend8(read_memory8(map, address));
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -104,9 +112,10 @@ void mov_b__load_register_direct_data_transfer(struct architectural_state * stat
 /* MOV.W @Rm,Rn */
 void mov_w__load_register_direct_data_transfer(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t op2 = sign_extend16(read_memory16(map, address));
+  int64_t op1, address, op2;
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  op2 = sign_extend16(read_memory16(map, address));
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -116,9 +125,10 @@ void mov_w__load_register_direct_data_transfer(struct architectural_state * stat
 /* MOV.L @Rm,Rn */
 void mov_l__load_register_direct_data_transfer(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t op2 = sign_extend32(read_memory32(map, address));
+  int64_t op1, address, op2;
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  op2 = sign_extend32(read_memory32(map, address));
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -128,9 +138,10 @@ void mov_l__load_register_direct_data_transfer(struct architectural_state * stat
 /* MOV.B Rm,@-Rn */
 void mov_b__store_direct_data_transfer_from_register(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op2 - 1);
+  int64_t op1, op2, address;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(op2 - 1);
   write_memory8(map, address, op1);
   op2 = address;
   REG(state, n) = _register(op2);
@@ -142,9 +153,10 @@ void mov_b__store_direct_data_transfer_from_register(struct architectural_state
 /* MOV.W Rm,@-Rn */
 void mov_w__store_direct_data_transfer_from_register(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op2 - 2);
+  int64_t op1, op2, address;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(op2 - 2);
   write_memory16(map, address, op1);
   op2 = address;
   REG(state, n) = _register(op2);
@@ -156,9 +168,10 @@ void mov_w__store_direct_data_transfer_from_register(struct architectural_state
 /* MOV.L Rm,@-Rn */
 void mov_l__store_direct_data_transfer_from_register(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op2 - 4);
+  int64_t op1, op2, address;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(op2 - 4);
   write_memory32(map, address, op1);
   op2 = address;
   REG(state, n) = _register(op2);
@@ -170,11 +183,12 @@ void mov_l__store_direct_data_transfer_from_register(struct architectural_state
 /* MOV.B @Rm+,Rn */
 void mov_b__load_direct_data_transfer_from_register(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t m_field = zero_extend4(m);
-  int64_t n_field = zero_extend4(n);
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t op2 = sign_extend8(read_memory8(map, address));
+  int64_t m_field, n_field, op1, address, op2;
+  m_field = zero_extend4(m);
+  n_field = zero_extend4(n);
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  op2 = sign_extend8(read_memory8(map, address));
   if (m_field == n_field) op1 = op2;
   else op1 = op1 + 1;
   REG(state, m) = _register(op1);
@@ -187,11 +201,12 @@ void mov_b__load_direct_data_transfer_from_register(struct architectural_state *
 /* MOV.W @Rm+,Rn */
 void mov_w__load_direct_data_transfer_from_register(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t m_field = zero_extend4(m);
-  int64_t n_field = zero_extend4(n);
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t op2 = sign_extend16(read_memory16(map, address));
+  int64_t m_field, n_field, op1, address, op2;
+  m_field = zero_extend4(m);
+  n_field = zero_extend4(n);
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  op2 = sign_extend16(read_memory16(map, address));
   if (m_field == n_field) op1 = op2;
   else op1 = op1 + 2;
   REG(state, m) = _register(op1);
@@ -204,11 +219,12 @@ void mov_w__load_direct_data_transfer_from_register(struct architectural_state *
 /* MOV.L @Rm+,Rn */
 void mov_l__load_direct_data_transfer_from_register(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t m_field = zero_extend4(m);
-  int64_t n_field = zero_extend4(n);
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t op2 = sign_extend32(read_memory32(map, address));
+  int64_t m_field, n_field, op1, address, op2;
+  m_field = zero_extend4(m);
+  n_field = zero_extend4(n);
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  op2 = sign_extend32(read_memory32(map, address));
   if (m_field == n_field) op1 = op2;
   else op1 = op1 + 4;
   REG(state, m) = _register(op1);
@@ -221,10 +237,11 @@ void mov_l__load_direct_data_transfer_from_register(struct architectural_state *
 /* MOV.B R0,@(disp,Rn) */
 void mov_b__store_register_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d, const uint32_t n)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t disp = zero_extend4(d);
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(disp + op2);
+  int64_t r0, disp, op2, address;
+  r0 = sign_extend32(REG(state, 0));
+  disp = zero_extend4(d);
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(disp + op2);
   write_memory8(map, address, r0);
 
   state->is_delay_slot = false;
@@ -234,10 +251,11 @@ void mov_b__store_register_indirect_with_displacement(struct architectural_state
 /* MOV.W R0,@(disp,Rn) */
 void mov_w__store_register_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d, const uint32_t n)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t disp = zero_extend4(d) << 1;
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(disp + op2);
+  int64_t r0, disp, op2, address;
+  r0 = sign_extend32(REG(state, 0));
+  disp = zero_extend4(d) << 1;
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(disp + op2);
   write_memory16(map, address, r0);
 
   state->is_delay_slot = false;
@@ -247,10 +265,11 @@ void mov_w__store_register_indirect_with_displacement(struct architectural_state
 /* MOV.L Rm,@(disp,Rn) */
 void mov_l__store_register_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t d, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t disp = zero_extend4(d) << 2;
-  int64_t op3 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(disp + op3);
+  int64_t op1, disp, op3, address;
+  op1 = sign_extend32(REG(state, m));
+  disp = zero_extend4(d) << 2;
+  op3 = sign_extend32(REG(state, n));
+  address = zero_extend32(disp + op3);
   write_memory32(map, address, op1);
 
   state->is_delay_slot = false;
@@ -260,10 +279,11 @@ void mov_l__store_register_indirect_with_displacement(struct architectural_state
 /* MOV.B @(disp,Rm),R0 */
 void mov_b__load_register_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d, const uint32_t m)
 {
-  int64_t disp = zero_extend4(d);
-  int64_t op2 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(disp + op2);
-  int64_t r0 = sign_extend8(read_memory8(map, address));
+  int64_t disp, op2, address, r0;
+  disp = zero_extend4(d);
+  op2 = sign_extend32(REG(state, m));
+  address = zero_extend32(disp + op2);
+  r0 = sign_extend8(read_memory8(map, address));
   REG(state, 0) = _register(r0);
 
   state->is_delay_slot = false;
@@ -273,10 +293,11 @@ void mov_b__load_register_indirect_with_displacement(struct architectural_state
 /* MOV.W @(disp,Rm),R0 */
 void mov_w__load_register_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d, const uint32_t m)
 {
-  int64_t disp = zero_extend4(d) << 1;
-  int64_t op2 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(disp + op2);
-  int64_t r0 = sign_extend16(read_memory16(map, address));
+  int64_t disp, op2, address, r0;
+  disp = zero_extend4(d) << 1;
+  op2 = sign_extend32(REG(state, m));
+  address = zero_extend32(disp + op2);
+  r0 = sign_extend16(read_memory16(map, address));
   REG(state, 0) = _register(r0);
 
   state->is_delay_slot = false;
@@ -286,10 +307,11 @@ void mov_w__load_register_indirect_with_displacement(struct architectural_state
 /* MOV.L @(disp,Rm),Rn */
 void mov_l__load_register_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d, const uint32_t m, const uint32_t n)
 {
-  int64_t disp = zero_extend4(d) << 2;
-  int64_t op2 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(disp + op2);
-  int64_t op3 = sign_extend32(read_memory32(map, address));
+  int64_t disp, op2, address, op3;
+  disp = zero_extend4(d) << 2;
+  op2 = sign_extend32(REG(state, m));
+  address = zero_extend32(disp + op2);
+  op3 = sign_extend32(read_memory32(map, address));
   REG(state, n) = _register(op3);
 
   state->is_delay_slot = false;
@@ -299,10 +321,11 @@ void mov_l__load_register_indirect_with_displacement(struct architectural_state
 /* MOV.B Rm,@(R0,Rn) */
 void mov_b__store_indexed_register_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(r0 + op2);
+  int64_t r0, op1, op2, address;
+  r0 = sign_extend32(REG(state, 0));
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(r0 + op2);
   write_memory8(map, address, op1);
 
   state->is_delay_slot = false;
@@ -312,10 +335,11 @@ void mov_b__store_indexed_register_indirect(struct architectural_state * state,
 /* MOV.W Rm,@(R0,Rn) */
 void mov_w__store_indexed_register_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(r0 + op2);
+  int64_t r0, op1, op2, address;
+  r0 = sign_extend32(REG(state, 0));
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(r0 + op2);
   write_memory16(map, address, op1);
 
   state->is_delay_slot = false;
@@ -325,10 +349,11 @@ void mov_w__store_indexed_register_indirect(struct architectural_state * state,
 /* MOV.L Rm,@(R0,Rn) */
 void mov_l__store_indexed_register_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(r0 + op2);
+  int64_t r0, op1, op2, address;
+  r0 = sign_extend32(REG(state, 0));
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(r0 + op2);
   write_memory32(map, address, op1);
 
   state->is_delay_slot = false;
@@ -338,10 +363,11 @@ void mov_l__store_indexed_register_indirect(struct architectural_state * state,
 /* MOV.B @(R0,Rm),Rn */
 void mov_b__load_indexed_register_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(r0 + op1);
-  int64_t op2 = sign_extend8(read_memory8(map, address));
+  int64_t r0, op1, address, op2;
+  r0 = sign_extend32(REG(state, 0));
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(r0 + op1);
+  op2 = sign_extend8(read_memory8(map, address));
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -351,10 +377,11 @@ void mov_b__load_indexed_register_indirect(struct architectural_state * state, s
 /* MOV.W @(R0,Rm),Rn */
 void mov_w__load_indexed_register_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(r0 + op1);
-  int64_t op2 = sign_extend16(read_memory16(map, address));
+  int64_t r0, op1, address, op2;
+  r0 = sign_extend32(REG(state, 0));
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(r0 + op1);
+  op2 = sign_extend16(read_memory16(map, address));
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -364,10 +391,11 @@ void mov_w__load_indexed_register_indirect(struct architectural_state * state, s
 /* MOV.L @(R0,Rm),Rn */
 void mov_l__load_indexed_register_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(r0 + op1);
-  int64_t op2 = sign_extend32(read_memory32(map, address));
+  int64_t r0, op1, address, op2;
+  r0 = sign_extend32(REG(state, 0));
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(r0 + op1);
+  op2 = sign_extend32(read_memory32(map, address));
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -377,10 +405,11 @@ void mov_l__load_indexed_register_indirect(struct architectural_state * state, s
 /* MOV.B R0,@(disp,GBR) */
 void mov_b__store_gbr_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t disp = zero_extend8(d);
-  int64_t address = zero_extend32(disp + gbr);
+  int64_t gbr, r0, disp, address;
+  gbr = sign_extend32(state->gbr);
+  r0 = sign_extend32(REG(state, 0));
+  disp = zero_extend8(d);
+  address = zero_extend32(disp + gbr);
   write_memory8(map, address, r0);
 
   state->is_delay_slot = false;
@@ -390,10 +419,11 @@ void mov_b__store_gbr_indirect_with_displacement(struct architectural_state * st
 /* MOV.W R0,@(disp,GBR) */
 void mov_w__store_gbr_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t disp = zero_extend8(d) << 1;
-  int64_t address = zero_extend32(disp + gbr);
+  int64_t gbr, r0, disp, address;
+  gbr = sign_extend32(state->gbr);
+  r0 = sign_extend32(REG(state, 0));
+  disp = zero_extend8(d) << 1;
+  address = zero_extend32(disp + gbr);
   write_memory16(map, address, r0);
 
   state->is_delay_slot = false;
@@ -403,10 +433,11 @@ void mov_w__store_gbr_indirect_with_displacement(struct architectural_state * st
 /* MOV.L R0,@(disp,GBR) */
 void mov_l__store_gbr_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t disp = zero_extend8(d) << 2;
-  int64_t address = zero_extend32(disp + gbr);
+  int64_t gbr, r0, disp, address;
+  gbr = sign_extend32(state->gbr);
+  r0 = sign_extend32(REG(state, 0));
+  disp = zero_extend8(d) << 2;
+  address = zero_extend32(disp + gbr);
   write_memory32(map, address, r0);
 
   state->is_delay_slot = false;
@@ -416,10 +447,11 @@ void mov_l__store_gbr_indirect_with_displacement(struct architectural_state * st
 /* MOV.B @(disp,GBR),R0 */
 void mov_b__load_gbr_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t disp = zero_extend8(d);
-  int64_t address = zero_extend32(disp + gbr);
-  int64_t r0 = sign_extend8(read_memory8(map, address));
+  int64_t gbr, disp, address, r0;
+  gbr = sign_extend32(state->gbr);
+  disp = zero_extend8(d);
+  address = zero_extend32(disp + gbr);
+  r0 = sign_extend8(read_memory8(map, address));
   REG(state, 0) = _register(r0);
 
   state->is_delay_slot = false;
@@ -429,10 +461,11 @@ void mov_b__load_gbr_indirect_with_displacement(struct architectural_state * sta
 /* MOV.W @(disp,GBR),R0 */
 void mov_w__load_gbr_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t disp = zero_extend8(d) << 1;
-  int64_t address = zero_extend32(disp + gbr);
-  int64_t r0 = sign_extend16(read_memory16(map, address));
+  int64_t gbr, disp, address, r0;
+  gbr = sign_extend32(state->gbr);
+  disp = zero_extend8(d) << 1;
+  address = zero_extend32(disp + gbr);
+  r0 = sign_extend16(read_memory16(map, address));
   REG(state, 0) = _register(r0);
 
   state->is_delay_slot = false;
@@ -442,10 +475,11 @@ void mov_w__load_gbr_indirect_with_displacement(struct architectural_state * sta
 /* MOV.L @(disp,GBR),R0 */
 void mov_l__load_gbr_indirect_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t disp = zero_extend8(d) << 2;
-  int64_t address = zero_extend32(disp + gbr);
-  int64_t r0 = sign_extend32(read_memory32(map, address));
+  int64_t gbr, disp, address, r0;
+  gbr = sign_extend32(state->gbr);
+  disp = zero_extend8(d) << 2;
+  address = zero_extend32(disp + gbr);
+  r0 = sign_extend32(read_memory32(map, address));
   REG(state, 0) = _register(r0);
 
   state->is_delay_slot = false;
@@ -455,10 +489,11 @@ void mov_l__load_gbr_indirect_with_displacement(struct architectural_state * sta
 /* MOVA @(disp,PC),R0 */
 void mova__pc_relative_with_displacement(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t disp = zero_extend8(d) << 2;
+  int64_t pc, disp, r0;
+  pc = sign_extend32(state->pc[0]);
+  disp = zero_extend8(d) << 2;
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t r0 = disp + ((pc + 4) & (~0x3));
+  r0 = disp + ((pc + 4) & (~0x3));
   REG(state, 0) = _register(r0);
 
   state->is_delay_slot = false;
@@ -468,8 +503,9 @@ void mova__pc_relative_with_displacement(struct architectural_state * state, str
 /* MOVT Rn */
 void movt__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t op1 = t;
+  int64_t t, op1;
+  t = zero_extend1(state->sr.bits.t);
+  op1 = t;
   REG(state, n) = _register(op1);
 
   state->is_delay_slot = false;
@@ -479,8 +515,9 @@ void movt__destination_operand_only(struct architectural_state * state, struct m
 /* SWAP.B Rm,Rn */
 void swap_b__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = ((bit_extract(op1, 16, 16) << 16) | (bit_extract(op1, 0, 8) << 8)) | bit_extract(op1, 8, 8);
+  int64_t op1, op2;
+  op1 = zero_extend32(REG(state, m));
+  op2 = ((bit_extract(op1, 16, 16) << 16) | (bit_extract(op1, 0, 8) << 8)) | bit_extract(op1, 8, 8);
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -490,8 +527,9 @@ void swap_b__source_and_destination_operands(struct architectural_state * state,
 /* SWAP.W Rm,Rn */
 void swap_w__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = (bit_extract(op1, 0, 16) << 16) | bit_extract(op1, 16, 16);
+  int64_t op1, op2;
+  op1 = zero_extend32(REG(state, m));
+  op2 = (bit_extract(op1, 0, 16) << 16) | bit_extract(op1, 16, 16);
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -501,8 +539,9 @@ void swap_w__source_and_destination_operands(struct architectural_state * state,
 /* XTRCT Rm,Rn */
 void xtrct__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = zero_extend32(REG(state, n));
+  int64_t op1, op2;
+  op1 = zero_extend32(REG(state, m));
+  op2 = zero_extend32(REG(state, n));
   op2 = bit_extract(op2, 16, 16) | (bit_extract(op1, 0, 16) << 16);
   REG(state, n) = _register(op2);
 
@@ -513,8 +552,9 @@ void xtrct__source_and_destination_operands(struct architectural_state * state,
 /* ADD Rm,Rn */
 void add__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
+  int64_t op1, op2;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
   op2 = op2 + op1;
   REG(state, n) = _register(op2);
 
@@ -525,8 +565,9 @@ void add__source_and_destination_operands(struct architectural_state * state, st
 /* ADD #imm,Rn */
 void add__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i, const uint32_t n)
 {
-  int64_t imm = sign_extend8(i);
-  int64_t op2 = sign_extend32(REG(state, n));
+  int64_t imm, op2;
+  imm = sign_extend8(i);
+  op2 = sign_extend32(REG(state, n));
   op2 = op2 + imm;
   REG(state, n) = _register(op2);
 
@@ -537,9 +578,10 @@ void add__immediate(struct architectural_state * state, struct memory_map * map,
 /* ADDC Rm,Rn */
 void addc__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t op1 = zero_extend32(sign_extend32(REG(state, m)));
-  int64_t op2 = zero_extend32(sign_extend32(REG(state, n)));
+  int64_t t, op1, op2;
+  t = zero_extend1(state->sr.bits.t);
+  op1 = zero_extend32(sign_extend32(REG(state, m)));
+  op2 = zero_extend32(sign_extend32(REG(state, n)));
   op2 = (op2 + op1) + t;
   t = bit_extract(op2, 32, 1);
   REG(state, n) = _register(op2);
@@ -552,10 +594,11 @@ void addc__source_and_destination_operands(struct architectural_state * state, s
 /* ADDV Rm,Rn */
 void addv__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
+  int64_t op1, op2, t;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
   op2 = op2 + op1;
-  int64_t t = unary_int(((op2 < (-(1LL << 31))) || (op2 >= (1LL << 31))));
+  t = unary_int(((op2 < (-(1LL << 31))) || (op2 >= (1LL << 31))));
   REG(state, n) = _register(op2);
   state->sr.bits.t = bit(t);
 
@@ -566,9 +609,10 @@ void addv__source_and_destination_operands(struct architectural_state * state, s
 /* CMP/EQ #imm,R0 */
 void cmp_eq__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t imm = sign_extend8(i);
-  int64_t t = unary_int((r0 == imm));
+  int64_t r0, imm, t;
+  r0 = sign_extend32(REG(state, 0));
+  imm = sign_extend8(i);
+  t = unary_int((r0 == imm));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -578,9 +622,10 @@ void cmp_eq__immediate(struct architectural_state * state, struct memory_map * m
 /* CMP/EQ Rm,Rn */
 void cmp_eq__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t t = unary_int((op2 == op1));
+  int64_t op1, op2, t;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  t = unary_int((op2 == op1));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -590,9 +635,10 @@ void cmp_eq__source_and_destination_operands(struct architectural_state * state,
 /* CMP/HS Rm,Rn */
 void cmp_hs__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(sign_extend32(REG(state, m)));
-  int64_t op2 = zero_extend32(sign_extend32(REG(state, n)));
-  int64_t t = unary_int((op2 >= op1));
+  int64_t op1, op2, t;
+  op1 = zero_extend32(sign_extend32(REG(state, m)));
+  op2 = zero_extend32(sign_extend32(REG(state, n)));
+  t = unary_int((op2 >= op1));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -602,9 +648,10 @@ void cmp_hs__source_and_destination_operands(struct architectural_state * state,
 /* CMP/GE Rm,Rn */
 void cmp_ge__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t t = unary_int((op2 >= op1));
+  int64_t op1, op2, t;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  t = unary_int((op2 >= op1));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -614,9 +661,10 @@ void cmp_ge__source_and_destination_operands(struct architectural_state * state,
 /* CMP/HI Rm,Rn */
 void cmp_hi__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(sign_extend32(REG(state, m)));
-  int64_t op2 = zero_extend32(sign_extend32(REG(state, n)));
-  int64_t t = unary_int((op2 > op1));
+  int64_t op1, op2, t;
+  op1 = zero_extend32(sign_extend32(REG(state, m)));
+  op2 = zero_extend32(sign_extend32(REG(state, n)));
+  t = unary_int((op2 > op1));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -626,9 +674,10 @@ void cmp_hi__source_and_destination_operands(struct architectural_state * state,
 /* CMP/GT Rm,Rn */
 void cmp_gt__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t t = unary_int((op2 > op1));
+  int64_t op1, op2, t;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  t = unary_int((op2 > op1));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -638,8 +687,9 @@ void cmp_gt__source_and_destination_operands(struct architectural_state * state,
 /* CMP/PZ Rn */
 void cmp_pz__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t t = unary_int((op1 >= 0));
+  int64_t op1, t;
+  op1 = sign_extend32(REG(state, n));
+  t = unary_int((op1 >= 0));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -649,8 +699,9 @@ void cmp_pz__destination_operand_only(struct architectural_state * state, struct
 /* CMP/PL Rn */
 void cmp_pl__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t t = unary_int((op1 > 0));
+  int64_t op1, t;
+  op1 = sign_extend32(REG(state, n));
+  t = unary_int((op1 > 0));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -660,10 +711,11 @@ void cmp_pl__destination_operand_only(struct architectural_state * state, struct
 /* CMP/STR Rm,Rn */
 void cmp_str__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t temp = op1 ^ op2;
-  int64_t t = unary_int((bit_extract(temp, 0, 8) == 0));
+  int64_t op1, op2, temp, t;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  temp = op1 ^ op2;
+  t = unary_int((bit_extract(temp, 0, 8) == 0));
   t = (unary_int((bit_extract(temp, 8, 8) == 0))) | t;
   t = (unary_int((bit_extract(temp, 16, 8) == 0))) | t;
   t = (unary_int((bit_extract(temp, 24, 8) == 0))) | t;
@@ -676,12 +728,13 @@ void cmp_str__source_and_destination_operands(struct architectural_state * state
 /* DIV1 Rm,Rn */
 void div1__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t q = zero_extend1(state->sr.bits.q);
-  int64_t _m = zero_extend1(state->sr.bits.m);
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t op1 = zero_extend32(sign_extend32(REG(state, m)));
-  int64_t op2 = zero_extend32(sign_extend32(REG(state, n)));
-  int64_t oldq = q;
+  int64_t q, _m, t, op1, op2, oldq;
+  q = zero_extend1(state->sr.bits.q);
+  _m = zero_extend1(state->sr.bits.m);
+  t = zero_extend1(state->sr.bits.t);
+  op1 = zero_extend32(sign_extend32(REG(state, m)));
+  op2 = zero_extend32(sign_extend32(REG(state, n)));
+  oldq = q;
   q = bit_extract(op2, 31, 1);
   op2 = zero_extend32(op2 << 1) | t;
   if (oldq == _m) op2 = op2 - op1;
@@ -699,11 +752,12 @@ void div1__source_and_destination_operands(struct architectural_state * state, s
 /* DIV0S Rm,Rn */
 void div0s__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t q = bit_extract(op2, 31, 1);
-  int64_t _m = bit_extract(op1, 31, 1);
-  int64_t t = _m ^ q;
+  int64_t op1, op2, q, _m, t;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  q = bit_extract(op2, 31, 1);
+  _m = bit_extract(op1, 31, 1);
+  t = _m ^ q;
   state->sr.bits.q = bit(q);
   state->sr.bits.m = bit(_m);
   state->sr.bits.t = bit(t);
@@ -715,9 +769,10 @@ void div0s__source_and_destination_operands(struct architectural_state * state,
 /* DIV0U */
 void div0u__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t q = 0;
-  int64_t _m = 0;
-  int64_t t = 0;
+  int64_t q, _m, t;
+  q = 0;
+  _m = 0;
+  t = 0;
   state->sr.bits.q = bit(q);
   state->sr.bits.m = bit(_m);
   state->sr.bits.t = bit(t);
@@ -729,11 +784,12 @@ void div0u__no_operand(struct architectural_state * state, struct memory_map * m
 /* DMULS.L Rm,Rn */
 void dmuls_l__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t mac = op2 * op1;
-  int64_t macl = mac;
-  int64_t mach = mac >> 32;
+  int64_t op1, op2, mac, macl, mach;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  mac = op2 * op1;
+  macl = mac;
+  mach = mac >> 32;
   state->macl = zero_extend32(macl);
   state->mach = zero_extend32(mach);
 
@@ -744,11 +800,12 @@ void dmuls_l__source_and_destination_operands(struct architectural_state * state
 /* DMULU.L Rm,Rn */
 void dmulu_l__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(sign_extend32(REG(state, m)));
-  int64_t op2 = zero_extend32(sign_extend32(REG(state, n)));
-  int64_t mac = op2 * op1;
-  int64_t macl = mac;
-  int64_t mach = mac >> 32;
+  int64_t op1, op2, mac, macl, mach;
+  op1 = zero_extend32(sign_extend32(REG(state, m)));
+  op2 = zero_extend32(sign_extend32(REG(state, n)));
+  mac = op2 * op1;
+  macl = mac;
+  mach = mac >> 32;
   state->macl = zero_extend32(macl);
   state->mach = zero_extend32(mach);
 
@@ -759,9 +816,10 @@ void dmulu_l__source_and_destination_operands(struct architectural_state * state
 /* DT Rn */
 void dt__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, n));
+  int64_t op1, t;
+  op1 = sign_extend32(REG(state, n));
   op1 = op1 - 1;
-  int64_t t = unary_int((op1 == 0));
+  t = unary_int((op1 == 0));
   REG(state, n) = _register(op1);
   state->sr.bits.t = bit(t);
 
@@ -772,8 +830,9 @@ void dt__destination_operand_only(struct architectural_state * state, struct mem
 /* EXTS.B Rm,Rn */
 void exts_b__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend8(REG(state, m));
-  int64_t op2 = op1;
+  int64_t op1, op2;
+  op1 = sign_extend8(REG(state, m));
+  op2 = op1;
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -783,8 +842,9 @@ void exts_b__source_and_destination_operands(struct architectural_state * state,
 /* EXTS.W Rm,Rn */
 void exts_w__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend16(REG(state, m));
-  int64_t op2 = op1;
+  int64_t op1, op2;
+  op1 = sign_extend16(REG(state, m));
+  op2 = op1;
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -794,8 +854,9 @@ void exts_w__source_and_destination_operands(struct architectural_state * state,
 /* EXTU.B Rm,Rn */
 void extu_b__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend8(REG(state, m));
-  int64_t op2 = op1;
+  int64_t op1, op2;
+  op1 = zero_extend8(REG(state, m));
+  op2 = op1;
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -805,8 +866,9 @@ void extu_b__source_and_destination_operands(struct architectural_state * state,
 /* EXTU.W Rm,Rn */
 void extu_w__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend16(REG(state, m));
-  int64_t op2 = op1;
+  int64_t op1, op2;
+  op1 = zero_extend16(REG(state, m));
+  op2 = op1;
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -816,25 +878,26 @@ void extu_w__source_and_destination_operands(struct architectural_state * state,
 /* MAC.L @Rm+,@Rn+ */
 void mac_l__multiply_and_accumulate_operation(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t macl = zero_extend32(state->macl);
-  int64_t mach = zero_extend32(state->mach);
-  int64_t s = zero_extend1(state->sr.bits.s);
-  int64_t m_field = zero_extend4(m);
-  int64_t n_field = zero_extend4(n);
-  int64_t m_address = sign_extend32(REG(state, m));
-  int64_t n_address = sign_extend32(REG(state, n));
-  int64_t value2 = sign_extend32(read_memory32(map, zero_extend32(n_address)));
+  int64_t macl, mach, s, m_field, n_field, m_address, n_address, value2, value1, mul, mac, result;
+  macl = zero_extend32(state->macl);
+  mach = zero_extend32(state->mach);
+  s = zero_extend1(state->sr.bits.s);
+  m_field = zero_extend4(m);
+  n_field = zero_extend4(n);
+  m_address = sign_extend32(REG(state, m));
+  n_address = sign_extend32(REG(state, n));
+  value2 = sign_extend32(read_memory32(map, zero_extend32(n_address)));
   n_address = n_address + 4;
   if (n_field == m_field) 
   {
   m_address = m_address + 4;
   n_address = n_address + 4;
   }
-  int64_t value1 = sign_extend32(read_memory32(map, zero_extend32(m_address)));
+  value1 = sign_extend32(read_memory32(map, zero_extend32(m_address)));
   m_address = m_address + 4;
-  int64_t mul = value2 * value1;
-  int64_t mac = (mach << 32) + macl;
-  int64_t result = mac + mul;
+  mul = value2 * value1;
+  mac = (mach << 32) + macl;
+  result = mac + mul;
   if (s == 1) if (bit_extract(((result ^ mac) & (result ^ mul)), 63, 1) == 1) if (bit_extract(mac, 63, 1) == 0) result = (1LL << 47) - 1;
   else result = -(1LL << 47);
   else result = signed_saturate48(result);
@@ -852,28 +915,29 @@ void mac_l__multiply_and_accumulate_operation(struct architectural_state * state
 /* MAC.W @Rm+,@Rn+ */
 void mac_w__multiply_and_accumulate_operation(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t macl = zero_extend32(state->macl);
-  int64_t mach = zero_extend32(state->mach);
-  int64_t s = zero_extend1(state->sr.bits.s);
-  int64_t m_field = zero_extend4(m);
-  int64_t n_field = zero_extend4(n);
-  int64_t m_address = sign_extend32(REG(state, m));
-  int64_t n_address = sign_extend32(REG(state, n));
-  int64_t value2 = sign_extend16(read_memory16(map, zero_extend32(n_address)));
+  int64_t macl, mach, s, m_field, n_field, m_address, n_address, value2, value1, mul, result, temp;
+  macl = zero_extend32(state->macl);
+  mach = zero_extend32(state->mach);
+  s = zero_extend1(state->sr.bits.s);
+  m_field = zero_extend4(m);
+  n_field = zero_extend4(n);
+  m_address = sign_extend32(REG(state, m));
+  n_address = sign_extend32(REG(state, n));
+  value2 = sign_extend16(read_memory16(map, zero_extend32(n_address)));
   n_address = n_address + 2;
   if (n_field == m_field) 
   {
   m_address = m_address + 2;
   n_address = n_address + 2;
   }
-  int64_t value1 = sign_extend16(read_memory16(map, zero_extend32(m_address)));
+  value1 = sign_extend16(read_memory16(map, zero_extend32(m_address)));
   m_address = m_address + 2;
-  int64_t mul = value2 * value1;
-  int64_t result = 0;
+  mul = value2 * value1;
+  result = 0;
   if (s == 1) 
   {
   macl = sign_extend32(macl) + mul;
-  int64_t temp = signed_saturate32(macl);
+  temp = signed_saturate32(macl);
   if (macl == temp) result = (mach << 32) | zero_extend32(macl);
   else result = (1LL << 32) | zero_extend32(temp);
   }
@@ -892,9 +956,10 @@ void mac_w__multiply_and_accumulate_operation(struct architectural_state * state
 /* MUL.L Rm,Rn */
 void mul_l__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t macl = op1 * op2;
+  int64_t op1, op2, macl;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  macl = op1 * op2;
   state->macl = zero_extend32(macl);
 
   state->is_delay_slot = false;
@@ -904,9 +969,10 @@ void mul_l__source_and_destination_operands(struct architectural_state * state,
 /* MULS.W Rm,Rn */
 void muls_w__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend16(sign_extend32(REG(state, m)));
-  int64_t op2 = sign_extend16(sign_extend32(REG(state, n)));
-  int64_t macl = op1 * op2;
+  int64_t op1, op2, macl;
+  op1 = sign_extend16(sign_extend32(REG(state, m)));
+  op2 = sign_extend16(sign_extend32(REG(state, n)));
+  macl = op1 * op2;
   state->macl = zero_extend32(macl);
 
   state->is_delay_slot = false;
@@ -916,9 +982,10 @@ void muls_w__source_and_destination_operands(struct architectural_state * state,
 /* MULU.W Rm,Rn */
 void mulu_w__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend16(sign_extend32(REG(state, m)));
-  int64_t op2 = zero_extend16(sign_extend32(REG(state, n)));
-  int64_t macl = op1 * op2;
+  int64_t op1, op2, macl;
+  op1 = zero_extend16(sign_extend32(REG(state, m)));
+  op2 = zero_extend16(sign_extend32(REG(state, n)));
+  macl = op1 * op2;
   state->macl = zero_extend32(macl);
 
   state->is_delay_slot = false;
@@ -928,8 +995,9 @@ void mulu_w__source_and_destination_operands(struct architectural_state * state,
 /* NEG Rm,Rn */
 void neg__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = -op1;
+  int64_t op1, op2;
+  op1 = sign_extend32(REG(state, m));
+  op2 = -op1;
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -939,9 +1007,10 @@ void neg__source_and_destination_operands(struct architectural_state * state, st
 /* NEGC Rm,Rn */
 void negc__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = (-op1) - t;
+  int64_t t, op1, op2;
+  t = zero_extend1(state->sr.bits.t);
+  op1 = zero_extend32(REG(state, m));
+  op2 = (-op1) - t;
   t = bit_extract(op2, 32, 1);
   REG(state, n) = _register(op2);
   state->sr.bits.t = bit(t);
@@ -953,8 +1022,9 @@ void negc__source_and_destination_operands(struct architectural_state * state, s
 /* SUB Rm,Rn */
 void sub__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
+  int64_t op1, op2;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
   op2 = op2 - op1;
   REG(state, n) = _register(op2);
 
@@ -965,9 +1035,10 @@ void sub__source_and_destination_operands(struct architectural_state * state, st
 /* SUBC Rm,Rn */
 void subc__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t op1 = zero_extend32(sign_extend32(REG(state, m)));
-  int64_t op2 = zero_extend32(sign_extend32(REG(state, n)));
+  int64_t t, op1, op2;
+  t = zero_extend1(state->sr.bits.t);
+  op1 = zero_extend32(sign_extend32(REG(state, m)));
+  op2 = zero_extend32(sign_extend32(REG(state, n)));
   op2 = (op2 - op1) - t;
   t = bit_extract(op2, 32, 1);
   REG(state, n) = _register(op2);
@@ -980,10 +1051,11 @@ void subc__source_and_destination_operands(struct architectural_state * state, s
 /* SUBV Rm,Rn */
 void subv__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
+  int64_t op1, op2, t;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
   op2 = op2 - op1;
-  int64_t t = unary_int(((op2 < (-(1LL << 31))) || (op2 >= (1LL << 31))));
+  t = unary_int(((op2 < (-(1LL << 31))) || (op2 >= (1LL << 31))));
   REG(state, n) = _register(op2);
   state->sr.bits.t = bit(t);
 
@@ -994,8 +1066,9 @@ void subv__source_and_destination_operands(struct architectural_state * state, s
 /* AND Rm,Rn */
 void and__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = zero_extend32(REG(state, n));
+  int64_t op1, op2;
+  op1 = zero_extend32(REG(state, m));
+  op2 = zero_extend32(REG(state, n));
   op2 = op2 & op1;
   REG(state, n) = _register(op2);
 
@@ -1006,8 +1079,9 @@ void and__source_and_destination_operands(struct architectural_state * state, st
 /* AND #imm,R0 */
 void and__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = zero_extend32(REG(state, 0));
-  int64_t imm = zero_extend8(i);
+  int64_t r0, imm;
+  r0 = zero_extend32(REG(state, 0));
+  imm = zero_extend8(i);
   r0 = r0 & imm;
   REG(state, 0) = _register(r0);
 
@@ -1018,11 +1092,12 @@ void and__immediate(struct architectural_state * state, struct memory_map * map,
 /* AND.B #imm,@(R0,GBR) */
 void and_b__store_indexed_gbr_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t imm = zero_extend8(i);
-  int64_t address = zero_extend32(r0 + gbr);
-  int64_t value = zero_extend8(read_memory8(map, address));
+  int64_t r0, gbr, imm, address, value;
+  r0 = sign_extend32(REG(state, 0));
+  gbr = sign_extend32(state->gbr);
+  imm = zero_extend8(i);
+  address = zero_extend32(r0 + gbr);
+  value = zero_extend8(read_memory8(map, address));
   value = value & imm;
   write_memory8(map, address, value);
 
@@ -1033,8 +1108,9 @@ void and_b__store_indexed_gbr_indirect(struct architectural_state * state, struc
 /* NOT Rm,Rn */
 void not__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = ~op1;
+  int64_t op1, op2;
+  op1 = zero_extend32(REG(state, m));
+  op2 = ~op1;
   REG(state, n) = _register(op2);
 
   state->is_delay_slot = false;
@@ -1044,8 +1120,9 @@ void not__source_and_destination_operands(struct architectural_state * state, st
 /* OR Rm,Rn */
 void or__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = zero_extend32(REG(state, n));
+  int64_t op1, op2;
+  op1 = zero_extend32(REG(state, m));
+  op2 = zero_extend32(REG(state, n));
   op2 = op2 | op1;
   REG(state, n) = _register(op2);
 
@@ -1056,8 +1133,9 @@ void or__source_and_destination_operands(struct architectural_state * state, str
 /* OR #imm,R0 */
 void or__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = zero_extend32(REG(state, 0));
-  int64_t imm = zero_extend8(i);
+  int64_t r0, imm;
+  r0 = zero_extend32(REG(state, 0));
+  imm = zero_extend8(i);
   r0 = r0 | imm;
   REG(state, 0) = _register(r0);
 
@@ -1068,11 +1146,12 @@ void or__immediate(struct architectural_state * state, struct memory_map * map,
 /* OR.B #imm,@(R0,GBR) */
 void or_b__store_indexed_gbr_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t imm = zero_extend8(i);
-  int64_t address = zero_extend32(r0 + gbr);
-  int64_t value = zero_extend8(read_memory8(map, address));
+  int64_t r0, gbr, imm, address, value;
+  r0 = sign_extend32(REG(state, 0));
+  gbr = sign_extend32(state->gbr);
+  imm = zero_extend8(i);
+  address = zero_extend32(r0 + gbr);
+  value = zero_extend8(read_memory8(map, address));
   value = value | imm;
   write_memory8(map, address, value);
 
@@ -1083,11 +1162,12 @@ void or_b__store_indexed_gbr_indirect(struct architectural_state * state, struct
 /* TAS.B @Rn */
 void tas_b__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op1);
+  int64_t op1, address, value, t;
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1);
   ocbp(state, address);
-  int64_t value = zero_extend8(read_memory8(map, address));
-  int64_t t = unary_int((value == 0));
+  value = zero_extend8(read_memory8(map, address));
+  t = unary_int((value == 0));
   value = value | (1LL << 7);
   write_memory8(map, address, value);
   state->sr.bits.t = bit(t);
@@ -1099,9 +1179,10 @@ void tas_b__destination_operand_only(struct architectural_state * state, struct
 /* TST Rm,Rn */
 void tst__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t op2 = sign_extend32(REG(state, n));
-  int64_t t = unary_int(((op1 & op2) == 0));
+  int64_t op1, op2, t;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  t = unary_int(((op1 & op2) == 0));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -1111,9 +1192,10 @@ void tst__source_and_destination_operands(struct architectural_state * state, st
 /* TST #imm,R0 */
 void tst__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t imm = zero_extend8(i);
-  int64_t t = unary_int(((r0 & imm) == 0));
+  int64_t r0, imm, t;
+  r0 = sign_extend32(REG(state, 0));
+  imm = zero_extend8(i);
+  t = unary_int(((r0 & imm) == 0));
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -1123,12 +1205,13 @@ void tst__immediate(struct architectural_state * state, struct memory_map * map,
 /* TST.B #imm,@(R0,GBR) */
 void tst_b__store_indexed_gbr_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t imm = zero_extend8(i);
-  int64_t address = zero_extend32(r0 + gbr);
-  int64_t value = zero_extend8(read_memory8(map, address));
-  int64_t t = ((value & imm) == 0);
+  int64_t r0, gbr, imm, address, value, t;
+  r0 = sign_extend32(REG(state, 0));
+  gbr = sign_extend32(state->gbr);
+  imm = zero_extend8(i);
+  address = zero_extend32(r0 + gbr);
+  value = zero_extend8(read_memory8(map, address));
+  t = ((value & imm) == 0);
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -1138,8 +1221,9 @@ void tst_b__store_indexed_gbr_indirect(struct architectural_state * state, struc
 /* XOR Rm,Rn */
 void xor__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, m));
-  int64_t op2 = zero_extend32(REG(state, n));
+  int64_t op1, op2;
+  op1 = zero_extend32(REG(state, m));
+  op2 = zero_extend32(REG(state, n));
   op2 = op2 ^ op1;
   REG(state, n) = _register(op2);
 
@@ -1150,8 +1234,9 @@ void xor__source_and_destination_operands(struct architectural_state * state, st
 /* XOR #imm,R0 */
 void xor__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = zero_extend32(REG(state, 0));
-  int64_t imm = zero_extend8(i);
+  int64_t r0, imm;
+  r0 = zero_extend32(REG(state, 0));
+  imm = zero_extend8(i);
   r0 = r0 ^ imm;
   REG(state, 0) = _register(r0);
 
@@ -1162,11 +1247,12 @@ void xor__immediate(struct architectural_state * state, struct memory_map * map,
 /* XOR.B #imm,@(R0,GBR) */
 void xor_b__store_indexed_gbr_indirect(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t r0 = sign_extend32(REG(state, 0));
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t imm = zero_extend8(i);
-  int64_t address = zero_extend32(r0 + gbr);
-  int64_t value = zero_extend8(read_memory8(map, address));
+  int64_t r0, gbr, imm, address, value;
+  r0 = sign_extend32(REG(state, 0));
+  gbr = sign_extend32(state->gbr);
+  imm = zero_extend8(i);
+  address = zero_extend32(r0 + gbr);
+  value = zero_extend8(read_memory8(map, address));
   value = value ^ imm;
   write_memory8(map, address, value);
 
@@ -1177,8 +1263,9 @@ void xor_b__store_indexed_gbr_indirect(struct architectural_state * state, struc
 /* ROTL Rn */
 void rotl__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
-  int64_t t = bit_extract(op1, 31, 1);
+  int64_t op1, t;
+  op1 = zero_extend32(REG(state, n));
+  t = bit_extract(op1, 31, 1);
   op1 = (op1 << 1) | t;
   REG(state, n) = _register(op1);
   state->sr.bits.t = bit(t);
@@ -1190,8 +1277,9 @@ void rotl__destination_operand_only(struct architectural_state * state, struct m
 /* ROTR Rn */
 void rotr__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
-  int64_t t = bit_extract(op1, 0, 1);
+  int64_t op1, t;
+  op1 = zero_extend32(REG(state, n));
+  t = bit_extract(op1, 0, 1);
   op1 = (op1 >> 1) | (t << 31);
   REG(state, n) = _register(op1);
   state->sr.bits.t = bit(t);
@@ -1203,8 +1291,9 @@ void rotr__destination_operand_only(struct architectural_state * state, struct m
 /* ROTCL Rn */
 void rotcl__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t op1 = zero_extend32(REG(state, n));
+  int64_t t, op1;
+  t = zero_extend1(state->sr.bits.t);
+  op1 = zero_extend32(REG(state, n));
   op1 = (op1 << 1) | t;
   t = bit_extract(op1, 32, 1);
   REG(state, n) = _register(op1);
@@ -1217,9 +1306,10 @@ void rotcl__destination_operand_only(struct architectural_state * state, struct
 /* ROTCR Rn */
 void rotcr__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t op1 = zero_extend32(REG(state, n));
-  int64_t oldt = t;
+  int64_t t, op1, oldt;
+  t = zero_extend1(state->sr.bits.t);
+  op1 = zero_extend32(REG(state, n));
+  oldt = t;
   t = bit_extract(op1, 0, 1);
   op1 = (op1 >> 1) | (oldt << 31);
   REG(state, n) = _register(op1);
@@ -1229,11 +1319,29 @@ void rotcr__destination_operand_only(struct architectural_state * state, struct
 }
 
 
+/* SHAD Rm,Rn */
+void shad__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
+{
+  int64_t op1, op2, shift_amount;
+  op1 = sign_extend32(REG(state, m));
+  op2 = sign_extend32(REG(state, n));
+  shift_amount = zero_extend5(op1);
+  if (op1 >= 0) op2 = op2 << shift_amount;
+  else if (shift_amount != 0) op2 = op2 >> (32 - shift_amount);
+  else if (op2 < 0) op2 = -1;
+  else op2 = 0;
+  REG(state, n) = _register(op2);
+
+  state->is_delay_slot = false;
+}
+
+
 /* SHAL Rn */
 void shal__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t t = bit_extract(op1, 31, 1);
+  int64_t op1, t;
+  op1 = sign_extend32(REG(state, n));
+  t = bit_extract(op1, 31, 1);
   op1 = op1 << 1;
   REG(state, n) = _register(op1);
   state->sr.bits.t = bit(t);
@@ -1245,8 +1353,9 @@ void shal__destination_operand_only(struct architectural_state * state, struct m
 /* SHAR Rn */
 void shar__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t t = bit_extract(op1, 0, 1);
+  int64_t op1, t;
+  op1 = sign_extend32(REG(state, n));
+  t = bit_extract(op1, 0, 1);
   op1 = op1 >> 1;
   REG(state, n) = _register(op1);
   state->sr.bits.t = bit(t);
@@ -1255,11 +1364,28 @@ void shar__destination_operand_only(struct architectural_state * state, struct m
 }
 
 
+/* SHLD Rm,Rn */
+void shld__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
+{
+  int64_t op1, op2, shift_amount;
+  op1 = sign_extend32(REG(state, m));
+  op2 = zero_extend32(REG(state, n));
+  shift_amount = zero_extend5(op1);
+  if (op1 >= 0) op2 = op2 << shift_amount;
+  else if (shift_amount != 0) op2 = op2 >> (32 - shift_amount);
+  else op2 = 0;
+  REG(state, n) = _register(op2);
+
+  state->is_delay_slot = false;
+}
+
+
 /* SHLL Rn */
 void shll__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
-  int64_t t = bit_extract(op1, 31, 1);
+  int64_t op1, t;
+  op1 = zero_extend32(REG(state, n));
+  t = bit_extract(op1, 31, 1);
   op1 = op1 << 1;
   REG(state, n) = _register(op1);
   state->sr.bits.t = bit(t);
@@ -1271,8 +1397,9 @@ void shll__destination_operand_only(struct architectural_state * state, struct m
 /* SHLR Rn */
 void shlr__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
-  int64_t t = bit_extract(op1, 0, 1);
+  int64_t op1, t;
+  op1 = zero_extend32(REG(state, n));
+  t = bit_extract(op1, 0, 1);
   op1 = op1 >> 1;
   REG(state, n) = _register(op1);
   state->sr.bits.t = bit(t);
@@ -1284,7 +1411,8 @@ void shlr__destination_operand_only(struct architectural_state * state, struct m
 /* SHLL2 Rn */
 void shll2__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
+  int64_t op1;
+  op1 = zero_extend32(REG(state, n));
   op1 = op1 << 2;
   REG(state, n) = _register(op1);
 
@@ -1295,7 +1423,8 @@ void shll2__destination_operand_only(struct architectural_state * state, struct
 /* SHLR2 Rn */
 void shlr2__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
+  int64_t op1;
+  op1 = zero_extend32(REG(state, n));
   op1 = op1 >> 2;
   REG(state, n) = _register(op1);
 
@@ -1306,7 +1435,8 @@ void shlr2__destination_operand_only(struct architectural_state * state, struct
 /* SHLL8 Rn */
 void shll8__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
+  int64_t op1;
+  op1 = zero_extend32(REG(state, n));
   op1 = op1 << 8;
   REG(state, n) = _register(op1);
 
@@ -1317,7 +1447,8 @@ void shll8__destination_operand_only(struct architectural_state * state, struct
 /* SHLR8 Rn */
 void shlr8__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
+  int64_t op1;
+  op1 = zero_extend32(REG(state, n));
   op1 = op1 >> 8;
   REG(state, n) = _register(op1);
 
@@ -1328,7 +1459,8 @@ void shlr8__destination_operand_only(struct architectural_state * state, struct
 /* SHLL16 Rn */
 void shll16__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
+  int64_t op1;
+  op1 = zero_extend32(REG(state, n));
   op1 = op1 << 16;
   REG(state, n) = _register(op1);
 
@@ -1339,7 +1471,8 @@ void shll16__destination_operand_only(struct architectural_state * state, struct
 /* SHLR16 Rn */
 void shlr16__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = zero_extend32(REG(state, n));
+  int64_t op1;
+  op1 = zero_extend32(REG(state, n));
   op1 = op1 >> 16;
   REG(state, n) = _register(op1);
 
@@ -1350,15 +1483,16 @@ void shlr16__destination_operand_only(struct architectural_state * state, struct
 /* BF label */
 void bf__pc_relative(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t newpc = sign_extend32(state->pc[1]);
-  int64_t delayedpc = sign_extend32(state->pc[2]);
-  int64_t label = sign_extend8(d) << 1;
+  int64_t t, pc, newpc, delayedpc, label, temp;
+  t = zero_extend1(state->sr.bits.t);
+  pc = sign_extend32(state->pc[0]);
+  newpc = sign_extend32(state->pc[1]);
+  delayedpc = sign_extend32(state->pc[2]);
+  label = sign_extend8(d) << 1;
   if (is_delay_slot(state)) return ILLSLOT(state);
   if (t == 0) 
   {
-  int64_t temp = zero_extend32(pc + 4 + label);
+  temp = zero_extend32(pc + 4 + label);
   newpc = temp;
   delayedpc = temp + 2;
   }
@@ -1372,14 +1506,15 @@ void bf__pc_relative(struct architectural_state * state, struct memory_map * map
 /* BF/S label */
 void bf_s__pc_relative(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t delayedpc = sign_extend32(state->pc[2]);
-  int64_t label = sign_extend8(d) << 1;
+  int64_t t, pc, delayedpc, label, temp;
+  t = zero_extend1(state->sr.bits.t);
+  pc = sign_extend32(state->pc[0]);
+  delayedpc = sign_extend32(state->pc[2]);
+  label = sign_extend8(d) << 1;
   if (is_delay_slot(state)) return ILLSLOT(state);
   if (t == 0) 
   {
-  int64_t temp = zero_extend32(pc + 4 + label);
+  temp = zero_extend32(pc + 4 + label);
   delayedpc = temp;
   }
   state->pc[2] = _register(delayedpc);
@@ -1391,15 +1526,16 @@ void bf_s__pc_relative(struct architectural_state * state, struct memory_map * m
 /* BT label */
 void bt__pc_relative(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t newpc = sign_extend32(state->pc[1]);
-  int64_t delayedpc = sign_extend32(state->pc[2]);
-  int64_t label = sign_extend8(d) << 1;
+  int64_t t, pc, newpc, delayedpc, label, temp;
+  t = zero_extend1(state->sr.bits.t);
+  pc = sign_extend32(state->pc[0]);
+  newpc = sign_extend32(state->pc[1]);
+  delayedpc = sign_extend32(state->pc[2]);
+  label = sign_extend8(d) << 1;
   if (is_delay_slot(state)) return ILLSLOT(state);
   if (t == 1) 
   {
-  int64_t temp = zero_extend32(pc + 4 + label);
+  temp = zero_extend32(pc + 4 + label);
   newpc = temp;
   delayedpc = temp + 2;
   }
@@ -1413,14 +1549,15 @@ void bt__pc_relative(struct architectural_state * state, struct memory_map * map
 /* BT/S label */
 void bt_s__pc_relative(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t t = zero_extend1(state->sr.bits.t);
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t delayedpc = sign_extend32(state->pc[2]);
-  int64_t label = sign_extend8(d) << 1;
+  int64_t t, pc, delayedpc, label, temp;
+  t = zero_extend1(state->sr.bits.t);
+  pc = sign_extend32(state->pc[0]);
+  delayedpc = sign_extend32(state->pc[2]);
+  label = sign_extend8(d) << 1;
   if (is_delay_slot(state)) return ILLSLOT(state);
   if (t == 1) 
   {
-  int64_t temp = zero_extend32(pc + 4 + label);
+  temp = zero_extend32(pc + 4 + label);
   delayedpc = temp;
   }
   state->pc[2] = _register(delayedpc);
@@ -1432,11 +1569,12 @@ void bt_s__pc_relative(struct architectural_state * state, struct memory_map * m
 /* BRA label */
 void bra__pc_relative(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t label = sign_extend12(d) << 1;
+  int64_t pc, label, temp, delayedpc;
+  pc = sign_extend32(state->pc[0]);
+  label = sign_extend12(d) << 1;
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t temp = zero_extend32(pc + 4 + label);
-  int64_t delayedpc = temp;
+  temp = zero_extend32(pc + 4 + label);
+  delayedpc = temp;
   state->pc[2] = _register(delayedpc);
 
   state->is_delay_slot = true;
@@ -1446,11 +1584,12 @@ void bra__pc_relative(struct architectural_state * state, struct memory_map * ma
 /* BRAF Rn */
 void braf__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t op1 = sign_extend32(REG(state, n));
+  int64_t pc, op1, target, delayedpc;
+  pc = sign_extend32(state->pc[0]);
+  op1 = sign_extend32(REG(state, n));
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t target = zero_extend32(pc + 4 + op1);
-  int64_t delayedpc = target & (~0x1);
+  target = zero_extend32(pc + 4 + op1);
+  delayedpc = target & (~0x1);
   state->pc[2] = _register(delayedpc);
 
   state->is_delay_slot = true;
@@ -1460,12 +1599,13 @@ void braf__destination_operand_only(struct architectural_state * state, struct m
 /* BSR label */
 void bsr__pc_relative(struct architectural_state * state, struct memory_map * map, const uint32_t d)
 {
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t label = sign_extend12(d) << 1;
+  int64_t pc, label, delayedpr, temp, delayedpc;
+  pc = sign_extend32(state->pc[0]);
+  label = sign_extend12(d) << 1;
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t delayedpr = pc + 4;
-  int64_t temp = zero_extend32(pc + 4 + label);
-  int64_t delayedpc = temp;
+  delayedpr = pc + 4;
+  temp = zero_extend32(pc + 4 + label);
+  delayedpc = temp;
   state->pr[2] = _register(delayedpr);
   state->pc[2] = _register(delayedpc);
 
@@ -1476,12 +1616,13 @@ void bsr__pc_relative(struct architectural_state * state, struct memory_map * ma
 /* BSRF Rn */
 void bsrf__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t op1 = sign_extend32(REG(state, n));
+  int64_t pc, op1, delayedpr, target, delayedpc;
+  pc = sign_extend32(state->pc[0]);
+  op1 = sign_extend32(REG(state, n));
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t delayedpr = pc + 4;
-  int64_t target = zero_extend32(pc + 4 + op1);
-  int64_t delayedpc = target & (~0x1);
+  delayedpr = pc + 4;
+  target = zero_extend32(pc + 4 + op1);
+  delayedpc = target & (~0x1);
   state->pr[2] = _register(delayedpr);
   state->pc[2] = _register(delayedpc);
 
@@ -1492,10 +1633,11 @@ void bsrf__destination_operand_only(struct architectural_state * state, struct m
 /* JMP @Rn */
 void jmp__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t op1 = sign_extend32(REG(state, n));
+  int64_t op1, target, delayedpc;
+  op1 = sign_extend32(REG(state, n));
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t target = op1;
-  int64_t delayedpc = target & (~0x1);
+  target = op1;
+  delayedpc = target & (~0x1);
   state->pc[2] = _register(delayedpc);
 
   state->is_delay_slot = true;
@@ -1505,12 +1647,13 @@ void jmp__destination_operand_only(struct architectural_state * state, struct me
 /* JSR @Rn */
 void jsr__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t pc = sign_extend32(state->pc[0]);
-  int64_t op1 = sign_extend32(REG(state, n));
+  int64_t pc, op1, delayedpr, target, delayedpc;
+  pc = sign_extend32(state->pc[0]);
+  op1 = sign_extend32(REG(state, n));
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t delayedpr = pc + 4;
-  int64_t target = op1;
-  int64_t delayedpc = target & (~0x1);
+  delayedpr = pc + 4;
+  target = op1;
+  delayedpc = target & (~0x1);
   state->pr[2] = _register(delayedpr);
   state->pc[2] = _register(delayedpc);
 
@@ -1521,10 +1664,11 @@ void jsr__destination_operand_only(struct architectural_state * state, struct me
 /* RTS */
 void rts__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t pr = sign_extend32(state->pr[0]);
+  int64_t pr, target, delayedpc;
+  pr = sign_extend32(state->pr[0]);
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t target = pr;
-  int64_t delayedpc = target & (~0x1);
+  target = pr;
+  delayedpc = target & (~0x1);
   state->pc[2] = _register(delayedpc);
 
   state->is_delay_slot = true;
@@ -1534,8 +1678,9 @@ void rts__no_operand(struct architectural_state * state, struct memory_map * map
 /* CLRMAC */
 void clrmac__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t macl = 0;
-  int64_t mach = 0;
+  int64_t macl, mach;
+  macl = 0;
+  mach = 0;
   state->macl = zero_extend32(macl);
   state->mach = zero_extend32(mach);
 
@@ -1546,7 +1691,8 @@ void clrmac__no_operand(struct architectural_state * state, struct memory_map *
 /* CLRS */
 void clrs__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t s = 0;
+  int64_t s;
+  s = 0;
   state->sr.bits.s = bit(s);
 
   state->is_delay_slot = false;
@@ -1556,7 +1702,8 @@ void clrs__no_operand(struct architectural_state * state, struct memory_map * ma
 /* CLRT */
 void clrt__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t t = 0;
+  int64_t t;
+  t = 0;
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -1566,10 +1713,11 @@ void clrt__no_operand(struct architectural_state * state, struct memory_map * ma
 /* LDC Rm,SR */
 void ldc__transfer_to_sr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, op1, sr;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t sr = op1;
+  op1 = sign_extend32(REG(state, m));
+  sr = op1;
   state->sr.value = _register(sr);
 
   state->is_delay_slot = false;
@@ -1579,8 +1727,9 @@ void ldc__transfer_to_sr(struct architectural_state * state, struct memory_map *
 /* LDC Rm,GBR */
 void ldc__transfer_to_gbr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t gbr = op1;
+  int64_t op1, gbr;
+  op1 = sign_extend32(REG(state, m));
+  gbr = op1;
   state->gbr = _register(gbr);
 
   state->is_delay_slot = false;
@@ -1590,24 +1739,82 @@ void ldc__transfer_to_gbr(struct architectural_state * state, struct memory_map
 /* LDC Rm,VBR */
 void ldc__transfer_to_vbr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, op1, vbr;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t vbr = op1;
+  op1 = sign_extend32(REG(state, m));
+  vbr = op1;
   state->vbr = _register(vbr);
 
   state->is_delay_slot = false;
 }
 
 
+/* LDC Rm,SSR */
+void ldc__transfer_to_ssr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t md, op1, ssr;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG(state, m));
+  ssr = op1;
+  state->ssr = _register(ssr);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDC Rm,SPC */
+void ldc__transfer_to_spc(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t md, op1, spc;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG(state, m));
+  spc = op1;
+  state->spc = _register(spc);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDC Rm,DBR */
+void ldc__transfer_to_dbr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t md, op1, dbr;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG(state, m));
+  dbr = op1;
+  state->dbr = _register(dbr);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDC Rm,Rn_BANK */
+void ldc__transfer_to_rn_bank(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
+{
+  int64_t md, op1, rn_bank;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG(state, m));
+  rn_bank = op1;
+  REG_BANK(state, n) = _register(rn_bank);
+
+  state->is_delay_slot = false;
+}
+
+
 /* LDC.L @Rm+,SR */
 void ldc_l__load_to_sr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, op1, address, sr;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t sr = sign_extend32(read_memory32(map, address));
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  sr = sign_extend32(read_memory32(map, address));
   op1 = op1 + 4;
   REG(state, m) = _register(op1);
   state->sr.value = _register(sr);
@@ -1619,9 +1826,10 @@ void ldc_l__load_to_sr(struct architectural_state * state, struct memory_map * m
 /* LDC.L @Rm+,GBR */
 void ldc_l__load_to_gbr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t gbr = sign_extend32(read_memory32(map, address));
+  int64_t op1, address, gbr;
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  gbr = sign_extend32(read_memory32(map, address));
   op1 = op1 + 4;
   REG(state, m) = _register(op1);
   state->gbr = _register(gbr);
@@ -1633,11 +1841,12 @@ void ldc_l__load_to_gbr(struct architectural_state * state, struct memory_map *
 /* LDC.L @Rm+,VBR */
 void ldc_l__load_to_vbr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, op1, address, vbr;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t vbr = sign_extend32(read_memory32(map, address));
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  vbr = sign_extend32(read_memory32(map, address));
   op1 = op1 + 4;
   REG(state, m) = _register(op1);
   state->vbr = _register(vbr);
@@ -1646,11 +1855,80 @@ void ldc_l__load_to_vbr(struct architectural_state * state, struct memory_map *
 }
 
 
+/* LDC.L @Rm+,SSR */
+void ldc_l__load_to_ssr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t md, op1, address, ssr;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  ssr = sign_extend32(read_memory32(map, address));
+  op1 = op1 + 4;
+  REG(state, m) = _register(op1);
+  state->ssr = _register(ssr);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDC.L @Rm+,SPC */
+void ldc_l__load_to_spc(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t md, op1, address, spc;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  spc = sign_extend32(read_memory32(map, address));
+  op1 = op1 + 4;
+  REG(state, m) = _register(op1);
+  state->spc = _register(spc);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDC.L @Rm+,DBR */
+void ldc_l__load_to_dbr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t md, op1, address, dbr;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  dbr = sign_extend32(read_memory32(map, address));
+  op1 = op1 + 4;
+  REG(state, m) = _register(op1);
+  state->dbr = _register(dbr);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDC.L @Rm+,Rn_BANK */
+void ldc_l__load_to_rn_bank(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
+{
+  int64_t md, op1, address, rn_bank;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  rn_bank = sign_extend32(read_memory32(map, address));
+  op1 = op1 + 4;
+  REG(state, m) = _register(op1);
+  REG_BANK(state, n) = _register(rn_bank);
+
+  state->is_delay_slot = false;
+}
+
+
 /* LDS Rm,MACH */
 void lds__transfer_to_mach(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t mach = op1;
+  int64_t op1, mach;
+  op1 = sign_extend32(REG(state, m));
+  mach = op1;
   state->mach = zero_extend32(mach);
 
   state->is_delay_slot = false;
@@ -1660,8 +1938,9 @@ void lds__transfer_to_mach(struct architectural_state * state, struct memory_map
 /* LDS Rm,MACL */
 void lds__transfer_to_macl(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t macl = op1;
+  int64_t op1, macl;
+  op1 = sign_extend32(REG(state, m));
+  macl = op1;
   state->macl = zero_extend32(macl);
 
   state->is_delay_slot = false;
@@ -1671,9 +1950,10 @@ void lds__transfer_to_macl(struct architectural_state * state, struct memory_map
 /* LDS Rm,PR */
 void lds__transfer_to_pr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t newpr = op1;
-  int64_t delayedpr = newpr;
+  int64_t op1, newpr, delayedpr;
+  op1 = sign_extend32(REG(state, m));
+  newpr = op1;
+  delayedpr = newpr;
   state->pr[1] = _register(newpr);
   state->pr[2] = _register(delayedpr);
 
@@ -1684,9 +1964,10 @@ void lds__transfer_to_pr(struct architectural_state * state, struct memory_map *
 /* LDS.L @Rm+,MACH */
 void lds_l__load_to_mach(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t mach = sign_extend32(read_memory32(map, address));
+  int64_t op1, address, mach;
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  mach = sign_extend32(read_memory32(map, address));
   op1 = op1 + 4;
   REG(state, m) = _register(op1);
   state->mach = zero_extend32(mach);
@@ -1698,9 +1979,10 @@ void lds_l__load_to_mach(struct architectural_state * state, struct memory_map *
 /* LDS.L @Rm+,MACL */
 void lds_l__load_to_macl(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t macl = sign_extend32(read_memory32(map, address));
+  int64_t op1, address, macl;
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  macl = sign_extend32(read_memory32(map, address));
   op1 = op1 + 4;
   REG(state, m) = _register(op1);
   state->macl = zero_extend32(macl);
@@ -1712,10 +1994,11 @@ void lds_l__load_to_macl(struct architectural_state * state, struct memory_map *
 /* LDS.L @Rm+,PR */
 void lds_l__load_to_pr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
 {
-  int64_t op1 = sign_extend32(REG(state, m));
-  int64_t address = zero_extend32(op1);
-  int64_t newpr = sign_extend32(read_memory32(map, address));
-  int64_t delayedpr = newpr;
+  int64_t op1, address, newpr, delayedpr;
+  op1 = sign_extend32(REG(state, m));
+  address = zero_extend32(op1);
+  newpr = sign_extend32(read_memory32(map, address));
+  delayedpr = newpr;
   op1 = op1 + 4;
   REG(state, m) = _register(op1);
   state->pr[1] = _register(newpr);
@@ -1737,13 +2020,14 @@ void nop__no_operand(struct architectural_state * state, struct memory_map * map
 /* RTE */
 void rte__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, ssr, pc, target, delayedpc;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t ssr = sign_extend32(state->ssr);
-  int64_t pc = sign_extend32(state->pc[0]);
+  ssr = sign_extend32(state->ssr);
+  pc = sign_extend32(state->pc[0]);
   if (is_delay_slot(state)) return ILLSLOT(state);
-  int64_t target = pc;
-  int64_t delayedpc = target & (~0x1);
+  target = pc;
+  delayedpc = target & (~0x1);
   state->pc[2] = _register(delayedpc);
   state->sr.value = _register(ssr);
 
@@ -1754,7 +2038,8 @@ void rte__no_operand(struct architectural_state * state, struct memory_map * map
 /* SETS */
 void sets__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t s = 1;
+  int64_t s;
+  s = 1;
   state->sr.bits.s = bit(s);
 
   state->is_delay_slot = false;
@@ -1764,7 +2049,8 @@ void sets__no_operand(struct architectural_state * state, struct memory_map * ma
 /* SETT */
 void sett__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t t = 1;
+  int64_t t;
+  t = 1;
   state->sr.bits.t = bit(t);
 
   state->is_delay_slot = false;
@@ -1774,7 +2060,8 @@ void sett__no_operand(struct architectural_state * state, struct memory_map * ma
 /* SLEEP */
 void sleep__no_operand(struct architectural_state * state, struct memory_map * map)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
   sleep(state);
 
@@ -1785,10 +2072,11 @@ void sleep__no_operand(struct architectural_state * state, struct memory_map * m
 /* STC SR,Rn */
 void stc__transfer_from_sr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, sr, op1;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t sr = sign_extend32(state->sr.value);
-  int64_t op1 = sr;
+  sr = sign_extend32(state->sr.value);
+  op1 = sr;
   REG(state, n) = _register(op1);
 
   state->is_delay_slot = false;
@@ -1798,8 +2086,9 @@ void stc__transfer_from_sr(struct architectural_state * state, struct memory_map
 /* STC GBR,Rn */
 void stc__transfer_from_gbr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t op1 = gbr;
+  int64_t gbr, op1;
+  gbr = sign_extend32(state->gbr);
+  op1 = gbr;
   REG(state, n) = _register(op1);
 
   state->is_delay_slot = false;
@@ -1809,24 +2098,96 @@ void stc__transfer_from_gbr(struct architectural_state * state, struct memory_ma
 /* STC VBR,Rn */
 void stc__transfer_from_vbr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, vbr, op1;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t vbr = sign_extend32(state->vbr);
-  int64_t op1 = vbr;
+  vbr = sign_extend32(state->vbr);
+  op1 = vbr;
   REG(state, n) = _register(op1);
 
   state->is_delay_slot = false;
 }
 
 
+/* STC SSR,Rn */
+void stc__transfer_from_ssr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t md, ssr, op1;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  ssr = sign_extend32(state->ssr);
+  op1 = ssr;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STC SPC,Rn */
+void stc__transfer_from_spc(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t md, spc, op1;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  spc = sign_extend32(state->spc);
+  op1 = spc;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STC SGR,Rn */
+void stc__transfer_from_sgr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t md, sgr, op1;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  sgr = sign_extend32(state->sgr);
+  op1 = sgr;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STC DBR,Rn */
+void stc__transfer_from_dbr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t md, dbr, op1;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  dbr = sign_extend32(state->dbr);
+  op1 = dbr;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STC Rm_BANK,Rn */
+void stc__transfer_from_rm_bank(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
+{
+  int64_t md, op1, op2;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG_BANK(state, m));
+  op2 = op1;
+  REG(state, n) = _register(op2);
+
+  state->is_delay_slot = false;
+}
+
+
 /* STC.L SR,@-Rn */
 void stc_l__store_from_sr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, sr, op1, address;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t sr = sign_extend32(state->sr.value);
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op1 - 4);
+  sr = sign_extend32(state->sr.value);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
   write_memory32(map, address, sr);
   op1 = address;
   REG(state, n) = _register(op1);
@@ -1838,9 +2199,10 @@ void stc_l__store_from_sr(struct architectural_state * state, struct memory_map
 /* STC.L GBR,@-Rn */
 void stc_l__store_from_gbr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t gbr = sign_extend32(state->gbr);
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op1 - 4);
+  int64_t gbr, op1, address;
+  gbr = sign_extend32(state->gbr);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
   write_memory32(map, address, gbr);
   op1 = address;
   REG(state, n) = _register(op1);
@@ -1852,11 +2214,12 @@ void stc_l__store_from_gbr(struct architectural_state * state, struct memory_map
 /* STC.L VBR,@-Rn */
 void stc_l__store_from_vbr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t md = zero_extend1(state->sr.bits.md);
+  int64_t md, vbr, op1, address;
+  md = zero_extend1(state->sr.bits.md);
   if (md == 0) return RESINST(state);
-  int64_t vbr = sign_extend32(state->vbr);
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op1 - 4);
+  vbr = sign_extend32(state->vbr);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
   write_memory32(map, address, vbr);
   op1 = address;
   REG(state, n) = _register(op1);
@@ -1865,11 +2228,97 @@ void stc_l__store_from_vbr(struct architectural_state * state, struct memory_map
 }
 
 
+/* STC.L SSR,@-Rn */
+void stc_l__store_from_ssr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t md, ssr, op1, address;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  ssr = sign_extend32(state->ssr);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
+  write_memory32(map, address, ssr);
+  op1 = address;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STC.L SPC,@-Rn */
+void stc_l__store_from_spc(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t md, spc, op1, address;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  spc = sign_extend32(state->spc);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
+  write_memory32(map, address, spc);
+  op1 = address;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STC.L SGR,@-Rn */
+void stc_l__store_from_sgr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t md, sgr, op1, address;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  sgr = sign_extend32(state->sgr);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
+  write_memory32(map, address, sgr);
+  op1 = address;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STC.L DBR,@-Rn */
+void stc_l__store_from_dbr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t md, dbr, op1, address;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  dbr = sign_extend32(state->dbr);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
+  write_memory32(map, address, dbr);
+  op1 = address;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STC.L Rm_BANK,@-Rn */
+void stc_l__store_from_rm_bank(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n)
+{
+  int64_t md, op1, op2, address;
+  md = zero_extend1(state->sr.bits.md);
+  if (md == 0) return RESINST(state);
+  op1 = sign_extend32(REG_BANK(state, m));
+  op2 = sign_extend32(REG(state, n));
+  address = zero_extend32(op2 - 4);
+  write_memory32(map, address, op1);
+  op2 = address;
+  REG(state, n) = _register(op2);
+
+  state->is_delay_slot = false;
+}
+
+
 /* STS MACH,Rn */
 void sts__transfer_from_mach(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t mach = sign_extend32(state->mach);
-  int64_t op1 = mach;
+  int64_t mach, op1;
+  mach = sign_extend32(state->mach);
+  op1 = mach;
   REG(state, n) = _register(op1);
 
   state->is_delay_slot = false;
@@ -1879,8 +2328,9 @@ void sts__transfer_from_mach(struct architectural_state * state, struct memory_m
 /* STS MACL,Rn */
 void sts__transfer_from_macl(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t macl = sign_extend32(state->macl);
-  int64_t op1 = macl;
+  int64_t macl, op1;
+  macl = sign_extend32(state->macl);
+  op1 = macl;
   REG(state, n) = _register(op1);
 
   state->is_delay_slot = false;
@@ -1890,8 +2340,9 @@ void sts__transfer_from_macl(struct architectural_state * state, struct memory_m
 /* STS PR,Rn */
 void sts__transfer_from_pr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t pr = sign_extend32(state->pr[1]);
-  int64_t op1 = pr;
+  int64_t pr, op1;
+  pr = sign_extend32(state->pr[1]);
+  op1 = pr;
   REG(state, n) = _register(op1);
 
   state->is_delay_slot = false;
@@ -1901,9 +2352,10 @@ void sts__transfer_from_pr(struct architectural_state * state, struct memory_map
 /* STS.L MACH,@-Rn */
 void sts_l__store_from_mach(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t mach = sign_extend32(state->mach);
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op1 - 4);
+  int64_t mach, op1, address;
+  mach = sign_extend32(state->mach);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
   write_memory32(map, address, mach);
   op1 = address;
   REG(state, n) = _register(op1);
@@ -1915,9 +2367,10 @@ void sts_l__store_from_mach(struct architectural_state * state, struct memory_ma
 /* STS.L MACL,@-Rn */
 void sts_l__store_from_macl(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t macl = sign_extend32(state->macl);
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op1 - 4);
+  int64_t macl, op1, address;
+  macl = sign_extend32(state->macl);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
   write_memory32(map, address, macl);
   op1 = address;
   REG(state, n) = _register(op1);
@@ -1929,9 +2382,10 @@ void sts_l__store_from_macl(struct architectural_state * state, struct memory_ma
 /* STS.L PR,@-Rn */
 void sts_l__store_from_pr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
 {
-  int64_t pr = sign_extend32(state->pr[1]);
-  int64_t op1 = sign_extend32(REG(state, n));
-  int64_t address = zero_extend32(op1 - 4);
+  int64_t pr, op1, address;
+  pr = sign_extend32(state->pr[1]);
+  op1 = sign_extend32(REG(state, n));
+  address = zero_extend32(op1 - 4);
   write_memory32(map, address, pr);
   op1 = address;
   REG(state, n) = _register(op1);
@@ -1943,10 +2397,143 @@ void sts_l__store_from_pr(struct architectural_state * state, struct memory_map
 /* TRAPA #imm */
 void trapa__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i)
 {
-  int64_t imm = zero_extend8(i);
+  int64_t imm;
+  imm = zero_extend8(i);
   if (is_delay_slot(state)) return ILLSLOT(state);
   return TRAP(state, imm);
 
   state->is_delay_slot = false;
 }
 
+
+/* LDS Rm,FPSCR */
+void lds__transfer_to_fpscr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t sr, op1;
+  sr = zero_extend32(state->sr.value);
+  op1 = sign_extend32(REG(state, m));
+  if (fpu_is_disabled(sr) && is_delay_slot(state)) return SLOTFPUDIS(state);
+  if (fpu_is_disabled(sr)) return FPUDIS(state);
+  state->fpscr.value = zero_extend32(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDS Rm,FPUL */
+void lds__transfer_to_fpul(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t sr, op1, fpul;
+  sr = zero_extend32(state->sr.value);
+  op1 = sign_extend32(REG(state, m));
+  if (fpu_is_disabled(sr) && is_delay_slot(state)) return SLOTFPUDIS(state);
+  if (fpu_is_disabled(sr)) return FPUDIS(state);
+  fpul = op1;
+  state->fpul = zero_extend32(fpul);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDS.L @Rm+,FPSCR */
+void lds_l__load_to_fpscr(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t sr, op1, address, value;
+  sr = zero_extend32(state->sr.value);
+  op1 = sign_extend32(REG(state, m));
+  if (fpu_is_disabled(sr) && is_delay_slot(state)) return SLOTFPUDIS(state);
+  if (fpu_is_disabled(sr)) return FPUDIS(state);
+  address = zero_extend32(op1);
+  value = read_memory32(map, address);
+  op1 = op1 + 4;
+  REG(state, m) = _register(op1);
+  state->fpscr.value = zero_extend32(value);
+
+  state->is_delay_slot = false;
+}
+
+
+/* LDS.L @Rm+,FPUL */
+void lds_l__load_to_fpul(struct architectural_state * state, struct memory_map * map, const uint32_t m)
+{
+  int64_t sr, op1, address, fpul;
+  sr = zero_extend32(state->sr.value);
+  op1 = sign_extend32(REG(state, m));
+  if (fpu_is_disabled(sr) && is_delay_slot(state)) return SLOTFPUDIS(state);
+  if (fpu_is_disabled(sr)) return FPUDIS(state);
+  address = zero_extend32(op1);
+  fpul = read_memory32(map, address);
+  op1 = op1 + 4;
+  REG(state, m) = _register(op1);
+  state->fpul = zero_extend32(fpul);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STS FPSCR,Rn */
+void sts__transfer_from_fpscr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t sr, fps, op1;
+  sr = zero_extend32(state->sr.value);
+  fps = zero_extend32(state->fpscr.value);
+  if (fpu_is_disabled(sr) && is_delay_slot(state)) return SLOTFPUDIS(state);
+  if (fpu_is_disabled(sr)) return FPUDIS(state);
+  op1 = fps;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STS FPUL,Rn */
+void sts__transfer_from_fpul(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t sr, fpul, op1;
+  sr = zero_extend32(state->sr.value);
+  fpul = sign_extend32(state->fpul);
+  if (fpu_is_disabled(sr) && is_delay_slot(state)) return SLOTFPUDIS(state);
+  if (fpu_is_disabled(sr)) return FPUDIS(state);
+  op1 = fpul;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STS.L FPSCR,@-Rn */
+void sts_l__store_from_fpscr(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t sr, fps, op1, value, address;
+  sr = zero_extend32(state->sr.value);
+  fps = zero_extend32(state->fpscr.value);
+  op1 = sign_extend32(REG(state, n));
+  if (fpu_is_disabled(sr) && is_delay_slot(state)) return SLOTFPUDIS(state);
+  if (fpu_is_disabled(sr)) return FPUDIS(state);
+  value = fps;
+  address = zero_extend32(op1 - 4);
+  write_memory32(map, address, value);
+  op1 = address;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
+
+/* STS.L FPUL,@-Rn */
+void sts_l__store_from_fpul(struct architectural_state * state, struct memory_map * map, const uint32_t n)
+{
+  int64_t sr, fpul, op1, address;
+  sr = zero_extend32(state->sr.value);
+  fpul = sign_extend32(state->fpul);
+  op1 = sign_extend32(REG(state, n));
+  if (fpu_is_disabled(sr) && is_delay_slot(state)) return SLOTFPUDIS(state);
+  if (fpu_is_disabled(sr)) return FPUDIS(state);
+  address = zero_extend32(op1 - 4);
+  write_memory32(map, address, fpul);
+  op1 = address;
+  REG(state, n) = _register(op1);
+
+  state->is_delay_slot = false;
+}
+
diff --git a/c/impl.h b/c/impl.h
index c7f16f2..17eb185 100644
--- a/c/impl.h
+++ b/c/impl.h
@@ -183,10 +183,14 @@ void rotr__destination_operand_only(struct architectural_state * state, struct m
 void rotcl__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n);
 /* ROTCR Rn */
 void rotcr__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* SHAD Rm,Rn */
+void shad__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n);
 /* SHAL Rn */
 void shal__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n);
 /* SHAR Rn */
 void shar__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* SHLD Rm,Rn */
+void shld__source_and_destination_operands(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n);
 /* SHLL Rn */
 void shll__destination_operand_only(struct architectural_state * state, struct memory_map * map, const uint32_t n);
 /* SHLR Rn */
@@ -237,12 +241,28 @@ void ldc__transfer_to_sr(struct architectural_state * state, struct memory_map *
 void ldc__transfer_to_gbr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
 /* LDC Rm,VBR */
 void ldc__transfer_to_vbr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDC Rm,SSR */
+void ldc__transfer_to_ssr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDC Rm,SPC */
+void ldc__transfer_to_spc(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDC Rm,DBR */
+void ldc__transfer_to_dbr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDC Rm,Rn_BANK */
+void ldc__transfer_to_rn_bank(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n);
 /* LDC.L @Rm+,SR */
 void ldc_l__load_to_sr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
 /* LDC.L @Rm+,GBR */
 void ldc_l__load_to_gbr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
 /* LDC.L @Rm+,VBR */
 void ldc_l__load_to_vbr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDC.L @Rm+,SSR */
+void ldc_l__load_to_ssr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDC.L @Rm+,SPC */
+void ldc_l__load_to_spc(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDC.L @Rm+,DBR */
+void ldc_l__load_to_dbr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDC.L @Rm+,Rn_BANK */
+void ldc_l__load_to_rn_bank(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n);
 /* LDS Rm,MACH */
 void lds__transfer_to_mach(struct architectural_state * state, struct memory_map * map, const uint32_t m);
 /* LDS Rm,MACL */
@@ -271,12 +291,32 @@ void stc__transfer_from_sr(struct architectural_state * state, struct memory_map
 void stc__transfer_from_gbr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
 /* STC VBR,Rn */
 void stc__transfer_from_vbr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC SSR,Rn */
+void stc__transfer_from_ssr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC SPC,Rn */
+void stc__transfer_from_spc(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC SGR,Rn */
+void stc__transfer_from_sgr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC DBR,Rn */
+void stc__transfer_from_dbr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC Rm_BANK,Rn */
+void stc__transfer_from_rm_bank(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n);
 /* STC.L SR,@-Rn */
 void stc_l__store_from_sr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
 /* STC.L GBR,@-Rn */
 void stc_l__store_from_gbr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
 /* STC.L VBR,@-Rn */
 void stc_l__store_from_vbr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC.L SSR,@-Rn */
+void stc_l__store_from_ssr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC.L SPC,@-Rn */
+void stc_l__store_from_spc(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC.L SGR,@-Rn */
+void stc_l__store_from_sgr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC.L DBR,@-Rn */
+void stc_l__store_from_dbr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STC.L Rm_BANK,@-Rn */
+void stc_l__store_from_rm_bank(struct architectural_state * state, struct memory_map * map, const uint32_t m, const uint32_t n);
 /* STS MACH,Rn */
 void sts__transfer_from_mach(struct architectural_state * state, struct memory_map * map, const uint32_t n);
 /* STS MACL,Rn */
@@ -290,4 +330,20 @@ void sts_l__store_from_macl(struct architectural_state * state, struct memory_ma
 /* STS.L PR,@-Rn */
 void sts_l__store_from_pr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
 /* TRAPA #imm */
-void trapa__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i);
\ No newline at end of file
+void trapa__immediate(struct architectural_state * state, struct memory_map * map, const uint32_t i);
+/* LDS Rm,FPSCR */
+void lds__transfer_to_fpscr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDS Rm,FPUL */
+void lds__transfer_to_fpul(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDS.L @Rm+,FPSCR */
+void lds_l__load_to_fpscr(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* LDS.L @Rm+,FPUL */
+void lds_l__load_to_fpul(struct architectural_state * state, struct memory_map * map, const uint32_t m);
+/* STS FPSCR,Rn */
+void sts__transfer_from_fpscr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STS FPUL,Rn */
+void sts__transfer_from_fpul(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STS.L FPSCR,@-Rn */
+void sts_l__store_from_fpscr(struct architectural_state * state, struct memory_map * map, const uint32_t n);
+/* STS.L FPUL,@-Rn */
+void sts_l__store_from_fpul(struct architectural_state * state, struct memory_map * map, const uint32_t n);
\ No newline at end of file
diff --git a/c/operations.h b/c/operations.h
index 6c9d181..8cfbcff 100644
--- a/c/operations.h
+++ b/c/operations.h
@@ -64,6 +64,11 @@ static inline uint32_t zero_extend8(uint32_t x)
   return zero_extend(x, 8);
 }
 
+static inline uint32_t zero_extend5(uint32_t x)
+{
+  return zero_extend(x, 5);
+}
+
 static inline uint32_t zero_extend4(uint32_t x)
 {
   return zero_extend(x, 4);
diff --git a/c/sr_bits.h b/c/sr_bits.h
deleted file mode 100644
index 8ed6eef..0000000
--- a/c/sr_bits.h
+++ /dev/null
@@ -1,39 +0,0 @@
-#pragma once
-
-#include <stdint.h>
-
-struct sr_bits {
-#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-  uint32_t t : 1;
-  uint32_t s : 1;
-  uint32_t _res0 : 2;
-  uint32_t imask : 4;
-  uint32_t _res1 : 3;
-  uint32_t q : 1;
-  uint32_t m : 1;
-  uint32_t _res2 : 5;
-  uint32_t fd : 1;
-  uint32_t _res3 : 12;
-  uint32_t bl : 1;
-  uint32_t rb : 1;
-  uint32_t md : 1;
-  uint32_t _res4 : 1;
-#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
-  uint32_t _res4 : 1;
-  uint32_t md : 1;
-  uint32_t rb : 1;
-  uint32_t bl : 1;
-  uint32_t _res3 : 12;
-  uint32_t fd : 1;
-  uint32_t _res2 : 5;
-  uint32_t m : 1;
-  uint32_t q : 1;
-  uint32_t _res1 : 3;
-  uint32_t imask : 4;
-  uint32_t _res0 : 2;
-  uint32_t s : 1;
-  uint32_t t : 1;
-#else
-# error "unsupported endianness"
-#endif
-};
diff --git a/c/state.h b/c/state.h
index 4fab23f..b731587 100644
--- a/c/state.h
+++ b/c/state.h
@@ -4,7 +4,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-#include "sr_bits.h"
+#include "status_bits.h"
 
 #define SR__RB (1 << 29)
 #define SR__MD (1 << 30)
@@ -33,6 +33,29 @@ static_assert(REGN_BANK(SR__MD | SR__RB, 7 ) == 7 );
 static_assert(REGN_BANK(SR__MD | SR__RB, 8 ) == 8 );
 static_assert(REGN_BANK(SR__MD | SR__RB, 15) == 15);
 
+union floating_point_registers {
+  uint32_t fr[32];
+  uint32_t fp[16][2];
+  uint64_t dr[16];
+  uint32_t fv[8][4];
+  uint32_t fm[2][16];
+};
+
+static_assert((sizeof (union floating_point_registers)) == 32 * 4);
+
+#define FR_N(state, x) ((x) ^ ((state)->fpscr.fr << 4))
+#define FR_(state, x) ((state)->floating_point_register.fr[FR_N(state, x)])
+#define FP_N(state, x) ((x) ^ ((state)->fpscr.fr << 3))
+#define FP_(state, x) ((state)->floating_point_register.fp[FP_N(state, x)])
+#define DR2_N(state, x) ((x) ^ ((state)->fpscr.fr << 3))
+#define DR2_(state, x) ((state)->floating_point_register.dr[DR2_N(state, x)])
+#define XD2_N(state, x) ((x) ^ ((!(state)->fpscr.fr) << 3))
+#define XD2_(state, x) ((state)->floating_point_register.dr[XD2_N(state, x)])
+#define FV4_N(state, x) ((x) ^ ((state)->fpscr.fr << 2))
+#define FV4_(state, x) ((state)->floating_point_register.dr[FV4_N(state, x)])
+#define XMTRX_N(state) (!(state)->fpscr.fr)
+#define XMTRX(state) ((state)->floating_point_register.fm[XMTRX_N(state)])
+
 struct architectural_state {
   uint32_t general_register[24];
 
@@ -41,7 +64,10 @@ struct architectural_state {
   uint32_t macl;
   uint32_t pr[3];
   uint32_t pc[3];
-  uint32_t fpscr;
+  union {
+    struct fpscr_bits bits;
+    uint32_t value;
+  } fpscr;
   uint32_t fpul;
   //
 
@@ -58,7 +84,7 @@ struct architectural_state {
   uint32_t dbr;
   //
 
-  uint32_t floating_point_register[32];
+  union floating_point_registers floating_point_register;
 
   bool is_delay_slot;
 };
diff --git a/c/state_helpers.h b/c/state_helpers.h
index ab0958d..ccc08e4 100644
--- a/c/state_helpers.h
+++ b/c/state_helpers.h
@@ -5,12 +5,28 @@
 
 #include "state.h"
 #include "memory_map.h"
+#include "status_bits.h"
 
 static inline bool is_delay_slot(struct architectural_state * state)
 {
   return state->is_delay_slot;
 }
 
+static inline struct sr_bits _sr_bits(uint32_t sr)
+{
+  union {
+    struct sr_bits bits;
+    uint32_t value;
+  } sr_union;
+  sr_union.value = sr;
+  return sr_union.bits;
+}
+
+static inline bool fpu_is_disabled(uint32_t sr)
+{
+  return _sr_bits(sr).fd;
+}
+
 static inline void sleep(struct architectural_state * state)
 {
 }
diff --git a/c/status_bits.h b/c/status_bits.h
new file mode 100644
index 0000000..3449c78
--- /dev/null
+++ b/c/status_bits.h
@@ -0,0 +1,96 @@
+#pragma once
+
+#include <stdint.h>
+
+
+struct sr_bits {
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+  uint32_t t : 1;
+  uint32_t s : 1;
+  uint32_t _res0 : 2;
+  uint32_t imask : 4;
+  uint32_t _res1 : 3;
+  uint32_t q : 1;
+  uint32_t m : 1;
+  uint32_t _res2 : 5;
+  uint32_t fd : 1;
+  uint32_t _res3 : 12;
+  uint32_t bl : 1;
+  uint32_t rb : 1;
+  uint32_t md : 1;
+  uint32_t _res4 : 1;
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+  uint32_t _res4 : 1;
+  uint32_t md : 1;
+  uint32_t rb : 1;
+  uint32_t bl : 1;
+  uint32_t _res3 : 12;
+  uint32_t fd : 1;
+  uint32_t _res2 : 5;
+  uint32_t m : 1;
+  uint32_t q : 1;
+  uint32_t _res1 : 3;
+  uint32_t imask : 4;
+  uint32_t _res0 : 2;
+  uint32_t s : 1;
+  uint32_t t : 1;
+#else
+# error "unsupported endianness"
+#endif
+};
+
+
+struct fpscr_bits {
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+  uint32_t rm : 1;
+  uint32_t _res0 : 1;
+  uint32_t flag_inexact : 1;
+  uint32_t flag_underflow : 1;
+  uint32_t flag_overflow : 1;
+  uint32_t flag_division_by_zero : 1;
+  uint32_t flag_invalid_operation : 1;
+  uint32_t enable_inexact : 1;
+  uint32_t enable_underflow : 1;
+  uint32_t enable_overflow : 1;
+  uint32_t enable_division_by_zero : 1;
+  uint32_t enable_invalid : 1;
+  uint32_t cause_inexact : 1;
+  uint32_t cause_underflow : 1;
+  uint32_t cause_overflow : 1;
+  uint32_t cause_division_by_zero : 1;
+  uint32_t cause_invalid : 1;
+  uint32_t cause_fpu_error : 1;
+  uint32_t dn : 1;
+  uint32_t pr : 1;
+  uint32_t sz : 1;
+  uint32_t fr : 1;
+  uint32_t _res1 : 10;
+#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+  uint32_t _res1 : 10;
+  uint32_t fr : 1;
+  uint32_t sz : 1;
+  uint32_t pr : 1;
+  uint32_t dn : 1;
+  uint32_t cause_fpu_error : 1;
+  uint32_t cause_invalid : 1;
+  uint32_t cause_division_by_zero : 1;
+  uint32_t cause_overflow : 1;
+  uint32_t cause_underflow : 1;
+  uint32_t cause_inexact : 1;
+  uint32_t enable_invalid : 1;
+  uint32_t enable_division_by_zero : 1;
+  uint32_t enable_overflow : 1;
+  uint32_t enable_underflow : 1;
+  uint32_t enable_inexact : 1;
+  uint32_t flag_invalid_operation : 1;
+  uint32_t flag_division_by_zero : 1;
+  uint32_t flag_overflow : 1;
+  uint32_t flag_underflow : 1;
+  uint32_t flag_inexact : 1;
+  uint32_t _res0 : 1;
+  uint32_t rm : 1;
+#else
+# error "unsupported endianness"
+#endif
+};
+
diff --git a/generate_bits.py b/generate_bits.py
new file mode 100644
index 0000000..43b8cd2
--- /dev/null
+++ b/generate_bits.py
@@ -0,0 +1,79 @@
+sr_bits = (
+    ("T"    , 0 , 1),  # true/false condition
+    ("S"    , 1 , 1),  # saturation
+    ("IMASK", 4 , 4),  # interrupt mask level, 4 bits
+    ("Q"    , 8 , 1),  # state for divide step
+    ("M"    , 9 , 1),  # state for divide step
+    ("FD"   , 15, 1),  # FPU disable
+    ("BL"   , 28, 1),  # Exception/interrupt block bit
+    ("RB"   , 29, 1),  # General register bank specifier in privileged mode
+    ("MD"   , 30, 1),  # Processor mode
+)
+
+fpscr_bits = (
+    ("RM"                     , 0,  1), # Rounding mode
+    ("FLAG_INEXACT"           , 2,  1),
+    ("FLAG_UNDERFLOW"         , 3,  1),
+    ("FLAG_OVERFLOW"          , 4,  1),
+    ("FLAG_DIVISION_BY_ZERO"  , 5,  1),
+    ("FLAG_INVALID_OPERATION" , 6,  1),
+    ("ENABLE_INEXACT"         , 7,  1),
+    ("ENABLE_UNDERFLOW"       , 8,  1),
+    ("ENABLE_OVERFLOW"        , 9,  1),
+    ("ENABLE_DIVISION_BY_ZERO", 10, 1),
+    ("ENABLE_INVALID"         , 11, 1),
+    ("CAUSE_INEXACT"          , 12, 1),
+    ("CAUSE_UNDERFLOW"        , 13, 1),
+    ("CAUSE_OVERFLOW"         , 14, 1),
+    ("CAUSE_DIVISION_BY_ZERO" , 15, 1),
+    ("CAUSE_INVALID"          , 16, 1),
+    ("CAUSE_FPU_ERROR"        , 17, 1),
+    ("DN"                     , 18, 1), # Denormalization mode
+    ("PR"                     , 19, 1), # Precision mode
+    ("SZ"                     , 20, 1), # Transfer size mode
+    ("FR"                     , 21, 1), # Floating-point register bank
+)
+
+def generate_bitfield(bits, start=0, end=31):
+    res = 0
+    current = start
+    for name, index, length in bits:
+        if index != current:
+            size = index - current
+            yield f"_res{res}", size
+            res += 1
+        yield name, length
+        current = index + 1
+
+    end_len = end + 1
+    if current != end_len:
+        yield f"_res{res}", end_len - current
+
+def generate_bitfield_little(bits):
+    return generate_bitfield(bits)
+
+def generate_bitfield_big(bits):
+    return reversed(list(generate_bitfield(bits)))
+
+def generate(struct_name, bits):
+    yield ""
+    yield f"struct {struct_name} {{"
+    yield "#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__"
+    for name, size in generate_bitfield_little(bits):
+        yield f"  uint32_t {name.lower()} : {size};"
+    yield "#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__"
+    for name, size in generate_bitfield_big(bits):
+        yield f"  uint32_t {name.lower()} : {size};"
+    yield "#else"
+    yield '# error "unsupported endianness"'
+    yield "#endif"
+    yield "};"
+    yield ""
+
+if __name__ == "__main__":
+    print("#pragma once")
+    print()
+    print("#include <stdint.h>")
+    print()
+    print('\n'.join(generate("sr_bits", sr_bits)))
+    print('\n'.join(generate("fpscr_bits", fpscr_bits)))
diff --git a/transform.py b/generate_impl.py
similarity index 77%
rename from transform.py
rename to generate_impl.py
index 5a8681f..7ccf878 100644
--- a/transform.py
+++ b/generate_impl.py
@@ -3,7 +3,8 @@ import os
 
 from lexer import Lexer
 from parser import Parser
-from generator import generate, CTX
+from ast_to_c_source import generate
+from ast_transformers import transform_statements
 
 from instruction_table import untabulate_instructions_sh4
 from instruction_table import untabulate_instructions_sh2
@@ -52,17 +53,20 @@ def generate_function_declaration(instruction_name, function_name, variables):
     yield f"void {function_name}({args})"
 
 def generate_file(instruction_name, function_name, variables, delay_slot, src_path):
+    print(instruction_name)
     tokens = list(parse_file(src_path))
     parser = Parser(tokens)
+    statements = []
+    while parser.tokens[parser.pos:]:
+        statements.append(parser.statement())
 
-    ctx = CTX(identifiers=set())
+    statements = transform_statements(statements)
 
     yield from generate_function_declaration(instruction_name, function_name, variables)
     yield "{"
     output = []
-    while parser.tokens[parser.pos:]:
-        stmt = parser.statement()
-        src = "".join(generate(ctx, stmt))
+    for statement in statements:
+        src = "".join(generate(statement))
         output.append(src)
 
     for line in "".join(output).rstrip().split('\n'):
@@ -90,10 +94,49 @@ def main():
         '',
     ]
 
-    sh2_instructions = set((ins.instruction, ins.operands) for ins in untabulate_instructions_sh2())
+    skip = [
+        "FLDS",
+        "FSTS",
+        "FABS",
+        "FADD",
+        "FCMP/EQ",
+        "FCMP/GT",
+        "FDIV",
+        "FLOAT",
+        "FMAC",
+        "FMUL",
+        "FNEG",
+        "FSQRT",
+        "FSUB",
+        "FTRC",
+        "FCNVDS",
+        "FCNVSD",
+        "FRCHG",
+        "FSCHG",
+        "FCSA",
+        "FSRRA",
+        "FIPR",
+        "FTRV",
+
+        "FLDI0",
+        "FLDI1",
+        "FMOV",
+        "FMOV.S",
+
+        "LDTLB",
+        "OCBI",
+        "OCBP",
+        "OCBWB",
+        "PREF",
+
+        "MOVCA.L",
+        "BRK",
+    ]
+
     for ins in untabulate_instructions_sh4():
-        if (ins.instruction, ins.operands) not in sh2_instructions:
+        if ins.instruction in skip:
             continue
+
         _name = [ins.instruction, ins.operands] if ins.operands else [ins.instruction]
         instruction_name = " ".join(_name)
         function_name = instruction_function_name(ins)
diff --git a/generator.py b/generator.py
deleted file mode 100644
index acb4a9f..0000000
--- a/generator.py
+++ /dev/null
@@ -1,301 +0,0 @@
-from dataclasses import dataclass
-
-from parser import Tree
-from lexer import Identifier, Punctuator, IntegerConstant
-import identifier_substitution
-
-@dataclass
-class CTX:
-    identifiers: set
-
-def argument_list(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield ", "
-    yield from generate(ctx, tree.children[1])
-
-def _is_new_temporary(ctx, tree):
-    return (
-        type(tree) is Identifier
-        and tree.token not in identifier_substitution.mapping
-        and tree.token not in ctx.identifiers
-    )
-
-def assignment(ctx, tree):
-    lhs = tree.children[0]
-    rhs = tree.children[1]
-    if _is_new_temporary(ctx, lhs):
-        ctx.identifiers.add(lhs.token)
-        yield "int64_t "
-
-    yield from generate(ctx, tree.children[0])
-    yield " = "
-    yield from generate(ctx, tree.children[1])
-
-def bit_extraction(ctx, tree):
-    yield "bit_extract("
-    yield from generate(ctx, tree.children[0])
-    yield ", "
-    yield from generate(ctx, tree.children[1])
-    yield ")"
-
-def bitwise_and(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " & "
-    yield from generate(ctx, tree.children[1])
-
-def bitwise_or(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " | "
-    yield from generate(ctx, tree.children[1])
-
-def bitwise_xor(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " ^ "
-    yield from generate(ctx, tree.children[1])
-
-def block_item_list(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield from generate(ctx, tree.children[1])
-
-def compound_statement(ctx, tree):
-    yield "\n{\n"
-    if tree.children:
-        yield from generate(ctx, tree.children[0])
-    yield "}\n"
-
-def expression_statement(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield ";\n"
-
-def for_expression(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield ", "
-    if len(tree.children) > 1:
-        yield from generate(ctx, tree.children[1])
-    else:
-        yield "1"
-
-def helper_arguments(tree):
-    if type(tree.children[0]) is not Identifier:
-        return
-    name = tree.children[0].token
-    mapping = {
-        "IsDelaySlot": "state",
-        "SLEEP": "state",
-        "OCBP" : "state",
-        "WriteMemory8" : "map",
-        "WriteMemory16": "map",
-        "WriteMemory32": "map",
-        "ReadMemory8"  : "map",
-        "ReadMemory16" : "map",
-        "ReadMemory32" : "map",
-    }
-    return mapping.get(name, None)
-
-def function_call(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield "("
-    if len(tree.children) >= 2:
-        if helper_arguments(tree):
-            yield helper_arguments(tree)
-            yield ", "
-        yield from generate(ctx, tree.children[1])
-    else:
-        if helper_arguments(tree):
-            yield helper_arguments(tree)
-    yield ")"
-
-def grouping(ctx, tree):
-    yield "("
-    yield from generate(ctx, tree.children[0])
-    yield ")"
-
-def _if(ctx, tree):
-    yield "if ("
-    yield from generate(ctx, tree.children[0])
-    yield ") "
-    yield from generate(ctx, tree.children[1])
-
-def if_else(ctx, tree):
-    yield "if ("
-    yield from generate(ctx, tree.children[0])
-    yield ") "
-    yield from generate(ctx, tree.children[1])
-    yield "else "
-    yield from generate(ctx, tree.children[2])
-
-def logical_and(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " && "
-    yield from generate(ctx, tree.children[1])
-
-def logical_or(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " || "
-    yield from generate(ctx, tree.children[1])
-
-def member(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield "."
-    yield from generate(ctx, tree.children[1])
-
-def subscript(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield "["
-    yield from generate(ctx, tree.children[1])
-    yield "]"
-
-def throw(ctx, tree):
-    yield "return "
-    yield from generate(ctx, tree.children[0])
-    yield "(state);\n"
-
-def throw_arg(ctx, tree):
-    yield "return "
-    yield from generate(ctx, tree.children[0])
-    yield "(state, "
-    yield from generate(ctx, tree.children[1])
-    yield ");\n"
-
-def unary_complement(ctx, tree):
-    yield from "~"
-    yield from generate(ctx, tree.children[0])
-
-def unary_int(ctx, tree):
-    yield "unary_int("
-    yield from generate(ctx, tree.children[0])
-    yield ")"
-
-def unary_negation(ctx, tree):
-    yield "-"
-    yield from generate(ctx, tree.children[0])
-
-def unary_not(ctx, tree):
-    yield "!"
-    yield from generate(ctx, tree.children[0])
-
-#
-def addition(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " + "
-    yield from generate(ctx, tree.children[1])
-
-def division(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " / "
-    yield from generate(ctx, tree.children[1])
-
-def equality_equal(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " == "
-    yield from generate(ctx, tree.children[1])
-
-def equality_not_equal(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " != "
-    yield from generate(ctx, tree.children[1])
-
-def greater_than(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " > "
-    yield from generate(ctx, tree.children[1])
-
-def greater_than_equal(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " >= "
-    yield from generate(ctx, tree.children[1])
-
-def left_shift(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    # hack for left shift by LHS constant
-    if type(tree.children[0]) is IntegerConstant:
-        yield "LL"
-    yield " << "
-    yield from generate(ctx, tree.children[1])
-
-def less_than(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " < "
-    yield from generate(ctx, tree.children[1])
-
-def less_than_equal(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " <= "
-    yield from generate(ctx, tree.children[1])
-
-def multiplication(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " * "
-    yield from generate(ctx, tree.children[1])
-
-def right_shift(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " >> "
-    yield from generate(ctx, tree.children[1])
-
-def subtraction(ctx, tree):
-    yield from generate(ctx, tree.children[0])
-    yield " - "
-    yield from generate(ctx, tree.children[1])
-
-def identifier(ctx, token):
-    if token.token in identifier_substitution.mapping:
-        yield identifier_substitution.mapping[token.token]
-    else:
-        assert token.token.lower() == token.token, token
-        if token.token not in {'m', 'n', 'i', 'd'}:
-            assert token.token in ctx.identifiers, (token, ctx.identifiers)
-        yield token.token
-
-def constant(ctx, elem):
-    yield elem.token.lower()
-
-def generate(ctx, elem):
-    mapping = {
-        "argument_list": argument_list,
-        "assignment": assignment,
-        "bit_extraction": bit_extraction,
-        "bitwise_and": bitwise_and,
-        "bitwise_or": bitwise_or,
-        "bitwise_xor": bitwise_xor,
-        "block_item_list": block_item_list,
-        "compound_statement": compound_statement,
-        "expression_statement": expression_statement,
-        "for_expression": for_expression,
-        "function_call": function_call,
-        "grouping": grouping,
-        "if": _if,
-        "if_else": if_else,
-        "logical_and": logical_and,
-        "logical_or": logical_or,
-        "member": member,
-        "subscript": subscript,
-        "throw": throw,
-        "throw_arg": throw_arg,
-        "unary_complement": unary_complement,
-        "unary_int": unary_int,
-        "unary_negation": unary_negation,
-        "unary_not": unary_not,
-        #
-        "addition": addition,
-        "division": division,
-        "equality_equal": equality_equal,
-        "equality_not_equal": equality_not_equal,
-        "greater_than": greater_than,
-        "greater_than_equal": greater_than_equal,
-        "left_shift": left_shift,
-        "less_than": less_than,
-        "less_than_equal": less_than_equal,
-        "multiplication": multiplication,
-        "right_shift": right_shift,
-        "subtraction": subtraction,
-        #
-    }
-    if type(elem) is Tree:
-        yield from mapping[elem.operation](ctx, elem)
-    elif type(elem) is Identifier:
-        yield from identifier(ctx, elem)
-    elif type(elem) is IntegerConstant:
-        yield from constant(ctx, elem)
-    else:
-        assert False, type(elem)
diff --git a/identifier_substitution.py b/identifier_substitution.py
index 677c5d9..898a6be 100644
--- a/identifier_substitution.py
+++ b/identifier_substitution.py
@@ -28,7 +28,7 @@ mapping = {
     "PC"              : "state->pc[0]",
     "PC’"             : "state->pc[1]",
     "PC’’"            : "state->pc[2]",
-    "FPSCR"           : "state->fpscr",
+    "FPSCR"           : "state->fpscr.value",
     "FPUL"            : "state->fpul",
 
     "SR"              : "state->sr.value",
@@ -71,37 +71,111 @@ mapping = {
     "IsDelaySlot"     : "is_delay_slot",
     "SLEEP"           : "sleep",
     "OCBP"            : "ocbp",
+
+    "ASID"            : "ASID",
+    "VPN"             : "VPN",
+    "PPN"             : "PPN",
+    "SZ"              : "SZ",
+    "SZ0"             : "SZ0",
+    "SZ1"             : "SZ1",
+    "SH"              : "SH",
+    "WT"              : "WT",
+    "C"               : "C",
+    "D"               : "D",
+    "V"               : "V",
+
+    "ALLOCO"          : "ALLOCO",
+    "MMU"             : "MMU",
+    "MMUCR"           : "MMUCR",
+    "OCBI"            : "OCBI",
+    "OCBWB"           : "OCBWB",
+    "PREF"            : "PREF",
+    "PTEH"            : "PTEH",
+    "PTEL"            : "PTEL",
+    "URC"             : "URC",
+    "UTLB"            : "UTLB",
+
+    "AddressUnavailable": "address_unavailable",
+    "DataAccessMiss"  : "data_access_miss",
+    "DirtyBit"        : "dirty_bit",
+    "ReadProhibited"  : "read_prohibited",
+    "WriteProhibited" : "write_prohibited",
+
+    "FR0"             : "FR_(state, 0)",
+    "FRm"             : "FR_(state, m)",
+    "FRn"             : "FR_(state, n)",
+    "FP2m"            : "FP2_(state, m)",
+    "FP2n"            : "FP2_(state, n)",
+    "DR2m"            : "DR2_(state, m)",
+    "DR2n"            : "DR2_(state, n)",
+    "XD2m"            : "XD2_(state, m)",
+    "XD2n"            : "XD2_(state, n)",
+    "FV4n"            : "FV4_(state, n)",
+    "FV4m"            : "FV4_(state, m)",
+    "XMTRX"           : "XMTRX(state)",
+
+    "FR"              : "fr",
+
+    "ReadMemoryPair32"    : "read_memory_pair32",
+    "WriteMemoryPair32"   : "write_memory_pair32",
+
+    "FloatRegister32"      : "float_register32",
+    "FloatRegister64"      : "float_register64",
+    "FloatRegisterPair32"  : "float_register_pair32",
+    "FloatRegisterVector32": "float_register_vector32",
+    "FloatValue32"         : "float_value32",
+    "FloatValue64"         : "float_value64",
+    "FloatValuePair32"     : "float_value_pair32",
+    "FloatValueVector32"   : "float_value_vector32",
+    "FloatValueMatrix32"   : "float_value_matrix32",
+
+    "FADD_S"              : "fadd_s",
+    "FADD_D"              : "fadd_d",
+    "FSUB_S"              : "fsub_s",
+    "FSUB_D"              : "fsub_d",
+    "FMUL_S"              : "fmul_s",
+    "FMUL_D"              : "fmul_d",
+    "FDIV_S"              : "fdiv_s",
+    "FDIV_D"              : "fdiv_d",
+
+    "FABS_S"              : "fabs_s",
+    "FABS_D"              : "fabs_d",
+    "FNEG_S"              : "fneg_s",
+    "FNEG_D"              : "fneg_d",
+    "FSQRT_S"             : "fsqrt_s",
+    "FSQRT_D"             : "fsqrt_d",
+
+    "FCMPEQ_S"            : "fcmpeq_s",
+    "FCMPEQ_D"            : "fcmpeq_d",
+    "FCMPGT_S"            : "fcmpgt_s",
+    "FCMPGT_D"            : "fcmpgt_d",
+
+    "FCNV_SD"             : "fcnv_sd",
+    "FCNV_DS"             : "fcnv_ds",
+    "FTRC_SL"             : "ftrc_sl",
+    "FTRC_DL"             : "ftrc_dl",
+    "FLOAT_LS"            : "float_ls",
+    "FLOAT_LD"            : "float_ld",
+
+    "FMAC_S"              : "fmac_s",
+    "FIPR_S"              : "fipr_s",
+    "FTRV_S"              : "ftrv_s",
+
+    "FpuIsDisabled"       : "fpu_is_disabled",
+    "FpuFlagI"            : "fpu_flag_I",
+    "FpuFlagU"            : "fpu_flag_U",
+    "FpuFlagO"            : "fpu_flag_O",
+    "FpuFlagZ"            : "fpu_flag_Z",
+    "FpuFlagV"            : "fpu_flag_V",
+    "FpuCauseI"           : "fpu_cause_I",
+    "FpuCauseU"           : "fpu_cause_U",
+    "FpuCauseO"           : "fpu_cause_O",
+    "FpuCauseZ"           : "fpu_cause_Z",
+    "FpuCauseV"           : "fpu_cause_V",
+    "FpuCauseE"           : "fpu_cause_E",
+    "FpuEnableI"          : "fpu_enable_I",
+    "FpuEnableU"          : "fpu_enable_U",
+    "FpuEnableO"          : "fpu_enable_O",
+    "FpuEnableZ"          : "fpu_enable_Z",
+    "FpuEnableV"          : "fpu_enable_V",
 }
-
-"""
-ASID
-VPN
-PPN
-SZ
-SZ0
-SZ1
-SH
-PR
-WT
-C
-D
-V
-
-AddressUnavailable
-ALLOCO
-DataAccessMiss
-DirtyBit
-FpuIsDisabled
-IsDelaySlot
-MMU
-MMUCR
-OCBI
-OCBWB
-PREF
-PTEH
-PTEL
-ReadProhibited
-URC
-UTLB
-WriteProhibited
-"""
diff --git a/parser.py b/parser.py
index 9b1f366..7ad1edf 100644
--- a/parser.py
+++ b/parser.py
@@ -337,10 +337,23 @@ class Parser:
             )
         return expr
 
+    def assignment_list(self):
+        expr = self.unary_expression()
+        while True:
+            if self.match_punctuator(","):
+                right = self.unary_expression()
+                expr = Tree(
+                    operation="assignment_list",
+                    children=[expr, right]
+                )
+            else:
+                break
+        return expr
+
     def assignment_expression(self):
         backtrack = self.pos
         try:
-            left = self.unary_expression()
+            left = self.assignment_list()
         except AssertionError:
             self.pos = backtrack
             return self.logical_or_expression()
diff --git a/syntax.txt b/syntax.txt
index b9acf2b..8c79370 100644
--- a/syntax.txt
+++ b/syntax.txt
@@ -88,9 +88,13 @@ logical-OR-expression:
 	logical-XOR-expression
 	logical-OR-expression "OR" logical-XOR-expression
 
+assignment-list:
+	unary-expression
+	assignment-lhs "," unary-expression
+
 assignment-expression:
 	logical-OR-expression
-	unary-expression "←" assignment-expression
+	assignment-list "←" assignment-expression
 
 expression:
 	assignment-expression
diff --git a/test_parser.py b/test_parser.py
index 49db307..571ba65 100644
--- a/test_parser.py
+++ b/test_parser.py
@@ -1,6 +1,8 @@
+from pprint import pprint
+
 from lexer import Lexer
 from parser import Parser
-from generator import generate
+from ast_to_c_source import generate
 
 sources = [
     "op1 ← FloatValue64(DR2n);",
@@ -28,12 +30,13 @@ def all_tokens(lexer):
             break
         yield token
 
-for source in sources:
+def dump(source):
     lexer = Lexer(source)
     tokens = list(all_tokens(lexer))
     parser = Parser(tokens)
-    from pprint import pprint
     root = parser.statement()
-    s = "".join(generate(root))
-    print(s, end='')
-    print()
+    pprint(root)
+
+source = "c ← foobar(b, c, d);"
+
+dump(source);