Zack Buhman
e179ce3bf6
It appears much more convenient to access oreg in particular via an "index variable". To avoid repeated boilerplate, add the accessor here as a c++ operator overload. This makes smpc.h c++-only. With defines guarding the overload, it could be reduced to C again, though I decided I don't want to bother with testing that.
301 lines
6.2 KiB
C
301 lines
6.2 KiB
C
#include "type.h"
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struct ireg {
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reg8 _res0;
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reg8 IREG0;
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reg8 _res1;
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reg8 IREG1;
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reg8 _res2;
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reg8 IREG2;
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reg8 _res3;
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reg8 IREG3;
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reg8 _res4;
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reg8 IREG4;
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reg8 _res5;
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reg8 IREG5;
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reg8 _res6;
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reg8 IREG6;
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inline constexpr reg8 & operator[](uint32_t i)
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{
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switch (i) {
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default:
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case 0: return IREG0;
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case 1: return IREG1;
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case 2: return IREG2;
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case 3: return IREG3;
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case 4: return IREG4;
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case 5: return IREG5;
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case 6: return IREG6;
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}
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};
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};
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static_assert((sizeof (struct ireg)) == 14);
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static_assert((offsetof (struct ireg, IREG0)) == 0x1);
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static_assert((offsetof (struct ireg, IREG1)) == 0x3);
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static_assert((offsetof (struct ireg, IREG6)) == 0xd);
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struct oreg {
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reg8 _res24;
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reg8 OREG0;
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reg8 _res25;
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reg8 OREG1;
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reg8 _res26;
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reg8 OREG2;
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reg8 _res27;
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reg8 OREG3;
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reg8 _res28;
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reg8 OREG4;
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reg8 _res29;
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reg8 OREG5;
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reg8 _res30;
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reg8 OREG6;
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reg8 _res31;
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reg8 OREG7;
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reg8 _res32;
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reg8 OREG8;
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reg8 _res33;
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reg8 OREG9;
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reg8 _res34;
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reg8 OREG10;
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reg8 _res35;
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reg8 OREG11;
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reg8 _res36;
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reg8 OREG12;
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reg8 _res37;
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reg8 OREG13;
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reg8 _res38;
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reg8 OREG14;
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reg8 _res39;
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reg8 OREG15;
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reg8 _res40;
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reg8 OREG16;
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reg8 _res41;
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reg8 OREG17;
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reg8 _res42;
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reg8 OREG18;
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reg8 _res43;
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reg8 OREG19;
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reg8 _res44;
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reg8 OREG20;
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reg8 _res45;
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reg8 OREG21;
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reg8 _res46;
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reg8 OREG22;
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reg8 _res47;
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reg8 OREG23;
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reg8 _res48;
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reg8 OREG24;
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reg8 _res49;
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reg8 OREG25;
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reg8 _res50;
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reg8 OREG26;
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reg8 _res51;
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reg8 OREG27;
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reg8 _res52;
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reg8 OREG28;
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reg8 _res53;
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reg8 OREG29;
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reg8 _res54;
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reg8 OREG30;
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reg8 _res55;
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reg8 OREG31;
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inline constexpr reg8 const& operator[](uint32_t i) const
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{
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switch (i) {
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default:
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case 0: return OREG0;
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case 1: return OREG1;
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case 2: return OREG2;
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case 3: return OREG3;
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case 4: return OREG4;
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case 5: return OREG5;
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case 6: return OREG6;
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case 7: return OREG7;
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case 8: return OREG8;
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case 9: return OREG9;
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case 10: return OREG10;
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case 11: return OREG11;
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case 12: return OREG12;
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case 13: return OREG13;
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case 14: return OREG14;
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case 15: return OREG15;
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case 16: return OREG16;
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case 17: return OREG17;
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case 18: return OREG18;
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case 19: return OREG19;
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case 20: return OREG20;
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case 21: return OREG21;
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case 22: return OREG22;
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case 23: return OREG23;
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case 24: return OREG24;
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case 25: return OREG25;
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case 26: return OREG26;
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case 27: return OREG27;
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case 28: return OREG28;
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case 29: return OREG29;
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case 30: return OREG30;
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case 31: return OREG31;
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}
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};
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};
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static_assert((sizeof (struct oreg)) == 64);
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static_assert((offsetof (struct oreg, OREG0)) == 0x1);
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static_assert((offsetof (struct oreg, OREG1)) == 0x3);
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struct smpc_reg {
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struct ireg ireg;
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reg8 _res7;
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reg8 _res8;
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reg8 _res9;
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reg8 _res10;
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reg8 _res11;
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reg8 _res12;
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reg8 _res13;
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reg8 _res14;
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reg8 _res15;
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reg8 _res16;
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reg8 _res17;
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reg8 _res18;
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reg8 _res19;
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reg8 _res20;
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reg8 _res21;
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reg8 _res22;
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reg8 _res23;
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reg8 COMREG;
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struct oreg oreg;
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reg8 _res56;
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reg8 SR;
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reg8 _res57;
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reg8 SF;
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reg8 _res58;
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reg8 _res59;
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reg8 _res60;
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reg8 _res61;
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reg8 _res62;
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reg8 _res63;
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reg8 _res64;
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reg8 _res65;
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reg8 _res66;
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reg8 _res67;
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reg8 _res68;
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reg8 _res69;
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reg8 _res70;
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reg8 _res71;
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reg8 _res72;
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reg8 _res73;
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reg8 _res74;
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reg8 PDR1;
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reg8 _res75;
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reg8 PDR2;
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reg8 _res76;
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reg8 DDR1;
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reg8 _res77;
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reg8 DDR2;
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reg8 _res78;
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reg8 IOSEL;
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reg8 _res79;
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reg8 EXLE;
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};
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static_assert((sizeof (smpc_reg)) == 0x80);
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static_assert((offsetof (struct smpc_reg, oreg.OREG0)) == 0x21);
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static_assert((offsetof (struct smpc_reg, oreg.OREG1)) == 0x23);
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static_assert((offsetof (struct smpc_reg, oreg.OREG31)) == 0x5f);
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static_assert((offsetof (struct smpc_reg, SF)) == 0x63);
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struct smpc {
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smpc_reg reg;
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};
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extern struct smpc smpc __asm("smpc");
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/* bits */
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enum comreg_bit {
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COMREG__MSHON = 0x00,
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COMREG__SSHON = 0x02,
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COMREG__SSHOFF = 0x03,
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COMREG__SNDON = 0x06,
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COMREG__SNDOFF = 0x07,
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COMREG__CDON = 0x08,
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COMREG__CDOFF = 0x09,
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COMREG__SYSRES = 0x0D,
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COMREG__CKCHG352 = 0x0E,
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COMREG__CKCHG320 = 0x0F,
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COMREG__INTBACK = 0x10,
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COMREG__SETTIME = 0x16,
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COMREG__SETSMEM = 0x17,
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COMREG__NMIREQ = 0x18,
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COMREG__RESENAB = 0x19,
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COMREG__RESDISA = 0x1A,
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};
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enum intback_ireg_bit {
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INTBACK__IREG0__CONTINUE = (1 << 7),
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INTBACK__IREG0__BREAK = (1 << 6),
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INTBACK__IREG0__STATUS_DISABLE = (0x00),
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INTBACK__IREG0__STATUS_ENABLE = (0x01),
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INTBACK__IREG1__PORT2_15BYTE = (0b00 << 6),
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INTBACK__IREG1__PORT2_256BYTE = (0b01 << 6),
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INTBACK__IREG1__PORT2_0BYTE = (0b11 << 6),
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INTBACK__IREG1__PORT1_15BYTE = (0b00 << 4),
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INTBACK__IREG1__PORT1_256BYTE = (0b01 << 4),
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INTBACK__IREG1__PORT1_0BYTE = (0b11 << 4),
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INTBACK__IREG1__PERIPHERAL_DATA_ENABLE = (1 << 3),
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INTBACK__IREG1__NOT_OPTIMIZED = (1 << 1),
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INTBACK__IREG2__MAGIC = (0xF0),
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};
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enum sr_bit {
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SR__PDL = (1 << 6),
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SR__NPE = (1 << 5),
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SR__RESB = (1 << 4),
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SR__P2MD1 = (1 << 3),
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SR__P2MD0 = (1 << 2),
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SR__P1MD1 = (1 << 1),
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SR__P1MD0 = (1 << 0),
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#define SR__P2MD__15BYTE(sr) (((sr & 0b00001100)) == (0b00 << 2))
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#define SR__P2MD__255BYTE(sr) (((sr & 0b00001100)) == (0b01 << 2))
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#define SR__P2MD__0BYTE(sr) (((sr & 0b00001100)) == (0b11 << 2))
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#define SR__P1MD__15BYTE(sr) (((sr & 0b00000011)) == (0b00 << 0))
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#define SR__P1MD__255BYTE(sr) (((sr & 0b00000011)) == (0b01 << 0))
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#define SR__P1MD__0BYTE(sr) (((sr & 0b00000011)) == (0b11 << 0))
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};
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//enum port_status {
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#define PORT_STATUS__CONNECTORS(oreg) ((oreg >> 0) & 0b1111)
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#define PORT_STATUS__MULTITAP_ID(oreg) ((oreg >> 4) & 0b1111)
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//}
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//enum peripheral_id {
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#define PERIPHERAL_ID__DATA_SIZE(oreg) ((oreg >> 0) & 0b1111)
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#define PERIPHERAL_ID__IS_DIGITAL_PAD(oreg) (((oreg >> 4) & 0b1111) == 0b0000)
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//}
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enum digital_bit {
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DIGITAL__1__RIGHT = (1 << 7),
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DIGITAL__1__LEFT = (1 << 6),
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DIGITAL__1__DOWN = (1 << 5),
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DIGITAL__1__UP = (1 << 4),
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DIGITAL__1__START = (1 << 3),
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DIGITAL__1__A = (1 << 2),
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DIGITAL__1__C = (1 << 1),
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DIGITAL__1__B = (1 << 0),
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DIGITAL__2__R = (1 << 7),
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DIGITAL__2__X = (1 << 6),
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DIGITAL__2__Y = (1 << 5),
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DIGITAL__2__Z = (1 << 4),
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DIGITAL__2__L = (1 << 3),
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};
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