92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
//
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// scsp
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//
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// The SCSP will initialize the internal registers, etc. for about 30µ sec
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// after the reset has been released. For this reason, access is not allowed
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// during the 30µ sec.
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// Before downloading anything, make sure to set MEM4MB bit to 1 and DAC18B
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// bit to 0 within the sound CPU (address) 10400H address.
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smpc.reg.COMREG = COMREG__SNDON;
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while (smpc.reg.OREG31 != 0b00000110) {}
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for (long i = 0; i < 807; i++) { asm volatile ("nop"); } // wait for (way) more than 30µs
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scsp.reg.common[0] = SCSP__0__MEM4MB | SCSP__0__DAC18B;
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u16 * m68k_main_start = (u16 *)&_binary_m68k_main_bin_start;
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u32 m68k_main_size = (u32)&_binary_m68k_main_bin_size;
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copy_16(m68k_main_start, &scsp.ram.u16[0], m68k_main_size);
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smpc.reg.COMREG = COMREG__SNDOFF;
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while (smpc.reg.OREG31 != 0b00000111) {}
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for (long i = 0; i < 807; i++) { asm volatile ("nop"); } // wait for (way) more than 30µs
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smpc.reg.COMREG = COMREG__SNDON;
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while (smpc.reg.OREG31 != 0b00000110) {}
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for (long i = 0; i < 807; i++) { asm volatile ("nop"); } // wait for (way) more than 30µs
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scsp.reg.common[0] = SCSP__0__MEM4MB | SCSP__0__DAC18B;
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///
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static signed int left_phase;
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static void fill_data(int16_t * output, int len)
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{
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for (int i = 0; i < len; i++) {
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*output++ = (signed short)left_phase;
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left_phase += 327 / 2;
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if (left_phase >= 32767) left_phase = -32768;
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}
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}
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#include "scsp.h"
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void main_sound(void)
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{
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while ((smpc.reg.SF & 0x01) == 1);
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smpc.reg.SF = 1;
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smpc.reg.COMREG = COMREG__SNDON;
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while ((smpc.reg.SF & 0x01) == 1);
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while (smpc.reg.OREG31 != 0b00000110) {}
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for (long i = 0; i < 807; i++) { asm volatile ("nop"); } // wait for (way) more than 30µs
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scsp.reg.common[0] = SCSP__0__MEM4MB | SCSP__0__DAC18B | 15;
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left_phase = 0;
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fill_data((int16_t*)&scsp.ram.u16[0], 44100);
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scsp_slot& slot = scsp.reg.slot[0];
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while (1) {
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left_phase = 0;
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fill_data((int16_t*)&scsp.ram.u16[0], 44100);
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slot.field[0] = (1 << 11) | (1 << 5); // kx
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slot.field[1] = 0; // start_addr
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slot.field[2] = 0; // loop start address
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slot.field[3] = 44100; // loop end address
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slot.field[4] = 31; // d2r d1r ar
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//slot.field[5] = (1 << 14) | (0xf << 10) | 0; // krs dl rr (key_decay_release)
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slot.field[5] = 31; // krs dl rr (key_decay_release)
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slot.field[6] = 1 << 3; // tl (attenuation)
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slot.field[7] = 0; // mdl mdxsl mdysl (fm_data)
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slot.field[8] = 0; // oct fns (ofc_fns)
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slot.field[9] = 0; // lfof plfows (lfo_data)
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slot.field[10] = 0; // isel imxl (input_sel)
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slot.field[11] = (7 << 13); // disdl dipan efpan (pan_send)
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slot.field[0] |= (1 << 12);
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for (int32_t i = 0; i < 800000; i++) { asm volatile ("nop"); }
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slot.field[0] |= (1 << 12);
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slot.field[0] = 0;
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}
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}
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