Zack Buhman
6640c37a1d
- add code loading for m68k
- incomplete scsp experiments
- the register definitions should be fairly complete,
though I did not produce actual sound yet
- fix type.h definitions
- incomplete cdblock register definitions
117 lines
3.2 KiB
C
117 lines
3.2 KiB
C
void v_blank_in_int(void) __attribute__ ((interrupt_handler));
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void v_blank_in_int(void)
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{
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scu.reg.IST &= ~(IST__V_BLANK_IN);
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// reset FRC to zero
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sh2.reg.FRC.H = 0;
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sh2.reg.FRC.L = 0;
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// enable output compare interrupt
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sh2.reg.TIER = TIER__OCIAE;
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}
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void oci_int(void) __attribute__ ((interrupt_handler));
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void oci_int(void)
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{
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// clear OCFA
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sh2.reg.FTCSR &= ~(FTCSR__OCFA);
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while (smpc.reg.SF != 0) {}
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smpc.reg.SF = 0;
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smpc.reg.IREG0 = INTBACK__IREG0__STATUS_DISABLE;
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smpc.reg.IREG1 = ( INTBACK__IREG1__PERIPHERAL_DATA_ENABLE
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| INTBACK__IREG1__PORT2_0BYTE
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| INTBACK__IREG1__PORT1_15BYTE
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);
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smpc.reg.IREG2 = INTBACK__IREG2__MAGIC;
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smpc.reg.COMREG = COMREG__INTBACK;
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// disable output compare interrupt (to be re-enabled on the next v_blank_in)
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sh2.reg.TIER = 0;
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}
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void smpc_int(void) __attribute__ ((interrupt_handler));
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void smpc_int(void)
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{
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scu.reg.IST &= ~(IST__SMPC);
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if (smpc.reg.SR & SR__PDL) {
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// to get all controller data, one should check SR__NPE and send CONTINUE
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// requests as needed
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// assuming SR__PDL is set and SR__P1MD is not 0-byte-mode:
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// smpc.reg.OREG0 (port 1 status)
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// smpc.reg.OREG1 (peripheral 1 data[0] {type,size})
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// smpc.reg.OREG2 (peripheral 1 data[1])
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if ((smpc.reg.OREG2 & DIGITAL__1__C) == 0) {
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// if C is pressed, swap the color palette
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vdp2.cram.u16[1] = (0x31 << 10); // blue
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vdp2.cram.u16[2] = (0x31 << 5); // green
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} else {
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// if C is not pressed, restore the original palette
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vdp2.cram.u16[1] = (0x31 << 5); // green
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vdp2.cram.u16[2] = (0x31 << 10); // blue
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}
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}
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smpc.reg.IREG0 = INTBACK__IREG0__BREAK;
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}
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//
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// scu1:
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//
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// If timer0 is counting at roughly 15.73426 kHz (1/63.5556 µs), we can count
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// to 300µs at roughly T0C = 5 (~317.778 µs). H-Blank-IN subtracts about
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// 10.9µs which is still (~306 µs) more than 300µs.
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vec[SCU_VEC__SMPC] = (u32)(&smpc_int);
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vec[SCU_VEC__V_BLANK_IN] = (u32)(&v_blank_in_int);
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//scu.reg.T0C = 5;
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//scu.reg.T1MD = T1MD__TENB;
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// From the SMPC manual:
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// The SMPC uses the V-BLANK-IN interrupt to execute internal tasks. At this
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// time, issuing commands for 300 µs from V-BLANK-IN is prohibited.
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// CLKCHG320 (power-on default) NTSC, the FRC's internal clock is 26.8741 MHz.
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// The possible periods are then:
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//
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// - 0.29768 µs (/8)
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// - 1.19074 µs (/32)
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// - 4.76295 µs (/128)
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//
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// (1/(26.8741 MHz)) * 128 * 63 = 300.066 µs
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// FRC, OCRA, OCRB, and FCIR are 16-bit registers, but the FRT bus is an 8-bit
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// bus.
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// TCR set CKS to /128
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// TOCR set OCRS to OCRA
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// TIER set OCIAE
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// FTCSR set CCLRA (clear FRC on compare match A)
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// VCRC set FOCV
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// OCRA set 63
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// FRC set 0
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vec[0x60] = (u32)&oci_int;
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sh2.reg.VCRC = VCRC__FOCV(0x60);
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sh2.reg.TCR = TCR__CKS__INTERNAL_DIV128;
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sh2.reg.TOCR = TOCR__OCRS__OCRA;
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sh2.reg.FTCSR = FTCSR__CCLRA;
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sh2.reg.OCRAB.H = 0; // Even though Kronos doesn't emulate this, SH7095 says
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// we are required to write the upper bit prior to
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// writing the lower byte
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sh2.reg.OCRAB.L = 63;
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// reset/enable interrupts
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scu.reg.IST = 0;
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scu.reg.IMS = ~(IMS__SMPC | IMS__V_BLANK_IN);
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