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10 Commits

Author SHA1 Message Date
5146395169 vdp2: add color calculation bits 2024-03-24 14:41:43 +08:00
2cc1a27427 MIT license 2023-09-29 17:53:13 +00:00
582261eef5 scu: add DSP and DMA bits 2023-09-09 13:28:25 +00:00
3e162c8d14 vdp1: add COLOR_BANK macros for the COLR register
This also adds the directly related SPCTL macros for vdp2.
2023-08-04 00:51:58 +00:00
fcf31ce095 vdp2: fix macro typos
Add 32-bit unions for the map base offset registers.
2023-07-29 06:14:58 +00:00
06bc9b49bf vdp2: improve bit definitions
This fixes a typo in the MPCDN* bits.

Also adds window and background priority bits.
2023-07-26 01:48:13 +00:00
f6c9380ece common: add header dependencies 2023-07-23 22:30:47 +00:00
0c7c2e663a common.mk: add binary header rule 2023-07-23 17:58:30 +00:00
5f515a20d4 move most sys_ files to ip directory 2023-07-23 06:23:05 +00:00
1a72e2068e vdp2: improve vram cycle pattern definition 2023-07-21 22:29:56 -07:00
20 changed files with 536 additions and 94 deletions

1
.gitignore vendored
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@ -6,3 +6,4 @@ segasmp/lib/sys_init.o
*.bin
*.gch
*.out
*.d

21
LICENSE Normal file
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@ -0,0 +1,21 @@
MIT License
Copyright (c) 2023 saturn contributors
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

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@ -1,6 +1,7 @@
LIB ?= .
OPT ?= -Og
DEBUG ?= -g -gdwarf-4
GENERATED ?=
AARCH = --isa=sh2 --big
AFLAGS = --fatal-warnings
@ -8,6 +9,7 @@ AFLAGS = --fatal-warnings
CARCH = -m2 -mb
CFLAGS += -falign-functions=4 -ffunction-sections -fdata-sections -fshort-enums -ffreestanding -nostdlib
CFLAGS += -Wall -Werror -Wfatal-errors -Wno-error=unused-variable
DEPFLAGS = -MMD -E
LDFLAGS = --gc-sections --print-gc-sections --no-warn-rwx-segment --print-memory-usage --entry=_start --orphan-handling=error
CXXFLAGS = -std=c++20 -fno-exceptions -fno-non-call-exceptions -fno-rtti -fno-threadsafe-statics
@ -28,19 +30,36 @@ define BUILD_BINARY_O
$< $@
endef
as_obj_binary = _binary_$(subst .,_,$(subst /,_,$(basename $(1))))
define BUILD_BINARY_H
@echo gen $@
@echo '#pragma once' > $@
@echo '#include <stdint.h>' >> $@
@echo 'extern uint32_t $(call as_obj_binary,$@)_start __asm("$(call as_obj_binary,$@)_start");' >> $@
@echo 'extern uint32_t $(call as_obj_binary,$@)_end __asm("$(call as_obj_binary,$@)_end");' >> $@
@echo 'extern uint32_t $(call as_obj_binary,$@)_size __asm("$(call as_obj_binary,$@)_size");' >> $@
endef
%.o: %.s
$(AS) $(AARCH) $(AFLAGS) $(DEBUG) $< -o $@
%.o: %.S
$(CC) $(CARCH) $(CFLAGS) $(OPT) $(DEBUG) -c $< -o $@
%.o: %.c
%.c.d: | $(GENERATED)
$(CC) $(CARCH) $(CFLAGS) $(OPT) $(DEBUG) $(DEPFLAGS) -c $(basename $@) -MF $@ -o /dev/null
%.o: %.c %.c.d
$(CC) $(CARCH) $(CFLAGS) $(OPT) $(DEBUG) -c $< -o $@
%.o: %.cpp
%.cpp.d: | $(GENERATED)
$(CXX) $(CARCH) $(CFLAGS) $(CXXFLAGS) $(OPT) $(DEBUG) $(DEPFLAGS) -c $(basename $@) -MF $@ -o /dev/null
%.o: %.cpp %.cpp.d
$(CXX) $(CARCH) $(CFLAGS) $(CXXFLAGS) $(OPT) $(DEBUG) -c $< -o $@
%.elf:
%.elf: $(LIB)/start.o
$(LD) $(LDFLAGS) -T $(LIB)/sh2.lds $^ -o $@
%.bin: %.elf
@ -52,20 +71,20 @@ endef
--rename-section .data=.rodata,alloc,load,readonly,data,contents \
$< $@
SYS_IP_OBJ += $(LIB)/sys_id.o
SYS_IP_OBJ += $(LIB)/sys_sec.o
SYS_IP_OBJ += $(LIB)/area/sys_area.o
SYS_IP_OBJ += $(LIB)/area/sys_areb.o
SYS_IP_OBJ += $(LIB)/area/sys_aree.o
SYS_IP_OBJ += $(LIB)/area/sys_arej.o
SYS_IP_OBJ += $(LIB)/area/sys_arek.o
SYS_IP_OBJ += $(LIB)/area/sys_arel.o
SYS_IP_OBJ += $(LIB)/area/sys_aret.o
SYS_IP_OBJ += $(LIB)/area/sys_areu.o
SYS_IP_OBJ += $(LIB)/sys_init.o
SYS_IP_OBJ += $(LIB)/smpsys.o
SYS_IP_OBJ += $(LIB)/ip/sys_id.o
SYS_IP_OBJ += $(LIB)/ip/segasmp/sys_sec.o
SYS_IP_OBJ += $(LIB)/ip/sys_area.o
SYS_IP_OBJ += $(LIB)/ip/sys_areb.o
SYS_IP_OBJ += $(LIB)/ip/sys_aree.o
SYS_IP_OBJ += $(LIB)/ip/sys_arej.o
SYS_IP_OBJ += $(LIB)/ip/sys_arek.o
SYS_IP_OBJ += $(LIB)/ip/sys_arel.o
SYS_IP_OBJ += $(LIB)/ip/sys_aret.o
SYS_IP_OBJ += $(LIB)/ip/sys_areu.o
SYS_IP_OBJ += $(LIB)/ip/sys_init.o
SYS_IP_OBJ += $(LIB)/ip/smpsys.o
$(LIB)/sys_%.o: $(LIB)/segasmp/lib/sys_%.o
$(LIB)/ip/segasmp/sys_%.o: $(LIB)/segasmp/lib/sys_%.o
$(OBJCOPY) -I coff-sh -O elf32-sh -g \
--rename-section .text=.text.$* \
$< $@
@ -116,9 +135,15 @@ sys_ip.elf: $(SYS_IP_OBJ)
@echo " INDEX 01 00:00:00" >> $@
clean:
rm -f *.iso *.o *.bin *.elf *.cue
rm -f *.iso *.o *.d *.bin *.elf *.cue *.gch
.SUFFIXES:
.INTERMEDIATE:
.SECONDARY:
.PHONY: all clean
%: RCS/%,v
%: RCS/%
%: %,v
%: s.%
%: SCCS/s.%

0
ip/segasmp/.empty Normal file
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@ -27,6 +27,17 @@ define BUILD_BINARY_O
$< $@
endef
as_obj_binary = _binary_$(subst /,_,$(subst .,_,$(basename $(1))))
define BUILD_BINARY_H
@echo $@
@echo '#pragma once' > $@
@echo '#include <stdint.h>' >> $@
@echo 'extern uint32_t $(call as_obj_binary,$@)_start __asm("$(call as_obj_binary,$@)_start");' >> $@
@echo 'extern uint32_t $(call as_obj_binary,$@)_end __asm("$(call as_obj_binary,$@)_end");' >> $@
@echo 'extern uint32_t $(call as_obj_binary,$@)_size __asm("$(call as_obj_binary,$@)_size");' >> $@
endef
all: main.bin
%.o: %.s

142
scu.h
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@ -70,6 +70,148 @@ extern struct scu scu __asm("scu");
/* bits */
#define D0R__READ_ADDRESS(n) ((n) & 0x3ffffff)
#define D0W__WRITE_ADDRESS(n) ((n) & 0x3ffffff)
#define D0C__BYTE_COUNT(n) ((n) & 0x7ffff)
enum d0ad_bits {
D0AD__D0RA__0BYTES = (0 << 8),
D0AD__D0RA__4BYTES = (1 << 8),
D0AD__D0WA__0BYTES = (0b000 << 0),
D0AD__D0WA__2BYTES = (0b001 << 0),
D0AD__D0WA__4BYTES = (0b010 << 0),
D0AD__D0WA__8BYTES = (0b011 << 0),
D0AD__D0WA__16BYTES = (0b100 << 0),
D0AD__D0WA__32BYTES = (0b101 << 0),
D0AD__D0WA__64BYTES = (0b110 << 0),
D0AD__D0WA__128BYTES = (0b111 << 0),
};
enum d0en_bits {
D0EN__D0EN = (1 << 8),
D0EN__D0GO = (1 << 0),
};
enum d0md_bits {
D0MD__D0MOD = (1 << 24),
D0MD__D0RUP = (1 << 16),
D0MD__D0WUP = (1 << 8),
D0MD__D0FT__V_BLANK_IN = (0b000 << 0),
D0MD__D0FT__V_BLANK_OUT = (0b001 << 0),
D0MD__D0FT__H_BLANK_IN = (0b010 << 0),
D0MD__D0FT__TIMER_0 = (0b011 << 0),
D0MD__D0FT__TIMER_1 = (0b100 << 0),
D0MD__D0FT__SOUND_REQ = (0b101 << 0),
D0MD__D0FT__SPRITE_DRAW = (0b110 << 0),
D0MD__D0FT__FACTOR_BIT = (0b111 << 0),
};
#define D1R__READ_ADDRESS(n) ((n) & 0x3ffffff)
#define D1W__WRITE_ADDRESS(n) ((n) & 0x3ffffff)
#define D1C__BYTE_COUNT(n) ((n) & 0x7ffff)
enum d1ad_bits {
D1AD__D1RA__0BYTES = (0 << 8),
D1AD__D1RA__4BYTES = (1 << 8),
D1AD__D1WA__0BYTES = (0b000 << 0),
D1AD__D1WA__2BYTES = (0b001 << 0),
D1AD__D1WA__4BYTES = (0b010 << 0),
D1AD__D1WA__8BYTES = (0b011 << 0),
D1AD__D1WA__16BYTES = (0b100 << 0),
D1AD__D1WA__32BYTES = (0b101 << 0),
D1AD__D1WA__64BYTES = (0b110 << 0),
D1AD__D1WA__128BYTES = (0b111 << 0),
};
enum d1en_bits {
D1EN__D1EN = (1 << 8),
D1EN__D1GO = (1 << 0),
};
enum d1md_bits {
D1MD__D1MOD = (1 << 24),
D1MD__D1RUP = (1 << 16),
D1MD__D1WUP = (1 << 8),
D1MD__D1FT__V_BLANK_IN = (0b000 << 0),
D1MD__D1FT__V_BLANK_OUT = (0b001 << 0),
D1MD__D1FT__H_BLANK_IN = (0b010 << 0),
D1MD__D1FT__TIMER_0 = (0b011 << 0),
D1MD__D1FT__TIMER_1 = (0b100 << 0),
D1MD__D1FT__SOUND_REQ = (0b101 << 0),
D1MD__D1FT__SPRITE_DRAW = (0b110 << 0),
D1MD__D1FT__FACTOR_BIT = (0b111 << 0),
};
#define D2R__READ_ADDRESS(n) ((n) & 0x3ffffff)
#define D2W__WRITE_ADDRESS(n) ((n) & 0x3ffffff)
#define D2C__BYTE_COUNT(n) ((n) & 0x7ffff)
enum d2ad_bits {
D2AD__D2RA__0BYTES = (0 << 8),
D2AD__D2RA__4BYTES = (1 << 8),
D2AD__D2WA__0BYTES = (0b000 << 0),
D2AD__D2WA__2BYTES = (0b001 << 0),
D2AD__D2WA__4BYTES = (0b010 << 0),
D2AD__D2WA__8BYTES = (0b011 << 0),
D2AD__D2WA__16BYTES = (0b100 << 0),
D2AD__D2WA__32BYTES = (0b101 << 0),
D2AD__D2WA__64BYTES = (0b110 << 0),
D2AD__D2WA__128BYTES = (0b111 << 0),
};
enum d2en_bits {
D2EN__D2EN = (1 << 8),
D2EN__D2GO = (1 << 0),
};
enum d2md_bits {
D2MD__D2MOD = (1 << 24),
D2MD__D2RUP = (1 << 16),
D2MD__D2WUP = (1 << 8),
D2MD__D2FT__V_BLANK_IN = (0b000 << 0),
D2MD__D2FT__V_BLANK_OUT = (0b001 << 0),
D2MD__D2FT__H_BLANK_IN = (0b010 << 0),
D2MD__D2FT__TIMER_0 = (0b011 << 0),
D2MD__D2FT__TIMER_1 = (0b100 << 0),
D2MD__D2FT__SOUND_REQ = (0b101 << 0),
D2MD__D2FT__SPRITE_DRAW = (0b110 << 0),
D2MD__D2FT__FACTOR_BIT = (0b111 << 0),
};
enum dstp_bits {
DSTP__FORCE_STOP = (1 << 0),
};
enum dsta_bits {
DSTA__DACSD = (1 << 22),
DSTA__DACSB = (1 << 21),
DSTA__DACSA = (1 << 20),
DSTA__D1BK = (1 << 17),
DSTA__D0BK = (1 << 16),
DSTA__D2WT = (1 << 13),
DSTA__D2MV = (1 << 12),
DSTA__D1WT = (1 << 9),
DSTA__D1MV = (1 << 8),
DSTA__D0WT = (1 << 5),
DSTA__D0MV = (1 << 4),
DSTA__DDWT = (1 << 1),
DSTA__DDMV = (1 << 0),
};
enum ppaf_bits {
PPAF__PR = (1 << 26),
PPAF__EP = (1 << 25),
PPAF__T0 = (1 << 23),
PPAF__S = (1 << 22),
PPAF__Z = (1 << 21),
PPAF__C = (1 << 20),
PPAF__V = (1 << 19),
PPAF__E = (1 << 18),
PPAF__ES = (1 << 17),
PPAF__EX = (1 << 16),
PPAF__LE = (1 << 15),
#define PPAF__PRG_ADDRESS(n) (((n) & 0xff) << 0)
};
enum pda_bits {
PDA__RA__RAM0 = (0b00 << 6),
PDA__RA__RAM1 = (0b01 << 6),
PDA__RA__RAM2 = (0b10 << 6),
PDA__RA__RAM3 = (0b11 << 6),
#define PDA__RAM_ADDRESS(n) (((n) & 0x3f) << 0)
};
enum ims_bits {
IMS__A_BUS = (1 << 15),
IMS__DRAW_END = (1 << 13),

26
smpc.h
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@ -103,19 +103,19 @@ enum comreg_bit {
};
enum oreg_bit {
OREG31__MSHON = 0b0000'0000,
OREG31__SSHON = 0b0000'0010,
OREG31__SSHOFF = 0b0000'0011,
OREG31__SNDON = 0b0000'0110,
OREG31__SNDOFF = 0b0000'0111,
OREG31__CDON = 0b0000'1000,
OREG31__CDOFF = 0b0000'1001,
OREG31__SYSRES = 0b0000'1101,
OREG31__CKCHG352 = 0b0000'1110,
OREG31__CKCHG320 = 0b0000'1111,
OREG31__NMIREQ = 0b0001'1000,
OREG31__RESENAB = 0b0001'1001,
OREG31__RESDISA = 0b0001'1010,
OREG31__MSHON = 0b00000000,
OREG31__SSHON = 0b00000010,
OREG31__SSHOFF = 0b00000011,
OREG31__SNDON = 0b00000110,
OREG31__SNDOFF = 0b00000111,
OREG31__CDON = 0b00001000,
OREG31__CDOFF = 0b00001001,
OREG31__SYSRES = 0b00001101,
OREG31__CKCHG352 = 0b00001110,
OREG31__CKCHG320 = 0b00001111,
OREG31__NMIREQ = 0b00011000,
OREG31__RESENAB = 0b00011001,
OREG31__RESDISA = 0b00011010,
};
enum intback_ireg_bit {

16
vdp1.h
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@ -67,6 +67,7 @@ enum ctrl_bit {
CTRL__ZP__LOWER_CENTER = (0b1110 << 8),
CTRL__ZP__LOWER_RIGHT = (0b1111 << 8),
CTRL__DIR__NOT_INVERTED = (0b00 << 4),
CTRL__DIR__INVERTED_HORIZONTALLY = (0b01 << 4),
CTRL__DIR__INVERTED_VERTICALLY = (0b10 << 4),
@ -101,9 +102,22 @@ enum pmod_bit {
#define PMOD__COLOR_CALCULATION ( << 0)
};
// see "Pixel Data in Frame Buffer" in VDP1 manual
// see "Figure 9.1" in VDP2 manual
// - these two figures refer to the same bits (VDP1 framebuffer data)
// see "Scroll Dot Pixels" in the VDP2 manual
// - "Dot Color" (DC0, DC1, ...) is described in the "Scroll Dot
// Pixels" section.
enum colr_bit {
COLR__RGB = (1 << 15)
#define COLR__ADDRESS(n) ((n) >> 3)
#define COLR__LOOKUP_TABLE__ADDRESS(n) ((n) >> 3)
#define COLR__COLOR_BANK__4BPP__PALETTE(n) (((n) & 0x7f) << 4)
#define COLR__COLOR_BANK__TYPE0__PR(n) (((n) & 0b11) << 14)
#define COLR__COLOR_BANK__TYPE0__CC(n) (((n) & 0b111) << 11)
#define COLR__COLOR_BANK__TYPE1__PR(n) (((n) & 0b111) << 13)
#define COLR__COLOR_BANK__TYPE1__CC(n) (((n) & 0b11) << 11)
};
//enum srca_bit {

322
vdp2.h
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@ -33,14 +33,34 @@ typedef struct vdp2_reg {
reg16 VCNT; /* V-COUNTER */
reg16 _res0;
reg16 RAMCTL; /* RAM CONTROL */
union {
struct {
reg16 CYCA0L; /* VRAM CYCLE PATTERN (BANK A0) */
reg16 CYCA0U; /* VRAM CYCLE PATTERN (BANK A0) */
};
reg32 CYCA0;
};
union {
struct {
reg16 CYCA1L; /* VRAM CYCLE PATTERN (BANK A1) */
reg16 CYCA1U; /* VRAM CYCLE PATTERN (BANK A1) */
};
reg32 CYCA1;
};
union {
struct {
reg16 CYCB0L; /* VRAM CYCLE PATTERN (BANK A0) */
reg16 CYCB0U; /* VRAM CYCLE PATTERN (BANK A0) */
};
reg32 CYCB0;
};
union {
struct {
reg16 CYCB1L; /* VRAM CYCLE PATTERN (BANK B1) */
reg16 CYCB1U; /* VRAM CYCLE PATTERN (BANK B1) */
};
reg32 CYCB1;
};
reg16 BGON; /* SCREEN DISPLAY ENABLE */
reg16 MZCTL; /* MOSAIC CONTROL */
reg16 SFSEL; /* SPECIAL FUNCTION CODE SELECT */
@ -57,14 +77,34 @@ typedef struct vdp2_reg {
reg16 PLSZ; /* PLANE SIZE */
reg16 MPOFN; /* MAP OFFSET (NBG0~NBG3) */
reg16 MPOFR; /* MAP OFFSET (ROTATION PARAMETER A,B) */
union {
struct {
reg16 MPABN0; /* MAP (NBG0, PLANE A,B) */
reg16 MPCDN0; /* MAP (NBG0, PLANE C,D) */
};
reg32 MPN0;
};
union {
struct {
reg16 MPABN1; /* MAP (NBG1, PLANE A,B) */
reg16 MPCDN1; /* MAP (NBG1, PLANE C,D) */
};
reg32 MPN1;
};
union {
struct {
reg16 MPABN2; /* MAP (NBG2, PLANE A,B) */
reg16 MPCDN2; /* MAP (NBG2, PLANE C,D) */
};
reg32 MPN2;
};
union {
struct {
reg16 MPABN3; /* MAP (NBG3, PLANE A,B) */
reg16 MPCDN3; /* MAP (NBG3, PLANE C,D) */
};
reg32 MPN3;
};
reg16 MPABRA; /* MAP (ROTATION PARAMETER A, PLANE A,B) */
reg16 MPCDRA; /* MAP (ROTATION PARAMETER A, PLANE C,D) */
reg16 MPEFRA; /* MAP (ROTATION PARAMETER A, PLANE E,F) */
@ -73,7 +113,7 @@ typedef struct vdp2_reg {
reg16 MPKLRA; /* MAP (ROTATION PARAMETER A, PLANE K,L) */
reg16 MPMNRA; /* MAP (ROTATION PARAMETER A, PLANE M,N) */
reg16 MPOPRA; /* MAP (ROTATION PARAMETER A, PLANE O,P) */
reg16 MPABRB; /* MAP (ROTATION PARAMETER B, PLANE B,B) */
reg16 MPABRB; /* MAP (ROTATION PARAMETER B, PLANE A,B) */
reg16 MPCDRB; /* MAP (ROTATION PARAMETER B, PLANE C,D) */
reg16 MPEFRB; /* MAP (ROTATION PARAMETER B, PLANE E,F) */
reg16 MPGHRB; /* MAP (ROTATION PARAMETER B, PLANE G,H) */
@ -417,14 +457,14 @@ enum plsz_bit {
PLSZ__N0PLSZ__2x2 = (0b11 << 0),
};
// enum mpofn_bit {
#define MPOFN__N3MP(n) ((n) << 12)
#define MPOFN__N2MP(n) ((n) << 8)
#define MPOFN__N1MP(n) ((n) << 4)
#define MPOFN__N0MP(n) ((n) << 0)
#define MPOFN__N3MP(n) (((n) & 0b111) << 12)
#define MPOFN__N2MP(n) (((n) & 0b111) << 8)
#define MPOFN__N1MP(n) (((n) & 0b111) << 4)
#define MPOFN__N0MP(n) (((n) & 0b111) << 0)
// };
// enum mpofr_bit {
#define MPOFR__RBMP(n) ((n) << 4)
#define MPOFR__RAMP(n) ((n) << 0)
#define MPOFR__RBMP(n) (((n) & 0b111) << 4)
#define MPOFR__RAMP(n) (((n) & 0b111) << 0)
// };
// 4.8 Maps § Map Selection Register
@ -434,33 +474,37 @@ enum plsz_bit {
#define MPABN0__N0MPA(n) ((n) << 0)
// };
// enum mpcdn0_bit {
#define MPABN0__N0MPD(n) ((n) << 8)
#define MPABN0__N0MPC(n) ((n) << 0)
#define MPCDN0__N0MPD(n) ((n) << 8)
#define MPCDN0__N0MPC(n) ((n) << 0)
// };
#define MPN0__N0MP(n) (((n) << 24) | ((n) << 16) | ((n) << 8) | ((n) << 0))
// enum mpabn1_bit {
#define MPABN1__N1MPB(n) ((n) << 8)
#define MPABN1__N1MPA(n) ((n) << 0)
// };
// enum mpcdn1_bit {
#define MPABN1__N1MPD(n) ((n) << 8)
#define MPABN1__N1MPC(n) ((n) << 0)
#define MPCDN1__N1MPD(n) ((n) << 8)
#define MPCDN1__N1MPC(n) ((n) << 0)
// };
#define MPN1__N1MP(n) (((n) << 24) | ((n) << 16) | ((n) << 8) | ((n) << 0))
// enum mpabn2_bit {
#define MPABN2__N2MPB(n) ((n) << 8)
#define MPABN2__N2MPA(n) ((n) << 0)
// };
// enum mpcdn2_bit {
#define MPABN2__N2MPD(n) ((n) << 8)
#define MPABN2__N2MPC(n) ((n) << 0)
#define MPCDN2__N2MPD(n) ((n) << 8)
#define MPCDN2__N2MPC(n) ((n) << 0)
// };
#define MPN2__N2MP(n) (((n) << 24) | ((n) << 16) | ((n) << 8) | ((n) << 0))
// enum mpabn3_bit {
#define MPABN3__N3MPB(n) ((n) << 8)
#define MPABN3__N3MPA(n) ((n) << 0)
// };
// enum mpcdn3_bit {
#define MPABN3__N3MPD(n) ((n) << 8)
#define MPABN3__N3MPC(n) ((n) << 0)
#define MPCDN3__N3MPD(n) ((n) << 8)
#define MPCDN3__N3MPC(n) ((n) << 0)
// };
#define MPN3__N3MP(n) (((n) << 24) | ((n) << 16) | ((n) << 8) | ((n) << 0))
// enum mpabra_bit {
// };
// enum mpcdra_bit {
@ -591,14 +635,74 @@ enum bktau_bit {
// };
// enum wpey1_bit {
// };
// enum wctla_bit {
// };
// enum wctlb_bit {
// };
// enum wctlc_bit {
// };
// enum wctld_bit {
// };
enum wctla_bit {
WCTLA__N1LOG__AND = (1 << 15), /* Overlay logic for NBG1 */
WCTLA__N1SWE = (1 << 13), /* Enable NBG1 on the Sprite window */
WCTLA__N1SWA__OUTSIDE = (1 << 12), /* Enable the outside of the Sprite window */
WCTLA__N1W1E = (1 << 11), /* Enable NBG1 on the W1 window */
WCTLA__N1W1A__OUTSIDE = (1 << 10), /* Enable the outside of the W1 window */
WCTLA__N1W0E = (1 << 9), /* Enable NBG1 on the W0 window */
WCTLA__N1W0A__OUTSIDE = (1 << 8), /* Enable the outside of the W0 window */
WCTLA__N0LOG__AND = (1 << 7), /* Overlay logic for NBG0 */
WCTLA__N0SWE = (1 << 5), /* Enable NBG0 on the Sprite window */
WCTLA__N0SWA__OUTSIDE = (1 << 4), /* Enable the outside of the Sprite window */
WCTLA__N0W1E = (1 << 3), /* Enable NBG0 on the W1 window */
WCTLA__N0W1A__OUTSIDE = (1 << 2), /* Enable the outside of the W1 window */
WCTLA__N0W0E = (1 << 1), /* Enable NBG0 on the W0 window */
WCTLA__N0W0A__OUTSIDE = (1 << 0), /* Enable the outside of the W0 window */
};
enum wctlb_bit {
WCTLB__N3LOG__AND = (1 << 15), /* Overlay logic for NBG3 */
WCTLB__N3SWE = (1 << 13), /* Enable NBG3 on the Sprite window */
WCTLB__N3SWA__OUTSIDE = (1 << 12), /* Enable the outside of the Sprite window */
WCTLB__N3W1E = (1 << 11), /* Enable NBG3 on the W1 window */
WCTLB__N3W1A__OUTSIDE = (1 << 10), /* Enable the outside of the W1 window */
WCTLB__N3W0E = (1 << 9), /* Enable NBG3 on the W0 window */
WCTLB__N3W0A__OUTSIDE = (1 << 8), /* Enable the outside of the W0 window */
WCTLB__N2LOG__AND = (1 << 7), /* Overlay logic for NBG2 */
WCTLB__N2SWE = (1 << 5), /* Enable NBG2 on the Sprite window */
WCTLB__N2SWA__OUTSIDE = (1 << 4), /* Enable the outside of the Sprite window */
WCTLB__N2W1E = (1 << 3), /* Enable NBG2 on the W1 window */
WCTLB__N2W1A__OUTSIDE = (1 << 2), /* Enable the outside of the W1 window */
WCTLB__N2W0E = (1 << 1), /* Enable NBG2 on the W0 window */
WCTLB__N2W0A__OUTSIDE = (1 << 0), /* Enable the outside of the W0 window */
};
enum wctlc_bit {
WCTLC__SPLOG__AND = (1 << 15), /* Overlay logic for Sprite */
WCTLC__SPSWE = (1 << 13), /* Enable Sprite on the Sprite window */
WCTLC__SPSWA__OUTSIDE = (1 << 12), /* Enable the outside of the Sprite window */
WCTLC__SPW1E = (1 << 11), /* Enable Sprite on the W1 window */
WCTLC__SPW1A__OUTSIDE = (1 << 10), /* Enable the outside of the W1 window */
WCTLC__SPW0E = (1 << 9), /* Enable Sprite on the W0 window */
WCTLC__SPW0A__OUTSIDE = (1 << 8), /* Enable the outside of the W0 window */
WCTLC__R0LOG__AND = (1 << 7), /* Overlay logic for RBG0 */
WCTLC__R0SWE = (1 << 5), /* Enable RBG0 on the Sprite window */
WCTLC__R0SWA__OUTSIDE = (1 << 4), /* Enable the outside of the Sprite window */
WCTLC__R0W1E = (1 << 3), /* Enable RBG0 on the W1 window */
WCTLC__R0W1A__OUTSIDE = (1 << 2), /* Enable the outside of the W1 window */
WCTLC__R0W0E = (1 << 1), /* Enable RBG0 on the W0 window */
WCTLC__R0W0A__OUTSIDE = (1 << 0), /* Enable the outside of the W0 window */
};
enum wctld_bit {
WCTLD__CCLOG__AND = (1 << 15), /* Overlay logic for Rotation Parameter */
WCTLD__CCSWE = (1 << 13), /* Enable Rotation Parameter on the Sprite window */
WCTLD__CCSWA__OUTSIDE = (1 << 12), /* Enable the outside of the Sprite window */
WCTLD__CCW1E = (1 << 11), /* Enable Rotation Parameter on the W1 window */
WCTLD__CCW1A__OUTSIDE = (1 << 10), /* Enable the outside of the W1 window */
WCTLD__CCW0E = (1 << 9), /* Enable Rotation Parameter on the W0 window */
WCTLD__CCW0A__OUTSIDE = (1 << 8), /* Enable the outside of the W0 window */
WCTLD__RPLOG__AND = (1 << 7), /* Overlay logic for Color Calculation */
WCTLD__RPSWE = (1 << 5), /* Enable Color Calculation on the Sprite window */
WCTLD__RPSWA__OUTSIDE = (1 << 4), /* Enable the outside of the Sprite window */
WCTLD__RPW1E = (1 << 3), /* Enable Color Calculation on the W1 window */
WCTLD__RPW1A__OUTSIDE = (1 << 2), /* Enable the outside of the W1 window */
WCTLD__RPW0E = (1 << 1), /* Enable Color Calculation on the W0 window */
WCTLD__RPW0A__OUTSIDE = (1 << 0), /* Enable the outside of the W0 window */
};
// enum lwta0u_bit {
// };
// enum lwta0l_bit {
@ -607,75 +711,199 @@ enum bktau_bit {
// };
// enum lwta1l_bit {
// };
// enum spctl_bit {
// };
// enum sdctl_bit {
// };
enum spctl_bit {
#define SPCTL__SPCCCS(n) (((n) & 0b11) << 12)
#define SPCTL__SPCCN(n) (((n) & 0b111) << 8)
SPCTL__SPCLMD = (1 << 5),
SPCTL__SPWINEN = (1 << 4),
#define SPCTL__SPTYPE(n) (((n) & 0b1111) << 0)
};
enum sdctl_bit {
SDCTL__TPSDSL = (1 << 8),
SDCTL__BKSDEN = (1 << 5),
SDCTL__R0SDEN = (1 << 4),
SDCTL__N3SDEN = (1 << 3),
SDCTL__N2SDEN = (1 << 2),
SDCTL__N1SDEN = (1 << 1),
SDCTL__N0SDEN = (1 << 0),
};
// enum craofa_bit {
#define CRAOFA__N3CAOS(n) (((n) & 0b111) << 12)
#define CRAOFA__N2CAOS(n) (((n) & 0b111) << 8)
#define CRAOFA__N1CAOS(n) (((n) & 0b111) << 4)
#define CRAOFA__N0CAOS(n) (((n) & 0b111) << 0)
// };
// enum craofb_bit {
#define CRAOFB__SPCAOS(n) (((n) & 0b111) << 4)
#define CRAOFB__R0CAOS(n) (((n) & 0b111) << 0)
// };
// enum lnclen_bit {
// };
// enum sfprmd_bit {
// };
// enum ccctl_bit {
// };
// enum sfccmd_bit {
// };
enum lnclen_bit {
LNCLEN__SPLCEN = (1 << 5),
LNCLEN__R0LCEN = (1 << 4),
LNCLEN__N3LCEN = (1 << 3),
LNCLEN__N2LCEN = (1 << 2),
LNCLEN__N1LCEN = (1 << 1),
LNCLEN__N0LCEN = (1 << 0),
};
enum sfprmd_bit {
SFPRMD__R0SPRM__MODE0 = (0b00 << 8),
SFPRMD__R0SPRM__MODE1 = (0b01 << 8),
SFPRMD__R0SPRM__MODE2 = (0b10 << 8),
SFPRMD__N3SPRM__MODE0 = (0b00 << 6),
SFPRMD__N3SPRM__MODE1 = (0b01 << 6),
SFPRMD__N3SPRM__MODE2 = (0b10 << 6),
SFPRMD__N2SPRM__MODE0 = (0b00 << 4),
SFPRMD__N2SPRM__MODE1 = (0b01 << 4),
SFPRMD__N2SPRM__MODE2 = (0b10 << 4),
SFPRMD__N1SPRM__MODE0 = (0b00 << 2),
SFPRMD__N1SPRM__MODE1 = (0b01 << 2),
SFPRMD__N1SPRM__MODE2 = (0b10 << 2),
SFPRMD__N0SPRM__MODE0 = (0b00 << 0),
SFPRMD__N0SPRM__MODE1 = (0b01 << 0),
SFPRMD__N0SPRM__MODE2 = (0b10 << 0),
};
enum ccctl_bit {
CCCTL__BOKEN = (1 << 15),
CCCTL__BOKN__SPRITE = (0b000 << 12),
CCCTL__BOKN__RBG0 = (0b001 << 12),
CCCTL__BOKN__NBG0_OR_RBG1 = (0b010 << 12),
CCCTL__BOKN__NBG1_OR_EXBG = (0b100 << 12),
CCCTL__BOKN__NBG2 = (0b101 << 12),
CCCTL__BOKN__NBG3 = (0b110 << 12),
CCCTL__EXCCEN = (1 << 10),
CCCTL__CCRTMD = (1 << 9),
CCCTL__CCMD = (1 << 8),
CCCTL__SPCCEN = (1 << 6),
CCCTL__LCCCEN = (1 << 5),
CCCTL__R0CCEN = (1 << 4),
CCCTL__N3CCEN = (1 << 3),
CCCTL__N2CCEN = (1 << 2),
CCCTL__N1CCEN = (1 << 1),
CCCTL__N0CCEN = (1 << 0),
};
enum sfccmd_bit {
SFCCMD__R0SCCM__PER_SCREEN = (0b00 << 8),
SFCCMD__R0SCCM__PER_CHARACTER = (0b01 << 8),
SFCCMD__R0SCCM__PER_DOT = (0b10 << 8),
SFCCMD__R0SCCM__COLOR_DATA_MSB = (0b11 << 8),
SFCCMD__N3SCCM__PER_SCREEN = (0b00 << 6),
SFCCMD__N3SCCM__PER_CHARACTER = (0b01 << 6),
SFCCMD__N3SCCM__PER_DOT = (0b10 << 6),
SFCCMD__N3SCCM__COLOR_DATA_MSB = (0b11 << 6),
SFCCMD__N2SCCM__PER_SCREEN = (0b00 << 4),
SFCCMD__N2SCCM__PER_CHARACTER = (0b01 << 4),
SFCCMD__N2SCCM__PER_DOT = (0b10 << 4),
SFCCMD__N2SCCM__COLOR_DATA_MSB = (0b11 << 4),
SFCCMD__N1SCCM__PER_SCREEN = (0b00 << 2),
SFCCMD__N1SCCM__PER_CHARACTER = (0b01 << 2),
SFCCMD__N1SCCM__PER_DOT = (0b10 << 2),
SFCCMD__N1SCCM__COLOR_DATA_MSB = (0b11 << 2),
SFCCMD__N0SCCM__PER_SCREEN = (0b00 << 0),
SFCCMD__N0SCCM__PER_CHARACTER = (0b01 << 0),
SFCCMD__N0SCCM__PER_DOT = (0b10 << 0),
SFCCMD__N0SCCM__COLOR_DATA_MSB = (0b11 << 0),
};
// enum prisa_bit {
#define PRISA__S1PRIN(n) ((n) << 8)
#define PRISA__S0PRIN(n) ((n) << 0)
#define PRISA__S1PRIN(n) (((n) & 0xff) << 8)
#define PRISA__S0PRIN(n) (((n) & 0xff) << 0)
// };
// enum prisb_bit {
#define PRISA__S3PRIN(n) ((n) << 8)
#define PRISA__S2PRIN(n) ((n) << 0)
#define PRISA__S3PRIN(n) (((n) & 0xff) << 8)
#define PRISA__S2PRIN(n) (((n) & 0xff) << 0)
// };
// enum prisc_bit {
#define PRISA__S5PRIN(n) ((n) << 8)
#define PRISA__S4PRIN(n) ((n) << 0)
#define PRISA__S5PRIN(n) (((n) & 0xff) << 8)
#define PRISA__S4PRIN(n) (((n) & 0xff) << 0)
// };
// enum prisd_bit {
#define PRISA__S7PRIN(n) ((n) << 8)
#define PRISA__S6PRIN(n) ((n) << 0)
#define PRISA__S7PRIN(n) (((n) & 0xff) << 8)
#define PRISA__S6PRIN(n) (((n) & 0xff) << 0)
// };
// enum prina_bit {
#define PRINA__N1PRIN(n) (((n) & 0xff) << 8)
#define PRINA__N0PRIN(n) (((n) & 0xff) << 0)
// };
// enum prinb_bit {
#define PRINB__N3PRIN(n) (((n) & 0xff) << 8)
#define PRINB__N2PRIN(n) (((n) & 0xff) << 0)
// };
// enum prir_bit {
#define PRIR__R0PRIN(n) (((n) & 0xff) << 0)
// };
// enum ccrsa_bit {
#define CCRSA__S1CCRT(n) (((n) & 0xff) << 8)
#define CCRSA__S0CCRT(n) (((n) & 0xff) << 0)
// };
// enum ccrsb_bit {
#define CCRSB__S3CCRT(n) (((n) & 0xff) << 8)
#define CCRSB__S2CCRT(n) (((n) & 0xff) << 0)
// };
// enum ccrsc_bit {
#define CCRSC__S5CCRT(n) (((n) & 0xff) << 8)
#define CCRSC__S4CCRT(n) (((n) & 0xff) << 0)
// };
// enum ccrsd_bit {
#define CCRSD__S7CCRT(n) (((n) & 0xff) << 8)
#define CCRSD__S6CCRT(n) (((n) & 0xff) << 0)
// };
// enum ccrna_bit {
#define CCRNA__N1CCRT(n) (((n) & 0xff) << 8)
#define CCRNA__N0CCRT(n) (((n) & 0xff) << 0)
// };
// enum ccrnb_bit {
#define CCRNB__N3CCRT(n) (((n) & 0xff) << 8)
#define CCRNB__N2CCRT(n) (((n) & 0xff) << 0)
// };
// enum ccrr_bit {
#define CCRR__R0CCRT(n) (((n) & 0xff) << 0)
// };
// enum ccrlb_bit {
#define CCRLB__BKCCRT(n) (((n) & 0xff) << 8)
#define CCRLB__LCCCRT(n) (((n) & 0xff) << 0)
// };
// enum clofen_bit {
// };
// enum clofsl_bit {
// };
enum clofen_bit {
CLOFEN__SPCOEN = (1 << 6),
CLOFEN__BKCOEN = (1 << 5),
CLOFEN__R0COEN = (1 << 4),
CLOFEN__N3COEN = (1 << 3),
CLOFEN__N2COEN = (1 << 2),
CLOFEN__N1COEN = (1 << 1),
CLOFEN__N0COEN = (1 << 0),
};
enum clofsl_bit {
CLOFEN__SPCOSL = (1 << 6),
CLOFEN__BKCOSL = (1 << 5),
CLOFEN__R0COSL = (1 << 4),
CLOFEN__N3COSL = (1 << 3),
CLOFEN__N2COSL = (1 << 2),
CLOFEN__N1COSL = (1 << 1),
CLOFEN__N0COSL = (1 << 0),
};
// enum coar_bit {
#define COAR__COARD() ((n) & 0x1ff)
// };
// enum coag_bit {
#define COAG__COAGR() ((n) & 0x1ff)
// };
// enum coab_bit {
#define COAB__COABL() ((n) & 0x1ff)
// };
// enum cobr_bit {
#define COBR__COBRD() ((n) & 0x1ff)
// };
// enum cobg_bit {
#define COBG__COBGR() ((n) & 0x1ff)
// };
// enum cobb_bit {
#define COBB__COBBL() ((n) & 0x1ff)
// };