vdp2: define N1CHCN bits

common.mk

@@ -8,7 +8,7 @@ AFLAGS = --fatal-warnings
 
 CARCH = -m2 -mb
 CFLAGS += -falign-functions=4 -ffunction-sections -fdata-sections -fshort-enums -ffreestanding -nostdlib
-CFLAGS += -Wall -Werror -Wfatal-errors -Wno-error=unused-variable
+CFLAGS += -Wall -Werror -Wfatal-errors -Wno-error=unused-variable -Wno-array-bounds
 DEPFLAGS = -MMD -E
 LDFLAGS = --gc-sections --print-gc-sections --no-warn-rwx-segment --print-memory-usage --entry=_start --orphan-handling=error
 CXXFLAGS = -std=c++20 -fno-exceptions -fno-non-call-exceptions -fno-rtti -fno-threadsafe-statics
@@ -30,7 +30,9 @@ define BUILD_BINARY_O
 		$< $@
 endef
 
-as_obj_binary = _binary_$(subst .,_,$(subst /,_,$(basename $(1))))
+makefile_path := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
+makefile_relative = $(shell realpath --relative-to $(makefile_path) $(1))
+as_obj_binary = _binary_$(subst -,_,$(subst .,_,$(subst /,_,$(subst .h,,$(call makefile_relative,$(1))))))
 
 define BUILD_BINARY_H
 	@echo gen $@

regs/vdp1.csv

@@ -0,0 +1,12 @@
+"block","offset","address","size","name","r/w","description"
+"vdp1",10,"0000",2,"TVMR","RW",
+"vdp1",10,"0002",2,"FBCR","RW",
+"vdp1",10,"0004",2,"PTMR","RW",
+"vdp1",10,"0006",2,"EWDR","RW",
+"vdp1",10,"0008",2,"EWLR","RW",
+"vdp1",10,"000a",2,"EWRR","RW",
+"vdp1",10,"000c",2,"ENDR","RW",
+"vdp1",10,"0010",2,"EDSR","RW",
+"vdp1",10,"0012",2,"LOPR","RW",
+"vdp1",10,"0014",2,"COPR","RW",
+"vdp1",10,"0016",2,"MODR","RW",

regs/vdp2.csv

@@ -0,0 +1,132 @@
+"block","offset","address","size","name","r/w","description"
+"vdp2",18,"0000","2","TVMD","RW","Device ID"
+"vdp2",18,"0002",2,"EXTEN","RW",
+"vdp2",18,"0004",2,"TVSTAT","R",
+"vdp2",18,"0006",2,"VRSIZE","RW",
+"vdp2",18,"0008",2,"HCNT","R",
+"vdp2",18,"000a",2,"VCNT","R",
+"vdp2",18,"000e",2,"RAMCTL","RW",
+"vdp2",18,"0010",4,"CYCA0","RW",
+"vdp2",18,"0014",4,"CYCA1","RW",
+"vdp2",18,"0018",4,"CYCB0","RW",
+"vdp2",18,"001c",4,"CYCB1","RW",
+"vdp2",18,"0020",2,"BGON","RW",
+"vdp2",18,"0022",2,"MZCTL","RW",
+"vdp2",18,"0024",2,"SFSEL","RW",
+"vdp2",18,"0026",2,"SFCODE","RW",
+"vdp2",18,"0028",2,"CHCTLA","RW",
+"vdp2",18,"002a",2,"CHCTLB","RW",
+"vdp2",18,"002c",2,"BMPNA","RW",
+"vdp2",18,"002e",2,"BMPNB","RW",
+"vdp2",18,"0030",2,"PNCN0","RW",
+"vdp2",18,"0032",2,"PNCN1","RW",
+"vdp2",18,"0034",2,"PNCN2","RW",
+"vdp2",18,"0036",2,"PNCN3","RW",
+"vdp2",18,"0038",2,"PNCR","RW",
+"vdp2",18,"003a",2,"PLSZ","RW",
+"vdp2",18,"003c",2,"MPOFN","RW",
+"vdp2",18,"003e",2,"MPOFR","RW",
+"vdp2",18,"0040",2,"MPABN0","RW",
+"vdp2",18,"0042",2,"MPCDN0","RW",
+"vdp2",18,"0044",2,"MPABN1","RW",
+"vdp2",18,"0046",2,"MPCDN1","RW",
+"vdp2",18,"0048",2,"MPABN2","RW",
+"vdp2",18,"004a",2,"MPCDN2","RW",
+"vdp2",18,"004c",2,"MPABN3","RW",
+"vdp2",18,"004e",2,"MPCDN3","RW",
+"vdp2",18,"0050",2,"MPABRA","RW",
+"vdp2",18,"0052",2,"MPCDRA","RW",
+"vdp2",18,"0054",2,"MPEFRA","RW",
+"vdp2",18,"0056",2,"MPGHRA","RW",
+"vdp2",18,"0058",2,"MPIJRA","RW",
+"vdp2",18,"005a",2,"MPKLRA","RW",
+"vdp2",18,"005c",2,"MPMNRA","RW",
+"vdp2",18,"005e",2,"MPOPRA","RW",
+"vdp2",18,"0060",2,"MPABRB","RW",
+"vdp2",18,"0062",2,"MPCDRB","RW",
+"vdp2",18,"0064",2,"MPEFRB","RW",
+"vdp2",18,"0066",2,"MPGHRB","RW",
+"vdp2",18,"0068",2,"MPIJRB","RW",
+"vdp2",18,"006a",2,"MPKLRB","RW",
+"vdp2",18,"006c",2,"MPMNRB","RW",
+"vdp2",18,"006e",2,"MPOPRB","RW",
+"vdp2",18,"0070",2,"SCXIN0","RW",
+"vdp2",18,"0072",2,"SCXDN0","RW",
+"vdp2",18,"0074",2,"SCYIN0","RW",
+"vdp2",18,"0076",2,"SCYDN0","RW",
+"vdp2",18,"0078",2,"ZMXIN0","RW",
+"vdp2",18,"007a",2,"ZMXDN0","RW",
+"vdp2",18,"007c",2,"ZMYIN0","RW",
+"vdp2",18,"007e",2,"ZMYDN0","RW",
+"vdp2",18,"0080",2,"SCXIN1","RW",
+"vdp2",18,"0082",2,"SCXDN1","RW",
+"vdp2",18,"0084",2,"SCYIN1","RW",
+"vdp2",18,"0086",2,"SCYDN1","RW",
+"vdp2",18,"0088",2,"ZMXIN1","RW",
+"vdp2",18,"008a",2,"ZMXDN1","RW",
+"vdp2",18,"008c",2,"ZMYIN1","RW",
+"vdp2",18,"008e",2,"ZMYDN1","RW",
+"vdp2",18,"0090",2,"SCXN2","RW",
+"vdp2",18,"0092",2,"SCYN2","RW",
+"vdp2",18,"0094",2,"SCXN3","RW",
+"vdp2",18,"0096",2,"SCYN3","RW",
+"vdp2",18,"0098",2,"ZMCTL","RW",
+"vdp2",18,"009a",2,"SCRCTL","RW",
+"vdp2",18,"009c",2,"VCSTAU","RW",
+"vdp2",18,"009e",2,"VCSTAL","RW",
+"vdp2",18,"00a0",4,"LSTA0","RW",
+"vdp2",18,"00a4",4,"LSTA1","RW",
+"vdp2",18,"00a8",4,"LCTA","RW",
+"vdp2",18,"00ac",4,"BKTA","RW",
+"vdp2",18,"00b0",2,"RPMD","RW",
+"vdp2",18,"00b2",2,"RPRCTL","RW",
+"vdp2",18,"00b4",2,"KTCTL","RW",
+"vdp2",18,"00b6",2,"KTAOF","RW",
+"vdp2",18,"00b8",2,"OVPNRA","RW",
+"vdp2",18,"00ba",2,"OVPNRB","RW",
+"vdp2",18,"00bc",4,"RPTA","RW",
+"vdp2",18,"00c0",2,"WPSX0","RW",
+"vdp2",18,"00c2",2,"WPSY0","RW",
+"vdp2",18,"00c4",2,"WPEX0","RW",
+"vdp2",18,"00c6",2,"WPEY0","RW",
+"vdp2",18,"00c8",2,"WPSX1","RW",
+"vdp2",18,"00ca",2,"WPSY1","RW",
+"vdp2",18,"00cc",2,"WPEX1","RW",
+"vdp2",18,"00ce",2,"WPEY1","RW",
+"vdp2",18,"00d0",2,"WCTLA","RW",
+"vdp2",18,"00d2",2,"WCTLB","RW",
+"vdp2",18,"00d4",2,"WCTLC","RW",
+"vdp2",18,"00d6",2,"WCTLD","RW",
+"vdp2",18,"00d8",4,"LWTA0","RW",
+"vdp2",18,"00dc",4,"LWTA1","RW",
+"vdp2",18,"00e0",2,"SPCTL","RW",
+"vdp2",18,"00e2",2,"SDCTL","RW",
+"vdp2",18,"00e4",2,"CRAOFA","RW",
+"vdp2",18,"00e6",2,"CRAOFB","RW",
+"vdp2",18,"00e8",2,"LNCLEN","RW",
+"vdp2",18,"00ea",2,"SFPRMD","RW",
+"vdp2",18,"00ec",2,"CCCTL","RW",
+"vdp2",18,"00ee",2,"SFCCMD","RW",
+"vdp2",18,"00f0",2,"PRISA","RW",
+"vdp2",18,"00f2",2,"PRISB","RW",
+"vdp2",18,"00f4",2,"PRISC","RW",
+"vdp2",18,"00f6",2,"PRISD","RW",
+"vdp2",18,"00f8",2,"PRINA","RW",
+"vdp2",18,"00fa",2,"PRINB","RW",
+"vdp2",18,"00fc",2,"PRIR","RW",
+"vdp2",18,"0100",2,"CCRSA","RW",
+"vdp2",18,"0102",2,"CCRSB","RW",
+"vdp2",18,"0104",2,"CCRSC","RW",
+"vdp2",18,"0106",2,"CCRSD","RW",
+"vdp2",18,"0108",2,"CCRNA","RW",
+"vdp2",18,"010a",2,"CCRNB","RW",
+"vdp2",18,"010c",2,"CCRR","RW",
+"vdp2",18,"010e",2,"CCRLB","RW",
+"vdp2",18,"0110",2,"CLOFEN","RW",
+"vdp2",18,"0112",2,"CLOFSL","RW",
+"vdp2",18,"0114",2,"COAR","RW",
+"vdp2",18,"0116",2,"COAG","RW",
+"vdp2",18,"0118",2,"COAB","RW",
+"vdp2",18,"011a",2,"COBR","RW",
+"vdp2",18,"011c",2,"COBG","RW",
+"vdp2",18,"011e",2,"COBB","RW",

scu.h

@@ -35,10 +35,10 @@ typedef struct scu_reg {
   reg32 _res10;
   reg32 _res11;
   reg32 DTSA;
-  reg32 PPAF;
+  reg32 PPAF; // 0080 DSP Program Control Port
-  reg32 PPD;
+  reg32 PPD;  // 0084 DSP Program RAM DataPort
-  reg32 PDA;
+  reg32 PDA;  // 0088 DSP Data RAM Address Port
-  reg32 PDD;
+  reg32 PDD;  // 008c DSP Data RAM DataPort
   reg32 T0C;
   reg32 T1S;
   reg32 T1MD;

sh2.h

@@ -193,3 +193,15 @@ enum tocr_bits {
 // enum vcrd_bits {
 #define VCRD__FOVV(n) (n << 8)
 // };
+
+enum ccr_bits {
+  CCR__W__WAY0 = (0b00 << 6),
+  CCR__W__WAY1 = (0b01 << 6),
+  CCR__W__WAY2 = (0b10 << 6),
+  CCR__W__WAY3 = (0b11 << 6),
+  CCR__CP__CACHE_PURGE = (0b1 << 4),
+  CCR__TW__TWO_WAY_MODE = (0b1 << 3),
+  CCR__OD__DATA_REPLACEMENT_DISABLE = (0b1 << 2),
+  CCR__ID__INSTRUCTION_REPLACEMENT_DISABLE = (0b1 << 1),
+  CCR__CE__CACHE_ENABLE = (0b1 << 0),
+};

sh2.lds

@@ -4,6 +4,7 @@ MEMORY
 {
   work_ram_l : ORIGIN = 0x00200000, LENGTH = 1M
   work_ram_h : ORIGIN = 0x06000000, LENGTH = 1M
+  two_way_cache : ORIGIN = 0xc0000000, LENGTH = 2048
 }
 SECTIONS
 {
@@ -12,6 +13,7 @@ SECTIONS
   .text ALIGN(4) : SUBALIGN(4)
   {
     KEEP(*(.text.start))
+    *(.text.start.*)
     *(.text)
     *(.text.*)
   } > work_ram_h
@@ -45,6 +47,12 @@ SECTIONS
     *(.bss.work_ram_l)
   } > work_ram_l
 
+  . = 0xc0000000;
+
+  .cache ALIGN(4) : SUBALIGN(4)
+  {
+  } > two_way_cache AT> work_ram_h
+
   INCLUDE "saturn/debug.lds"
 }
 

vdp1.h

@@ -35,7 +35,7 @@ typedef struct vdp1_cmd {
     };
     cmd_point point[4];
   };
-  u16 GDRA;
+  u16 GRDA;
   u16 _dummy;
 } vdp1_cmd;
 
@@ -99,7 +99,9 @@ enum pmod_bit {
 #define PMOD__COLOR_MODE__COLOR_BANK_256  (0b100 << 3)
 #define PMOD__COLOR_MODE__RGB             (0b101 << 3)
 
-#define PMOD__COLOR_CALCULATION ( << 0)
+#define PMOD__COLOR_CALCULATION__GOURAUD_SHADING (0b100 << 0)
+#define PMOD__COLOR_CALCULATION__HALF_ORIGINAL_GRAPHIC (0b010 << 0)
+#define PMOD__COLOR_CALCULATION__HALF_BACKGROUND (0b001 << 0)
 };
 
 // see "Pixel Data in Frame Buffer" in VDP1 manual

vdp2.h

@@ -169,8 +169,13 @@ typedef struct vdp2_reg {
   reg16 KTAOF;  /* COEFFICIENT TABLE ADDRESS OFFSET (ROTATION PARAMETER A, B) */
   reg16 OVPNRA; /* SCREEN OVER PATTERN NAME (ROTATION PARAMETER A) */
   reg16 OVPNRB; /* SCREEN OVER PATTERN NAME (ROTATION PARAMETER B) */
-  reg16 RPTAU;  /* ROTATION PARAMETER TABLE ADDRESS (ROTATION PARAMETER A,B) */
+  union {
-  reg16 RPTAL;  /* ROTATION PARAMETER TABLE ADDRESS (ROTATION PARAMETER A,B) */
+    struct {
+      reg16 RPTAU;  /* ROTATION PARAMETER TABLE ADDRESS (ROTATION PARAMETER A,B) */
+      reg16 RPTAL;  /* ROTATION PARAMETER TABLE ADDRESS (ROTATION PARAMETER A,B) */
+    };
+    reg32 RPTA;
+  };
   reg16 WPSX0;  /* WINDOW POSITION (W0, HORIZONTAL START POINT) */
   reg16 WPSY0;  /* WINDOW POSITION (W0, VERTICAL START POINT) */
   reg16 WPEX0;  /* WINDOW POSITION (W0, HORIZONTAL END POINT) */
@@ -275,11 +280,23 @@ enum vrsize_bit {
 // };
 enum ramctl_bit {
   RAMCTL__CRKTE = (1 << 15),
-  RAMCTL__VRBMD = (1 << 9),
-  RAMCTL__VRAMD = (1 << 8),
   RAMCTL__CRMD__RGB_5BIT_1024 = (0b00 << 12),
   RAMCTL__CRMD__RGB_5BIT_2048 = (0b01 << 12),
-  RAMCTL__CRMD__RGB_8BIT_1024 = (0b10 << 12)
+  RAMCTL__CRMD__RGB_8BIT_1024 = (0b10 << 12),
+  RAMCTL__VRBMD = (1 << 9),
+  RAMCTL__VRAMD = (1 << 8),
+  RAMCTL__RDBSB1__COEFFICIENT_TABLE = (0b01 << 6),
+  RAMCTL__RDBSB1__PATTERN_NAME_TABLE = (0b10 << 6),
+  RAMCTL__RDBSB1__CHARACTER_PATTERN_TABLE = (0b11 << 6),
+  RAMCTL__RDBSB0__COEFFICIENT_TABLE = (0b01 << 4),
+  RAMCTL__RDBSB0__PATTERN_NAME_TABLE = (0b10 << 4),
+  RAMCTL__RDBSB0__CHARACTER_PATTERN_TABLE = (0b11 << 4),
+  RAMCTL__RDBSA1__COEFFICIENT_TABLE = (0b01 << 2),
+  RAMCTL__RDBSA1__PATTERN_NAME_TABLE = (0b10 << 2),
+  RAMCTL__RDBSA1__CHARACTER_PATTERN_TABLE = (0b11 << 2),
+  RAMCTL__RDBSA0__COEFFICIENT_TABLE = (0b01 << 0),
+  RAMCTL__RDBSA0__PATTERN_NAME_TABLE = (0b10 << 0),
+  RAMCTL__RDBSA0__CHARACTER_PATTERN_TABLE = (0b11 << 0),
 };
 // enum cyca0l_bit {
 // };
@@ -319,9 +336,9 @@ enum bgon_bit {
 // };
 enum chctla_bit {
   CHCTLA__N1CHCN__16_COLOR = (0b00 << 12),
-  CHCTLA__N1CHCN__256_COLOR = (0b00 << 12),
+  CHCTLA__N1CHCN__256_COLOR = (0b01 << 12),
-  CHCTLA__N1CHCN__2048_COLOR = (0b00 << 12),
+  CHCTLA__N1CHCN__2048_COLOR = (0b10 << 12),
-  CHCTLA__N1CHCN__32K_COLOR = (0b00 << 12),
+  CHCTLA__N1CHCN__32K_COLOR = (0b11 << 12),
 
   CHCTLA__N1BMSZ__512x256_DOT = (0b00 << 10),
   CHCTLA__N1BMSZ__512x512_DOT = (0b01 << 10),
@@ -436,9 +453,13 @@ enum pncr_bit {
 
 enum plsz_bit {
   PLSZ__RBOVR__ = (0b00 << 14),
-  PLSZ__RBPLSZ__ = (0b00 << 12),
+  PLSZ__RBPLSZ__1x1 = (0b00 << 12),
+  PLSZ__RBPLSZ__2x1 = (0b01 << 12),
+  PLSZ__RBPLSZ__2x2 = (0b10 << 12),
   PLSZ__RAOVR__ = (0b00 << 10),
-  PLSZ__RAPLSZ__ = (0b00 << 8),
+  PLSZ__RAPLSZ__1x1 = (0b00 << 8),
+  PLSZ__RAPLSZ__2x1 = (0b01 << 8),
+  PLSZ__RAPLSZ__2x2 = (0b10 << 8),
 
   PLSZ__N3PLSZ__1x1 = (0b00 << 6),
   PLSZ__N3PLSZ__2x1 = (0b01 << 6),
@@ -506,36 +527,68 @@ enum plsz_bit {
 // };
 #define MPN3__N3MP(n) (((n) << 24) | ((n) << 16) | ((n) << 8) | ((n) << 0))
 // enum mpabra_bit {
+#define MPABRA__RAMPB(n) (((n) & 0b111111) << 8)
+#define MPABRA__RAMPA(n) (((n) & 0b111111) << 0)
 // };
 // enum mpcdra_bit {
+#define MPCDRA__RAMPD(n) (((n) & 0b111111) << 8)
+#define MPCDRA__RAMPC(n) (((n) & 0b111111) << 0)
 // };
 // enum mpefra_bit {
+#define MPEFRA__RAMPF(n) (((n) & 0b111111) << 8)
+#define MPEFRA__RAMPE(n) (((n) & 0b111111) << 0)
 // };
 // enum mpghra_bit {
+#define MPGHRA__RAMPH(n) (((n) & 0b111111) << 8)
+#define MPGHRA__RAMPG(n) (((n) & 0b111111) << 0)
 // };
 // enum mpijra_bit {
+#define MPIJRA__RAMPJ(n) (((n) & 0b111111) << 8)
+#define MPIJRA__RAMPI(n) (((n) & 0b111111) << 0)
 // };
 // enum mpklra_bit {
+#define MPKLRA__RAMPL(n) (((n) & 0b111111) << 8)
+#define MPKLRA__RAMPK(n) (((n) & 0b111111) << 0)
 // };
 // enum mpmnra_bit {
+#define MPMNRA__RAMPN(n) (((n) & 0b111111) << 8)
+#define MPMNRA__RAMPM(n) (((n) & 0b111111) << 0)
 // };
 // enum mpopra_bit {
+#define MPOPRA__RAMPP(n) (((n) & 0b111111) << 8)
+#define MPOPRA__RAMPO(n) (((n) & 0b111111) << 0)
 // };
 // enum mpabrb_bit {
+#define MPABRB__RBMPB(n) (((n) & 0b111111) << 8)
+#define MPABRB__RBMPA(n) (((n) & 0b111111) << 0)
 // };
 // enum mpcdrb_bit {
+#define MPCDRB__RBMPD(n) (((n) & 0b111111) << 8)
+#define MPCDRB__RBMPC(n) (((n) & 0b111111) << 0)
 // };
 // enum mpefrb_bit {
+#define MPEFRB__RBMPF(n) (((n) & 0b111111) << 8)
+#define MPEFRB__RBMPE(n) (((n) & 0b111111) << 0)
 // };
 // enum mpghrb_bit {
+#define MPGHRB__RBMPH(n) (((n) & 0b111111) << 8)
+#define MPGHRB__RBMPG(n) (((n) & 0b111111) << 0)
 // };
 // enum mpijrb_bit {
+#define MPIJRB__RBMPJ(n) (((n) & 0b111111) << 8)
+#define MPIJRB__RBMPI(n) (((n) & 0b111111) << 0)
 // };
 // enum mpklrb_bit {
+#define MPKLRB__RBMPL(n) (((n) & 0b111111) << 8)
+#define MPKLRB__RBMPK(n) (((n) & 0b111111) << 0)
 // };
 // enum mpmnrb_bit {
+#define MPMNRB__RBMPN(n) (((n) & 0b111111) << 8)
+#define MPMNRB__RBMPM(n) (((n) & 0b111111) << 0)
 // };
 // enum mpoprb_bit {
+#define MPOPRB__RBMPP(n) (((n) & 0b111111) << 8)
+#define MPOPRB__RBMPO(n) (((n) & 0b111111) << 0)
 // };
 // enum scxin0_bit {
 // };
@@ -603,8 +656,14 @@ enum bktau_bit {
 };
 // enum bktal_bit {
 // };
-// enum rpmd_bit {
+enum bkta_bit {
-// };
+  BKTA__BKCLMD_SINGLE_COLOR = (0 << 31),
+  BKTA__BKCLMD_PER_LINE = (1 << 31),
+};
+enum rpmd_bit {
+  RPMD__ROTATION_PARAMETER_A = (0b00 << 0),
+  RPMD__ROTATION_PARAMETER_B = (0b01 << 0),
+};
 // enum rprctl_bit {
 // };
 // enum ktctl_bit {
@@ -919,3 +978,39 @@ enum clofsl_bit {
 
 #define PATTERN_NAME_TABLE_1WORD__PALETTE(n) (((n) & 0b1111) << 12)
 #define PATTERN_NAME_TABLE_1WORD__CHARACTER(n) (((n) & 0x3ff) << 0)
+
+//
+// rotation screen
+//
+
+struct vdp2_rotation_parameter_table {
+  int32_t screen_start_coordinate_xst;
+  int32_t screen_start_coordinate_yst;
+  int32_t screen_start_coordinate_zst;
+  int32_t screen_vertical_coordinate_increment_dxst;
+  int32_t screen_vertical_coordinate_increment_dyst;
+  int32_t screen_horizontal_coordinate_increment_dx;
+  int32_t screen_horizontal_coordinate_increment_dy;
+  int32_t rotation_matrix_parameter_a;
+  int32_t rotation_matrix_parameter_b;
+  int32_t rotation_matrix_parameter_c;
+  int32_t rotation_matrix_parameter_d;
+  int32_t rotation_matrix_parameter_e;
+  int32_t rotation_matrix_parameter_f;
+  int16_t viewpoint_coordinate_px;
+  int16_t viewpoint_coordinate_py;
+  int16_t viewpoint_coordinate_pz;
+  int16_t _pad0;
+  int16_t center_point_coordinate_px;
+  int16_t center_point_coordinate_py;
+  int16_t center_point_coordinate_pz;
+  int16_t _pad1;
+  int32_t horizontal_shift_mx;
+  int32_t horizontal_shift_my;
+  int32_t scaling_coefficient_kx;
+  int32_t scaling_coefficient_ky;
+  int32_t coefficient_table_start_address_kast;
+  int32_t coefficient_table_vertical_address_increment_dkast;
+  int32_t coefficient_table_horizontal_address_increment_dkax;
+};
+static_assert((sizeof (struct vdp2_rotation_parameter_table)) == 0x60);