correct smpc intback timing
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parent
76c4998664
commit
fe51d016df
27
main.c
27
main.c
@ -19,6 +19,19 @@ void timer0_int(void)
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scu.reg.IST &= ~(IST__TIMER0);
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}
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void v_blank_in_int(void) __attribute__ ((interrupt_handler));
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void v_blank_in_int(void)
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{
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scu.reg.IST &= ~(IST__V_BLANK_IN);
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// reset FRC to zero
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sh2.reg.FRC.H = 0;
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sh2.reg.FRC.L = 0;
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// enable output compare interrupt
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sh2.reg.TIER = TIER__OCIAE;
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}
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void oci_int(void) __attribute__ ((interrupt_handler));
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void oci_int(void)
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{
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@ -37,6 +50,9 @@ void oci_int(void)
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smpc.reg.IREG2 = INTBACK__IREG2__MAGIC;
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smpc.reg.COMREG = COMREG__INTBACK;
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// disable output compare interrupt (to be re-enabled on the next v_blank_in)
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sh2.reg.TIER = 0;
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}
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void smpc_int(void) __attribute__ ((interrupt_handler));
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@ -44,8 +60,6 @@ void smpc_int(void)
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{
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scu.reg.IST &= ~(IST__SMPC);
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smpc.reg.IREG0 = INTBACK__IREG0__BREAK;
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}
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@ -198,6 +212,7 @@ void start(void)
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vec[SCU_VEC__TIMER0] = (u32)(&timer0_int);
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vec[SCU_VEC__SMPC] = (u32)(&smpc_int);
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vec[SCU_VEC__V_BLANK_IN] = (u32)(&v_blank_in_int);
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//scu.reg.T0C = 5;
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//scu.reg.T1MD = T1MD__TENB;
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@ -235,16 +250,10 @@ void start(void)
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// we are required to write the upper bit prior to
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// writing the lower byte
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sh2.reg.OCRAB.L = 63;
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sh2.reg.FRC.H = 0;
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sh2.reg.FRC.L = 0;
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// enable output compare interrupt
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sh2.reg.TIER = TIER__OCIAE;
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// reset/enable interrupts
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scu.reg.IST = 0;
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scu.reg.IMS = ~(IMS__SMPC);
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scu.reg.IMS = ~(IMS__SMPC | IMS__V_BLANK_IN);
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while (1) {
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vec[0] = scu.reg.IST;
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