vdp1 experiments
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main.c
87
main.c
@ -1,4 +1,5 @@
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#include "vdp2.h"
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#include "vdp1.h"
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void start(void) {
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//
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@ -10,12 +11,12 @@ void start(void) {
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vdp2.reg.BGON = 0;
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// BKTAU/BKTAL are shifted left 1: (0x4000 << 1 = 0x8000)
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vdp2.reg.BKTA = REG_UL(BKTAU__BKCLMD_SINGLE_COLOR, 0x4000);
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// background color, rgb15
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vdp2.vram.u16[0x8000 / 2] = (0x05 << 0); // dark red
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//
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// vdp2: define and place a single character on NBG0
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//
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@ -51,5 +52,89 @@ void start(void) {
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// (bit 5~0) * 0x4000
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vdp2.vram.u32[(0x4000 / 4)] = PATTERN_NAME_TABLE_2WORD__CHARACTER(1);
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//
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// vdp1:
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//
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// The VBE setting must be set immediately after the V-blank IN interrupt.
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//
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// TVM settings must be performed from the second H-blank IN interrupt after
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// the V-blank IN interrupt to the H-blank IN interrupt immediately after the
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// V-blank OUT interrupt.
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vdp1.reg.TVMR = ( TVMR__TVM__NTSC_PAL
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| TVMR__TVM__FRAMEBUFFER_NONROTATION
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| TVMR__TVM__16BPP
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);
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// make FCM and FCT settings immediately after V-blank OUT
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vdp1.reg.FBCR = 0;
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// "A command table must always be stored at address 00000H to 0001EH."
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// we can't trigger a plot yet because we have no (valid) table.
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//vdp1.reg.PTMR = PTMR__PTM__FRAME_CHANGE;
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vdp1.reg.EWDR = 0; // black
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// upper-left
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vdp1.reg.EWLR = PTMR__EWLR__16BPP_X1(0) | PTMR__EWLR__Y1(0);
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// lower-right
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vdp1.reg.EWRR = PTMR__EWRR__16BPP_X3(319) | PTMR__EWRR__Y3(239);
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vdp1.vram.cmd[0].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__USER_CLIP_COORDINATES;
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vdp1.vram.cmd[0].LINK = 0;
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vdp1.vram.cmd[0].XA = 0;
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vdp1.vram.cmd[0].YA = 0;
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vdp1.vram.cmd[0].XC = 319;
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vdp1.vram.cmd[0].YC = 239;
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vdp1.vram.cmd[1].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__SYSTEM_CLIP_COORDINATES;
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vdp1.vram.cmd[1].LINK = 0;
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vdp1.vram.cmd[1].XC = 319;
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vdp1.vram.cmd[1].YC = 239;
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vdp1.vram.cmd[2].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__LOCAL_COORDINATE;
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vdp1.vram.cmd[2].LINK = 0;
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vdp1.vram.cmd[2].XA = 0;
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vdp1.vram.cmd[2].YA = 0;
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vdp1.vram.cmd[3].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__POLYGON;
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vdp1.vram.cmd[3].LINK = 0;
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vdp1.vram.cmd[3].PMOD = CTRL__PMOD__ECD | CTRL__PMOD__SPD;
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vdp1.vram.cmd[3].COLR = 0x2; // palette color #2
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vdp1.vram.cmd[3].XA = 50;
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vdp1.vram.cmd[3].YA = 50;
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vdp1.vram.cmd[3].XB = 150;
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vdp1.vram.cmd[3].YB = 50;
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vdp1.vram.cmd[3].XC = 150;
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vdp1.vram.cmd[3].YC = 150;
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vdp1.vram.cmd[3].XD = 50;
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vdp1.vram.cmd[3].YD = 150;
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vdp1.vram.cmd[4].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__POLYGON;
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vdp1.vram.cmd[4].LINK = 0;
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vdp1.vram.cmd[4].PMOD = CTRL__PMOD__ECD | CTRL__PMOD__SPD;
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vdp1.vram.cmd[4].COLR = (1 << 15) | (0x31 << 10) | (0x31 << 0); // RGB15 magenta
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vdp1.vram.cmd[4].XA = 100;
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vdp1.vram.cmd[4].YA = 50;
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vdp1.vram.cmd[4].XB = 150;
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vdp1.vram.cmd[4].YB = 100;
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vdp1.vram.cmd[4].XC = 100;
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vdp1.vram.cmd[4].YC = 150;
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vdp1.vram.cmd[4].XD = 50;
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vdp1.vram.cmd[4].YD = 100;
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vdp1.vram.cmd[5].CTRL = CTRL__END;
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// priorities
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vdp2.reg.PRISA = 0x0101;
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vdp2.reg.PRISB = 0x0101;
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vdp2.reg.PRISC = 0x0101;
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vdp2.reg.PRISD = 0x0101;
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// start drawing
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vdp1.reg.PTMR = PTMR__PTM__FRAME_CHANGE;
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while (1) {}
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}
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6
type.h
6
type.h
@ -9,4 +9,10 @@ static_assert((sizeof (reg8)) == 1);
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static_assert((sizeof (reg16)) == 2);
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static_assert((sizeof (reg32)) == 4);
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typedef volatile unsigned short u16;
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typedef volatile short s16;
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static_assert((sizeof (u16)) == 2);
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static_assert((sizeof (s16)) == 2);
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#define REG_UL(U, L) (((U) << 16) | (L))
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170
vdp1.h
Normal file
170
vdp1.h
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#include "type.h"
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/* command table */
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typedef struct vdp1_cmd {
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u16 CTRL;
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u16 LINK;
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u16 PMOD;
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u16 COLR;
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u16 SRCA;
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u16 SIZE;
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s16 XA;
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s16 YA;
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s16 XB;
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s16 YB;
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s16 XC;
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s16 YC;
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s16 XD;
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s16 YD;
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u16 GDRA;
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u16 _dummy;
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} vdp1_cmd;
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static_assert((sizeof (struct vdp1_cmd)) == 0x20);
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/* command table bits */
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enum bits_ctrl {
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CTRL__END = (1 << 15),
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CTRL__JP__JUMP_NEXT = (0b000 << 12),
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CTRL__JP__JUMP_ASSIGN = (0b001 << 12),
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CTRL__JP__JUMP_CALL = (0b010 << 12),
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CTRL__JP__JUMP_RETURN = (0b011 << 12),
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CTRL__JP__SKIP_NEXT = (0b100 << 12),
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CTRL__JP__SKIP_ASSIGN = (0b101 << 12),
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CTRL__JP__SKIP_CALL = (0b110 << 12),
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CTRL__JP__SKIP_RETURN = (0b111 << 12),
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CTRL__ZP__TWO = (0b0000 << 8),
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CTRL__ZP__UPPER_LEFT = (0b0101 << 8),
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CTRL__ZP__UPPER_CENTER = (0b0110 << 8),
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CTRL__ZP__UPPER_RIGHT = (0b0111 << 8),
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CTRL__ZP__CENTER_LEFT = (0b1001 << 8),
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CTRL__ZP__CENTER_CENTER = (0b1010 << 8),
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CTRL__ZP__CENTER_RIGHT = (0b1011 << 8),
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CTRL__ZP__LOWER_LEFT = (0b1101 << 8),
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CTRL__ZP__LOWER_CENTER = (0b1110 << 8),
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CTRL__ZP__LOWER_RIGHT = (0b1111 << 8),
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CTRL__DIR__INVERTED_HORIZONTALLY = (0b01 << 4),
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CTRL__DIR__INVERTED_VERTICALLY = (0b10 << 4),
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CTRL__COMM__NORMAL_SPRITE = (0b0000),
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CTRL__COMM__SCALED_SPRITE = (0b0001),
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CTRL__COMM__DISTORTED_SPRITE = (0b0010),
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CTRL__COMM__POLYGON = (0b0100),
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CTRL__COMM__POLYLINE = (0b0101),
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CTRL__COMM__LINE = (0b0110),
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CTRL__COMM__USER_CLIP_COORDINATES = (0b1000),
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CTRL__COMM__SYSTEM_CLIP_COORDINATES = (0b1001),
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CTRL__COMM__LOCAL_COORDINATE = (0b1010),
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};
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enum bits_pmod {
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CTRL__PMOD__MON = (1 << 15),
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CTRL__PMOD__HSS = (1 << 12),
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CTRL__PMOD__PCLP = (1 << 11),
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CTRL__PMOD__CLIP = (1 << 10),
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CTRL__PMOD__CMOD = (1 << 9),
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CTRL__PMOD__MESH = (1 << 8),
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CTRL__PMOD__ECD = (1 << 7),
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CTRL__PMOD__SPD = (1 << 6),
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#define CTRL__PMOD__COLOR_MODE ( << 3)
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#define CTRL__PMOD__COLOR_CALCULATION ( << 0)
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};
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/* memory offsets */
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typedef union vdp1_vram {
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unsigned char u8[0x080000 / 1];
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unsigned short u16[0x080000 / 2];
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unsigned long u32[0x080000 / 4];
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vdp1_cmd cmd[0x080000 / 0x20];
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} vdp1_vram;
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static_assert((sizeof (union vdp1_vram)) == 0x080000);
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typedef union vdp1_framebuffer {
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unsigned char u8[0x040000 / 1];
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unsigned short u16[0x040000 / 2];
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unsigned long u32[0x040000 / 4];
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} vdp1_framebuffer;
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static_assert((sizeof (union vdp1_framebuffer)) == 0x040000);
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typedef unsigned char vdp1_res0[0x040000];
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typedef struct vdp1_reg {
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reg16 TVMR; /* TV MODE SELECTION */
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reg16 FBCR; /* FRAME BUFFER CHANGE MODE */
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reg16 PTMR; /* PLOT TROGGER */
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reg16 EWDR; /* ERASE/WRITE DATA */
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reg16 EWLR; /* ERASE/WRITE UPPER-LEFT COORDINATE */
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reg16 EWRR; /* ERASE/WRITE LOWER-RIGHT COORDINATE */
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reg16 ENDR; /* PLOT ABNORMAL END */
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reg16 _res0;
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reg16 EDSR; /* TRANSFER END STATUS */
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reg16 LOPR; /* LAST OPERATION COMMAND ADDRESS */
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reg16 COPR; /* CURRENT OPERATION COMMAND ADDRESS */
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reg16 MODR; /* MODE STATUS */
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} vdp1_reg;
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static_assert((offsetof (struct vdp1_reg, ENDR)) == 0x0C);
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static_assert((offsetof (struct vdp1_reg, EDSR)) == 0x10);
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static_assert((sizeof (struct vdp1_reg)) == 24);
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struct vdp1 {
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vdp1_vram vram;
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vdp1_framebuffer framebuffer;
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vdp1_res0 _res0;
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vdp1_reg reg;
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};
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static_assert((sizeof (struct vdp1)) == 0x100018);
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static_assert((offsetof (struct vdp1, vram)) == 0x000000);
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static_assert((offsetof (struct vdp1, framebuffer)) == 0x080000);
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static_assert((offsetof (struct vdp1, reg)) == 0x100000);
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extern struct vdp1 vdp1 __asm("vdp1");
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/* register bits */
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enum bits_tvmr {
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TVMR__VBE = (1 << 3),
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TVMR__TVM__NTSC_PAL = (0 << 2),
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TVMR__TVM__HDTV_31KC = (1 << 2),
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TVMR__TVM__FRAMEBUFFER_NONROTATION = (0 << 1),
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TVMR__TVM__FRAMEBUFFER_ROTATION = (1 << 1),
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TVMR__TVM__16BPP = (0 << 0),
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TVMR__TVM__8BPP = (1 << 0),
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};
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enum bits_fbcr {
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FBCR__EOS = (1 << 4),
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FBCR__DIE = (1 << 3),
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FBCR__DIL = (1 << 2),
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FBCR__FCM = (1 << 1),
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FBCR__FCT = (1 << 0),
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};
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enum bits__ptmr {
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PTMR__PTM__IDLE = 0b00,
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PTMR__PTM__NOW = 0b01,
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PTMR__PTM__FRAME_CHANGE = 0b10,
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};
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// enum bits__ewlr {
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#define PTMR__EWLR__16BPP_X1(n) ((n / 8 ) << 9)
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#define PTMR__EWLR__8BPP_X1(n) ((n / 16) << 9)
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#define PTMR__EWLR__Y1(n) (n << 0)
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// }
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// enum bits__ewrr {
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#define PTMR__EWRR__16BPP_X3(n) (((n + 1) / 8 ) << 9)
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#define PTMR__EWLR__8BPP_X3(n) (((n + 1) / 16) << 9)
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#define PTMR__EWRR__Y3(n) (n << 0)
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// }
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