From a1a67522fe6f3c02e810b0eca6b020c7530f58ee Mon Sep 17 00:00:00 2001 From: Zack Buhman Date: Sun, 8 Jan 2023 11:53:54 -0800 Subject: [PATCH] scu, smpc, and sh2 register definitions This also improves sys_ip slightly. --- Makefile | 3 +- main.c | 56 +++++++- main.cue | 3 + scu.h | 164 ++++++++++++++++++++++++ segasmp/lib/sys_area.o | Bin 0 -> 316 bytes segasmp/lib/sys_areb.o | Bin 0 -> 316 bytes segasmp/lib/sys_arek.o | Bin 0 -> 316 bytes segasmp/lib/sys_arel.o | Bin 0 -> 316 bytes sh2.h | 97 ++++++++++++++ sh2.lds | 2 + smpc.h | 182 ++++++++++++++++++++++++++ sys_id.s | 2 +- sys_ip.lds | 30 ++++- vdp1.h | 14 +- vdp2.h | 284 ++++++++++++++++++++--------------------- 15 files changed, 680 insertions(+), 157 deletions(-) create mode 100644 main.cue create mode 100644 scu.h create mode 100755 segasmp/lib/sys_area.o create mode 100755 segasmp/lib/sys_areb.o create mode 100755 segasmp/lib/sys_arek.o create mode 100755 segasmp/lib/sys_arel.o create mode 100644 sh2.h create mode 100644 smpc.h diff --git a/Makefile b/Makefile index 48d131f..266ea7f 100644 --- a/Makefile +++ b/Makefile @@ -19,7 +19,8 @@ sys_%.o: segasmp/lib/sys_%.o SYS_IP_OBJ += sys_id.o SYS_IP_OBJ += sys_sec.o -SYS_IP_OBJ += sys_arej.o sys_aret.o sys_areu.o sys_aree.o +SYS_IP_OBJ += sys_area.o sys_areb.o sys_aree.o sys_arej.o +SYS_IP_OBJ += sys_arek.o sys_arel.o sys_aret.o sys_areu.o SYS_IP_OBJ += sys_init.o SYS_IP_OBJ += smpsys.o diff --git a/main.c b/main.c index fb9ff19..3d0f4aa 100644 --- a/main.c +++ b/main.c @@ -1,5 +1,7 @@ #include "vdp2.h" #include "vdp1.h" +#include "scu.h" +#include "smpc.h" void fill_32(u32 * buf, u32 v, s32 n) { @@ -10,7 +12,40 @@ void fill_32(u32 * buf, u32 v, s32 n) } } -void start(void) { +void timer0_int(void) __attribute__ ((interrupt_handler)); +void timer0_int(void) +{ + scu.reg.IST &= ~(IST__TIMER0); + + // The SMPC uses the V-BLANK-IN interrupt to execute internal tasks. At this + // time, issuing commands for 300 µs from V-BLANK-IN is prohibited. + + while (smpc.reg.SF != 0) {} + + smpc.reg.SF = 0; + + smpc.reg.IREG0 = INTBACK__IREG0__STATUS_DISABLE; + smpc.reg.IREG1 = ( INTBACK__IREG1__PERIPHERAL_DATA_ENABLE + | INTBACK__IREG1__PORT2_15BYTE + | INTBACK__IREG1__PORT1_15BYTE + ); + smpc.reg.IREG2 = INTBACK__IREG2__MAGIC; + + smpc.reg.COMREG = COMREG__INTBACK; +} + +void smpc_int(void) __attribute__ ((interrupt_handler)); +void smpc_int(void) +{ + scu.reg.IST &= ~(IST__SMPC); + + + + smpc.reg.IREG0 = INTBACK__IREG0__BREAK; +} + +void start(void) +{ // // vdp2: enable and set Back Screen color // @@ -148,5 +183,22 @@ void start(void) { // start drawing vdp1.reg.PTMR = PTMR__PTM__FRAME_CHANGE; - while (1) {} + // + // scu1: + // + + // If timer0 is counting at roughly 15.73426 kHz (1/63.5556 µs), we can count + // to 300µs at roughly T0C = 5 (~317.778 µs). H-Blank-IN subtracts about + // 10.9µs which is still (~306 µs) more than 300µs. + + vec[SCU_VEC__TIMER0] = (u32)(&timer0_int); + vec[SCU_VEC__SMPC] = (u32)(&smpc_int); + scu.reg.T0C = 5; + scu.reg.T1MD = T1MD__TENB; + scu.reg.IST = 0; + scu.reg.IMS = ~(IMS__TIMER0 | IMS__SMPC); + + while (1) { + vec[0] = scu.reg.IST; + } } diff --git a/main.cue b/main.cue new file mode 100644 index 0000000..ce51c75 --- /dev/null +++ b/main.cue @@ -0,0 +1,3 @@ +FILE "main.iso" BINARY + TRACK 01 MODE1/2048 + INDEX 01 00:00:00 diff --git a/scu.h b/scu.h new file mode 100644 index 0000000..ec30845 --- /dev/null +++ b/scu.h @@ -0,0 +1,164 @@ +#include "type.h" + +typedef struct scu_reg { + reg32 D0R; + reg32 D0W; + reg32 D0C; + reg32 D0AD; + reg32 D0EN; + reg32 D0MD; + reg32 _res0; + reg32 _res1; + reg32 D1R; + reg32 D1W; + reg32 D1C; + reg32 D1AD; + reg32 D1EN; + reg32 D1MD; + reg32 _res2; + reg32 _res3; + reg32 D2R; + reg32 D2W; + reg32 D2C; + reg32 D2AD; + reg32 D2EN; + reg32 D2MD; + reg32 _res4; + reg32 _res5; + reg32 DTSP; + reg32 _res6; + reg32 _res7; + reg32 _res8; + reg32 _res9; + reg32 _res10; + reg32 _res11; + reg32 DTSA; + reg32 PPAF; + reg32 PPD; + reg32 PDA; + reg32 PDD; + reg32 T0C; + reg32 T1S; + reg32 T1MD; + reg32 _res12; + reg32 IMS; + reg32 IST; + reg32 AIACK; + reg32 _res13; + reg32 ASR0; + reg32 ASR1; + reg32 AREF; + reg32 _res14; + reg32 _res15; + reg32 RSEL; + reg32 VER; + reg32 _res16; +} scu_reg; + +static_assert((sizeof (struct scu_reg)) == 0xD0); +static_assert((offsetof (struct scu_reg, D1R)) == 0x20); +static_assert((offsetof (struct scu_reg, AIACK)) == 0xA8); + +struct scu { + scu_reg reg; +}; + +extern struct scu scu __asm("scu"); + +/* bits */ + +enum ims_bits { + IMS__A_BUS = (1 << 15), + IMS__DRAW_END = (1 << 13), + IMS__DMA_ILLEGAL = (1 << 12), + IMS__DMA0_END = (1 << 11), + IMS__DMA1_END = (1 << 10), + IMS__DMA2_END = (1 << 9), + IMS__PAD = (1 << 8), + IMS__SMPC = (1 << 7), + IMS__SOUND_REQUEST = (1 << 6), + IMS__DSP_END = (1 << 5), + IMS__TIMER1 = (1 << 4), + IMS__TIMER0 = (1 << 3), + IMS__H_BLANK_IN = (1 << 2), + IMS__V_BLANK_OUT = (1 << 1), + IMS__V_BLANK_IN = (1 << 0), +}; + +enum ist_bits { + IST__EXT15 = (1 << 31), + IST__EXT14 = (1 << 30), + IST__EXT13 = (1 << 29), + IST__EXT12 = (1 << 28), + IST__EXT11 = (1 << 27), + IST__EXT10 = (1 << 26), + IST__EXT09 = (1 << 25), + IST__EXT08 = (1 << 24), + IST__EXT07 = (1 << 23), + IST__EXT06 = (1 << 22), + IST__EXT05 = (1 << 21), + IST__EXT04 = (1 << 20), + IST__EXT03 = (1 << 19), + IST__EXT02 = (1 << 18), + IST__EXT01 = (1 << 17), + IST__EXT00 = (1 << 16), + + IST__DRAW_END = (1 << 13), + IST__DMA_ILLEGAL = (1 << 12), + IST__DMA0_END = (1 << 11), + IST__DMA1_END = (1 << 10), + IST__DMA2_END = (1 << 9), + IST__PAD = (1 << 8), + IST__SMPC = (1 << 7), + IST__SOUND_REQUEST = (1 << 6), + IST__DSP_END = (1 << 5), + IST__TIMER1 = (1 << 4), + IST__TIMER0 = (1 << 3), + IST__H_BLANK_IN = (1 << 2), + IST__V_BLANK_OUT = (1 << 1), + IST__V_BLANK_IN = (1 << 0), +}; + +enum t1md_bits { + T1MD__T1MD = (1 << 8), + T1MD__TENB = (1 << 0), +}; + +enum scu_vec { + SCU_VEC__V_BLANK_IN = 0x40, + SCU_VEC__V_BLANK_OUT, + SCU_VEC__H_BLANK_IN, + SCU_VEC__TIMER0, + SCU_VEC__TIMER1, + SCU_VEC__DSP_END, + SCU_VEC__SOUND_REQUEST, + SCU_VEC__SMPC, + SCU_VEC__PAD, + SCU_VEC__DMA2_END, + SCU_VEC__DMA1_END, + SCU_VEC__DMA0_END, + SCU_VEC__DMA_ILLEGAL, + SCU_VEC__DRAW_END, + __scu_vec_res0, + __scu_vec_res1, + SCU_VEC__EXT00, + SCU_VEC__EXT01, + SCU_VEC__EXT02, + SCU_VEC__EXT03, + SCU_VEC__EXT04, + SCU_VEC__EXT05, + SCU_VEC__EXT06, + SCU_VEC__EXT07, + SCU_VEC__EXT08, + SCU_VEC__EXT09, + SCU_VEC__EXT10, + SCU_VEC__EXT11, + SCU_VEC__EXT12, + SCU_VEC__EXT13, + SCU_VEC__EXT14, + SCU_VEC__EXT15, +}; + +static_assert(SCU_VEC__EXT15 == 0x5f); + +extern reg32 vec[0x60] __asm("vec"); diff --git a/segasmp/lib/sys_area.o b/segasmp/lib/sys_area.o new file mode 100755 index 0000000000000000000000000000000000000000..4297cd3fa55cde5ff95802c0ea49705f51065f61 GIT binary patch literal 316 zcmZQ&U|=>VkXp{bz_130Ie?f|uOzji1js-F3P5%b5+B4=&`U`yNrVV0fcOw52I-)e zR9p-d1*rjHY@lfY9|NabevyJ>u&1L!fTNE>Vo_?Mo&p@`rDf)%LUsQC$H0)zn3k9g e6M%}NxSbK`IUq*25yjn1P&H^SLUA)Qb~OOfF&qy7 literal 0 HcmV?d00001 diff --git a/segasmp/lib/sys_areb.o b/segasmp/lib/sys_areb.o new file mode 100755 index 0000000000000000000000000000000000000000..1217a301df50772976190b3d5d7be4e5b8b38c0a GIT binary patch literal 316 zcmZQ&U|=>VkXp&Wz_130Ie?f|uOzji1js-F3P5%b5+B4=&`U`yNrVV0fcOw52I-)e zR9p-d1*rjHY@lfY9|NabevyJxkYkjmkDdZL&`ZnANrmeC|BrzooiQyj8zul1M{zqN X&~reHZX=4jnV@RWT!i9gX6$MJ8Z8>( literal 0 HcmV?d00001 diff --git a/segasmp/lib/sys_arek.o b/segasmp/lib/sys_arek.o new file mode 100755 index 0000000000000000000000000000000000000000..3422cdbfbc55296fd48fc6e22003e926b3cbdf6a GIT binary patch literal 316 zcmZQ&U|=>VkXpmQzyQJ=K+LLFl3Gy$WFP?rAiD>N4`M3lr6iUlLIf2+dv8nOTY literal 0 HcmV?d00001 diff --git a/segasmp/lib/sys_arel.o b/segasmp/lib/sys_arel.o new file mode 100755 index 0000000000000000000000000000000000000000..029ff168375ec2443a6460b6cb652a0d281b3614 GIT binary patch literal 316 zcmZQ&U|=>VkXp;Yz_130Ie?f|uOzji1js-F3P5%b5+B4=&`U`yNrVV0fcOw52I-)e zR9p-d1*rjHY@lfY9|NabevyKYV~D4pf}^i%kf*bwo&p@`rDf)%LUsQC$H0)zn3k9g e6M%}NxSbK`IUq*25yjn1P&H^SLUA)Qb~OO3;~UEW literal 0 HcmV?d00001 diff --git a/sh2.h b/sh2.h new file mode 100644 index 0000000..5922bee --- /dev/null +++ b/sh2.h @@ -0,0 +1,97 @@ +#include "type.h" + +typedef struct sh2_reg { + reg8 SMR; // 0x000 + reg8 BRR; // 0x001 + reg8 SCR; // 0x002 + reg8 TDR; // 0x003 + reg8 SSR; // 0x004 + reg8 RDR; // 0x005 + reg8 _res0[10]; + reg8 TIER; // 0x010 + reg8 FTCSR; // 0x011 + reg16 FRC; // 0x012 + reg16 OCRA_B; // 0x014 + reg8 TCR; // 0x016 + reg8 TOCR; // 0x017 + reg16 FICR; // 0x018 + reg8 _res1[70]; + reg16 IPRB; // 0x060 + reg16 VCRA; // 0x062 + reg16 VCRB; // 0x064 + reg16 VCRC; // 0x066 + reg16 VCRD; // 0x068 + reg8 _res2[7]; + reg8 DRCR0; // 0x071 + reg8 DRCR1; // 0x072 + reg8 _res3[13]; + reg8 WTCSR; // 0x080 + reg8 WTCNT; // 0x081 + reg8 _res4[1]; + reg8 WSTCSR; // 0x083 + reg8 _res5[13]; + reg8 SBYCR; // 0x091 + reg8 CCR; // 0x092 + reg8 _res6[77]; + reg16 ICR; // 0x0e0 + reg16 IPRA; // 0x0e2 + reg16 VCRWDT; // 0x0e4 + reg8 _res7[26]; + reg32 DVSR; // 0x100 + reg32 DVDNT; // 0x104 + reg32 DVCR; // 0x108 + reg32 VCRDIV; // 0x10c + reg32 DVDNTH; // 0x110 + reg32 DVDNTL; // 0x114 + reg8 _res8[40]; + reg16 BARAH; // 0x140 + reg16 BARAL; // 0x142 + reg16 BAMRAH; // 0x144 + reg16 BAMRAL; // 0x146 + reg16 BBRA; // 0x148 + reg8 _res9[22]; + reg16 BARBH; // 0x160 + reg16 BARBL; // 0x162 + reg16 BAMRBH; // 0x164 + reg16 BAMRBL; // 0x166 + reg16 BBRB; // 0x168 + reg8 _res10[6]; + reg16 BDRBH; // 0x170 + reg16 BDRBL; // 0x172 + reg16 BDMRBH; // 0x174 + reg16 BDMRBL; // 0x176 + reg16 BRCR; // 0x178 + reg8 _res11[6]; + reg32 SAR0; // 0x180 + reg32 DAR0; // 0x184 + reg32 TCR0; // 0x188 + reg32 CHCR0; // 0x18c + reg32 SAR1; // 0x190 + reg32 DAR1; // 0x194 + reg32 TCR1; // 0x198 + reg32 CHCR1; // 0x19c + reg32 VCRMA0; // 0x1a0 + reg8 _res12[4]; + reg32 VCRDMA1; // 0x1a8 + reg8 _res13[4]; + reg32 DMAOR; // 0x1b0 + reg8 _res14[44]; + reg32 BCR1; // 0x1e0 + reg32 BCR2; // 0x1e4 + reg32 WCR; // 0x1e8 + reg32 MCR; // 0x1ec + reg32 RTCSR; // 0x1f0 + reg32 RTCNT; // 0x1f4 + reg32 RTCOR; // 0x1f8 + reg8 _res15[4]; +} sh2_reg; + +static_assert((sizeof (struct sh2_reg)) == 0x200); +static_assert((offsetof (struct sh2_reg, OCRA_B)) == 0x014); +static_assert((offsetof (struct sh2_reg, BCR1)) == 0x1e0); + +struct sh2 { + sh2_reg reg; +}; + +extern struct sh2 sh2 __asm("sh2"); diff --git a/sh2.lds b/sh2.lds index ddf7ae9..47b87d6 100644 --- a/sh2.lds +++ b/sh2.lds @@ -37,3 +37,5 @@ scsp = 0x05A00000; vdp1 = 0x05C00000; vdp2 = 0x05E00000; scu = 0x05FE0000; +vec = 0x06000000; +sh2 = 0xfffffe00; diff --git a/smpc.h b/smpc.h new file mode 100644 index 0000000..6bdf86d --- /dev/null +++ b/smpc.h @@ -0,0 +1,182 @@ +#include "type.h" + +typedef struct smpc_reg { + reg8 _res0; + reg8 IREG0; + reg8 _res1; + reg8 IREG1; + reg8 _res2; + reg8 IREG2; + reg8 _res3; + reg8 IREG3; + reg8 _res4; + reg8 IREG4; + reg8 _res5; + reg8 IREG5; + reg8 _res6; + reg8 IREG6; + reg8 _res7; + reg8 _res8; + reg8 _res9; + reg8 _res10; + reg8 _res11; + reg8 _res12; + reg8 _res13; + reg8 _res14; + reg8 _res15; + reg8 _res16; + reg8 _res17; + reg8 _res18; + reg8 _res19; + reg8 _res20; + reg8 _res21; + reg8 _res22; + reg8 _res23; + reg8 COMREG; + reg8 _res24; + reg8 OREG0; + reg8 _res25; + reg8 OREG1; + reg8 _res26; + reg8 OREG2; + reg8 _res27; + reg8 OREG3; + reg8 _res28; + reg8 OREG4; + reg8 _res29; + reg8 OREG5; + reg8 _res30; + reg8 OREG6; + reg8 _res31; + reg8 OREG7; + reg8 _res32; + reg8 OREG8; + reg8 _res33; + reg8 OREG9; + reg8 _res34; + reg8 OREG10; + reg8 _res35; + reg8 OREG11; + reg8 _res36; + reg8 OREG12; + reg8 _res37; + reg8 OREG13; + reg8 _res38; + reg8 OREG14; + reg8 _res39; + reg8 OREG15; + reg8 _res40; + reg8 OREG16; + reg8 _res41; + reg8 OREG17; + reg8 _res42; + reg8 OREG18; + reg8 _res43; + reg8 OREG19; + reg8 _res44; + reg8 OREG20; + reg8 _res45; + reg8 OREG21; + reg8 _res46; + reg8 OREG22; + reg8 _res47; + reg8 OREG23; + reg8 _res48; + reg8 OREG24; + reg8 _res49; + reg8 OREG25; + reg8 _res50; + reg8 OREG26; + reg8 _res51; + reg8 OREG27; + reg8 _res52; + reg8 OREG28; + reg8 _res53; + reg8 OREG29; + reg8 _res54; + reg8 OREG30; + reg8 _res55; + reg8 OREG31; + reg8 _res56; + reg8 SR; + reg8 _res57; + reg8 SF; + reg8 _res58; + reg8 _res59; + reg8 _res60; + reg8 _res61; + reg8 _res62; + reg8 _res63; + reg8 _res64; + reg8 _res65; + reg8 _res66; + reg8 _res67; + reg8 _res68; + reg8 _res69; + reg8 _res70; + reg8 _res71; + reg8 _res72; + reg8 _res73; + reg8 _res74; + reg8 PDR1; + reg8 _res75; + reg8 PDR2; + reg8 _res76; + reg8 DDR1; + reg8 _res77; + reg8 DDR2; + reg8 _res78; + reg8 IOSEL; + reg8 _res79; + reg8 EXLE; +} smpc_reg; + +static_assert((sizeof (struct smpc_reg)) == 0x80); +static_assert((offsetof (struct smpc_reg, OREG0)) == 0x21); +static_assert((offsetof (struct smpc_reg, SF)) == 0x63); + +struct smpc { + smpc_reg reg; +}; + +extern struct smpc smpc __asm("smpc"); + +/* bits */ + +enum comreg_bit { + COMREG__MSHON = 0x00, + COMREG__SSHON = 0x02, + COMREG__SSHOFF = 0x03, + COMREG__SNDON = 0x06, + COMREG__SNDOFF = 0x07, + COMREG__CDON = 0x08, + COMREG__CDOFF = 0x09, + COMREG__SYSRES = 0x0D, + COMREG__CKCHG352 = 0x0E, + COMREG__CKCHG320 = 0x0F, + COMREG__INTBACK = 0x10, + COMREG__SETTIME = 0x16, + COMREG__SETSMEM = 0x17, + COMREG__NMIREQ = 0x18, + COMREG__RESENAB = 0x19, + COMREG__RESDISA = 0x1A, +}; + +enum intback_ireg_bit { + INTBACK__IREG0__CONTINUE = (1 << 7), + INTBACK__IREG0__BREAK = (1 << 6), + INTBACK__IREG0__STATUS_DISABLE = (0x00), + INTBACK__IREG0__STATUS_ENABLE = (0x01), + + + INTBACK__IREG1__PORT2_15BYTE = (0b00 << 6), + INTBACK__IREG1__PORT2_256BYTE = (0b01 << 6), + INTBACK__IREG1__PORT2_0BYTE = (0b11 << 6), + INTBACK__IREG1__PORT1_15BYTE = (0b00 << 4), + INTBACK__IREG1__PORT1_256BYTE = (0b01 << 4), + INTBACK__IREG1__PORT1_0BYTE = (0b11 << 4), + INTBACK__IREG1__PERIPHERAL_DATA_ENABLE = (1 << 3), + INTBACK__IREG1__NOT_OPTIMIZED = (1 << 1), + + INTBACK__IREG2__MAGIC = (0xF0), +}; diff --git a/sys_id.s b/sys_id.s index dd52c77..a2f0a88 100644 --- a/sys_id.s +++ b/sys_id.s @@ -4,7 +4,7 @@ .ascii "SEGA TP KAISHA-A" /* 10: maker ID */ .ascii "999999999 V1.000" /* 20: product number, version */ .ascii "19941122CD-1/1 " /* 30: release date, device information */ - .ascii "JTUE " /* 40: compatible area symbol */ + .ascii "JABEKLTU " /* 40: compatible area symbol */ .ascii "J " /* 50: compatible peripheral */ .ascii "GAME TITLE " /* 60: game title */ .ascii " " /* 70: */ diff --git a/sys_ip.lds b/sys_ip.lds index 37cb1ed..6e0924b 100644 --- a/sys_ip.lds +++ b/sys_ip.lds @@ -3,19 +3,41 @@ OUTPUT_ARCH(sh) MEMORY { - rom (arx) : ORIGIN = 0x06002000, LENGTH = 4M + ip (arx) : ORIGIN = 0x06002000, LENGTH = 4096 } SECTIONS { - .text : ALIGN(4) + .text : { KEEP(*(.text.id)) KEEP(*(.text.sec)) - KEEP(*(.text.are*)) + + /* + SEGA SATURN TECHNICAL BULLETIN #SOA-12: + + Please make sure that the area symbols and area codes + match in order. + + The final IP.BIN must be 4096 bytes. + + ABEJKLTU + */ + KEEP(*(.text.arej)) + KEEP(*(.text.area)) + KEEP(*(.text.areb)) + KEEP(*(.text.aree)) + KEEP(*(.text.arek)) + KEEP(*(.text.arel)) + KEEP(*(.text.aret)) + KEEP(*(.text.areu)) + KEEP(*(.text.init)) + KEEP(*(.text.main)) KEEP(*(.text.*)) - } > rom + + . = 4096; + } > ip } _text_size = SIZEOF(.text); diff --git a/vdp1.h b/vdp1.h index 207c3b6..500f638 100644 --- a/vdp1.h +++ b/vdp1.h @@ -25,7 +25,7 @@ static_assert((sizeof (struct vdp1_cmd)) == 0x20); /* command table bits */ -enum bits_ctrl { +enum ctrl_bit { CTRL__END = (1 << 15), CTRL__JP__JUMP_NEXT = (0b000 << 12), @@ -64,7 +64,7 @@ enum bits_ctrl { CTRL__COMM__LOCAL_COORDINATE = (0b1010), }; -enum bits_pmod { +enum pmod_bit { CTRL__PMOD__MON = (1 << 15), CTRL__PMOD__HSS = (1 << 12), CTRL__PMOD__PCLP = (1 << 11), @@ -133,7 +133,7 @@ extern struct vdp1 vdp1 __asm("vdp1"); /* register bits */ -enum bits_tvmr { +enum tvmr_bit { TVMR__VBE = (1 << 3), TVMR__TVM__NTSC_PAL = (0 << 2), TVMR__TVM__HDTV_31KC = (1 << 2), @@ -143,7 +143,7 @@ enum bits_tvmr { TVMR__TVM__8BPP = (1 << 0), }; -enum bits_fbcr { +enum fbcr_bit { FBCR__EOS = (1 << 4), FBCR__DIE = (1 << 3), FBCR__DIL = (1 << 2), @@ -151,19 +151,19 @@ enum bits_fbcr { FBCR__FCT = (1 << 0), }; -enum bits__ptmr { +enum ptmr_bit { PTMR__PTM__IDLE = 0b00, PTMR__PTM__NOW = 0b01, PTMR__PTM__FRAME_CHANGE = 0b10, }; -// enum bits__ewlr { +// enum ewlr_bit { #define PTMR__EWLR__16BPP_X1(n) ((n / 8 ) << 9) #define PTMR__EWLR__8BPP_X1(n) ((n / 16) << 9) #define PTMR__EWLR__Y1(n) (n << 0) // } -// enum bits__ewrr { +// enum ewrr_bit { #define PTMR__EWRR__16BPP_X3(n) (((n + 1) / 8 ) << 9) #define PTMR__EWLR__8BPP_X3(n) (((n + 1) / 16) << 9) #define PTMR__EWRR__Y3(n) (n << 0) diff --git a/vdp2.h b/vdp2.h index 23d05b2..2c09476 100644 --- a/vdp2.h +++ b/vdp2.h @@ -193,7 +193,7 @@ extern struct vdp2 vdp2 __asm("vdp2"); /* register bits */ -enum bits_tvmd { +enum tvmd_bit { TVMD__DISP = (1 << 15), TVMD__BDCLMD = (1 << 8), // display back screen TVMD__LSMD__NON_INTERLACE = (0b00 << 6), @@ -214,36 +214,36 @@ enum bits_tvmd { TVMD__HRESO__EXCLUSIVE_640 = (0b110 << 0), TVMD__HRESO__EXCLUSIVE_704 = (0b111 << 0), }; -// enum bits_exten { +// enum exten_bit { // }; -enum bits_tvstat { +enum tvstat_bit { TVSTAT__VBLANK = (1 << 3), }; -// enum bits_vrsize { +// enum vrsize_bit { // }; -// enum bits_hcnt { +// enum hcnt_bit { // }; -// enum bits_vcnt { +// enum vcnt_bit { // }; -// enum bits_ramctl { +// enum ramctl_bit { // }; -// enum bits_cyca0l { +// enum cyca0l_bit { // }; -// enum bits_cyca0u { +// enum cyca0u_bit { // }; -// enum bits_cyca1l { +// enum cyca1l_bit { // }; -// enum bits_cyca1u { +// enum cyca1u_bit { // }; -// enum bits_cycb0l { +// enum cycb0l_bit { // }; -// enum bits_cycb0u { +// enum cycb0u_bit { // }; -// enum bits_cycb1l { +// enum cycb1l_bit { // }; -// enum bits_cycb1u { +// enum cycb1u_bit { // }; -enum bits_bgon { +enum bgon_bit { BGON__R0TPON = (1 << 12), BGON__N3TPON = (1 << 11), BGON__N2TPON = (1 << 10), @@ -257,13 +257,13 @@ enum bits_bgon { BGON__N1ON = (1 << 1), BGON__N0ON = (1 << 0), }; -// enum bits_mzctl { +// enum mzctl_bit { // }; -// enum bits_sfsel { +// enum sfsel_bit { // }; -// enum bits_sfcode { +// enum sfcode_bit { // }; -enum bits_chctla { +enum chctla_bit { CHCTLA__N1CHCN__16_COLOR = (0b00 << 12), CHCTLA__N1CHCN__256_COLOR = (0b00 << 12), CHCTLA__N1CHCN__2K_COLOR = (0b00 << 12), @@ -297,7 +297,7 @@ enum bits_chctla { CHCTLA__N0CHSZ__1x1_CELL = (0 << 0), CHCTLA__N0CHSZ__2x2_CELL = (1 << 0), }; -enum bits_chctlb { +enum chctlb_bit { CHCTLB__R0CHCN__16_COLOR = (0b000 << 12), CHCTLB__R0CHCN__256_COLOR = (0b001 << 12), CHCTLB__R0CHCN__2K_COLOR = (0b010 << 12), @@ -325,12 +325,12 @@ enum bits_chctlb { CHCTLB__N2CHSZ__1x1_CELL = (0 << 4), CHCTLB__N2CHSZ__2x2_CELL = (1 << 4), }; -// enum bits_bmpna { +// enum bmpna_bit { // }; -// enum bits_bmpnb { +// enum bmpnb_bit { // }; -enum bits_pncn0 { +enum pncn0_bit { PNCN0__N0PNB__2WORD = (0 << 15), PNCN0__N0PNB__1WORD = (1 << 15), PNCN0__N0CNSM = (1 << 14), @@ -340,7 +340,7 @@ enum bits_pncn0 { #define PNCN0__N0SCN(n) (n << 0) }; -enum bits_pncn1 { +enum pncn1_bit { PNCN1__N1PNB__2WORD = (0 << 15), PNCN1__N1PNB__1WORD = (1 << 15), PNCN1__N1CNSM = (1 << 14), @@ -350,7 +350,7 @@ enum bits_pncn1 { #define PNCN1__N1SCN(n) (n << 0) }; -enum bits_pncn2 { +enum pncn2_bit { PNCN2__N2PNB__2WORD = (0 << 15), PNCN2__N2PNB__1WORD = (1 << 15), PNCN2__N2CNSM = (1 << 14), @@ -360,7 +360,7 @@ enum bits_pncn2 { #define PNCN2__N2SCN(n) (n << 0) }; -enum bits_pncn3 { +enum pncn3_bit { PNCN3__N3PNB__2WORD = (0 << 15), PNCN3__N3PNB__1WORD = (1 << 15), PNCN3__N3CNSM = (1 << 14), @@ -370,7 +370,7 @@ enum bits_pncn3 { #define PNCN3__N3SCN(n) (n << 0) }; -enum bits_pncr { +enum pncr_bit { PNCR__R0PNB__2WORD = (0 << 15), PNCR__R0PNB__1WORD = (1 << 15), PNCR__R0CNSM = (1 << 14), @@ -380,7 +380,7 @@ enum bits_pncr { #define PNCR__R0SCN(n) (n << 0) }; -enum bits_plsz { +enum plsz_bit { PLSZ__RBOVR__ = (0b00 << 14), PLSZ__RBPLSZ__ = (0b00 << 12), PLSZ__RAOVR__ = (0b00 << 10), @@ -402,258 +402,258 @@ enum bits_plsz { PLSZ__N0PLSZ__2x1 = (0b01 << 0), PLSZ__N0PLSZ__2x2 = (0b11 << 0), }; -// enum bits_mpofn { +// enum mpofn_bit { #define MPOFN__N3MP(n) (n << 12) #define MPOFN__N2MP(n) (n << 8) #define MPOFN__N1MP(n) (n << 4) #define MPOFN__N0MP(n) (n << 0) // }; -// enum bits_mpofr { +// enum mpofr_bit { #define MPOFR__RBMP(n) (n << 4) #define MPOFR__RAMP(n) (n << 0) // }; // 4.8 Maps § Map Selection Register -// enum bits_mpabn0 { +// enum mpabn0_bit { #define MPABN0__N0MPB(n) (n << 8) #define MPABN0__N0MPA(n) (n << 0) // }; -// enum bits_mpcdn0 { +// enum mpcdn0_bit { #define MPABN0__N0MPD(n) (n << 8) #define MPABN0__N0MPC(n) (n << 0) // }; -// enum bits_mpabn1 { +// enum mpabn1_bit { #define MPABN1__N1MPB(n) (n << 8) #define MPABN1__N1MPA(n) (n << 0) // }; -// enum bits_mpcdn1 { +// enum mpcdn1_bit { #define MPABN1__N1MPD(n) (n << 8) #define MPABN1__N1MPC(n) (n << 0) // }; -// enum bits_mpabn2 { +// enum mpabn2_bit { #define MPABN2__N2MPB(n) (n << 8) #define MPABN2__N2MPA(n) (n << 0) // }; -// enum bits_mpcdn2 { +// enum mpcdn2_bit { #define MPABN2__N2MPD(n) (n << 8) #define MPABN2__N2MPC(n) (n << 0) // }; -// enum bits_mpabn3 { +// enum mpabn3_bit { #define MPABN3__N3MPB(n) (n << 8) #define MPABN3__N3MPA(n) (n << 0) // }; -// enum bits_mpcdn3 { +// enum mpcdn3_bit { #define MPABN3__N3MPD(n) (n << 8) #define MPABN3__N3MPC(n) (n << 0) // }; -// enum bits_mpabra { +// enum mpabra_bit { // }; -// enum bits_mpcdra { +// enum mpcdra_bit { // }; -// enum bits_mpefra { +// enum mpefra_bit { // }; -// enum bits_mpghra { +// enum mpghra_bit { // }; -// enum bits_mpijra { +// enum mpijra_bit { // }; -// enum bits_mpklra { +// enum mpklra_bit { // }; -// enum bits_mpmnra { +// enum mpmnra_bit { // }; -// enum bits_mpopra { +// enum mpopra_bit { // }; -// enum bits_mpabrb { +// enum mpabrb_bit { // }; -// enum bits_mpcdrb { +// enum mpcdrb_bit { // }; -// enum bits_mpefrb { +// enum mpefrb_bit { // }; -// enum bits_mpghrb { +// enum mpghrb_bit { // }; -// enum bits_mpijrb { +// enum mpijrb_bit { // }; -// enum bits_mpklrb { +// enum mpklrb_bit { // }; -// enum bits_mpmnrb { +// enum mpmnrb_bit { // }; -// enum bits_mpoprb { +// enum mpoprb_bit { // }; -// enum bits_scxin0 { +// enum scxin0_bit { // }; -// enum bits_scxdn0 { +// enum scxdn0_bit { // }; -// enum bits_scyin0 { +// enum scyin0_bit { // }; -// enum bits_scydn0 { +// enum scydn0_bit { // }; -// enum bits_zmxin0 { +// enum zmxin0_bit { // }; -// enum bits_zmxdn0 { +// enum zmxdn0_bit { // }; -// enum bits_zmyin0 { +// enum zmyin0_bit { // }; -// enum bits_zmydn0 { +// enum zmydn0_bit { // }; -// enum bits_scxin1 { +// enum scxin1_bit { // }; -// enum bits_scxdn1 { +// enum scxdn1_bit { // }; -// enum bits_scyin1 { +// enum scyin1_bit { // }; -// enum bits_scydn1 { +// enum scydn1_bit { // }; -// enum bits_zmxin1 { +// enum zmxin1_bit { // }; -// enum bits_zmxdn1 { +// enum zmxdn1_bit { // }; -// enum bits_zmyin1 { +// enum zmyin1_bit { // }; -// enum bits_zmydn1 { +// enum zmydn1_bit { // }; -// enum bits_scxn2 { +// enum scxn2_bit { // }; -// enum bits_scyn2 { +// enum scyn2_bit { // }; -// enum bits_scxn3 { +// enum scxn3_bit { // }; -// enum bits_scyn3 { +// enum scyn3_bit { // }; -// enum bits_zmctl { +// enum zmctl_bit { // }; -// enum bits_scrctl { +// enum scrctl_bit { // }; -// enum bits_vcstau { +// enum vcstau_bit { // }; -// enum bits_vcstal { +// enum vcstal_bit { // }; -// enum bits_lsta0u { +// enum lsta0u_bit { // }; -// enum bits_lsta0l { +// enum lsta0l_bit { // }; -// enum bits_lsta1u { +// enum lsta1u_bit { // }; -// enum bits_lsta1l { +// enum lsta1l_bit { // }; -// enum bits_lctau { +// enum lctau_bit { // }; -// enum bits_lctal { +// enum lctal_bit { // }; -enum bits_bktau { +enum bktau_bit { BKTAU__BKCLMD_SINGLE_COLOR = (0 << 15), BKTAU__BKCLMD_PER_LINE = (1 << 15), }; -// enum bits_bktal { +// enum bktal_bit { // }; -// enum bits_rpmd { +// enum rpmd_bit { // }; -// enum bits_rprctl { +// enum rprctl_bit { // }; -// enum bits_ktctl { +// enum ktctl_bit { // }; -// enum bits_ktaof { +// enum ktaof_bit { // }; -// enum bits_ovpnra { +// enum ovpnra_bit { // }; -// enum bits_ovpnrb { +// enum ovpnrb_bit { // }; -// enum bits_rptau { +// enum rptau_bit { // }; -// enum bits_rptal { +// enum rptal_bit { // }; -// enum bits_wpsx0 { +// enum wpsx0_bit { // }; -// enum bits_wpsy0 { +// enum wpsy0_bit { // }; -// enum bits_wpex0 { +// enum wpex0_bit { // }; -// enum bits_wpey0 { +// enum wpey0_bit { // }; -// enum bits_wpsx1 { +// enum wpsx1_bit { // }; -// enum bits_wpsy1 { +// enum wpsy1_bit { // }; -// enum bits_wpex1 { +// enum wpex1_bit { // }; -// enum bits_wpey1 { +// enum wpey1_bit { // }; -// enum bits_wctla { +// enum wctla_bit { // }; -// enum bits_wctlb { +// enum wctlb_bit { // }; -// enum bits_wctlc { +// enum wctlc_bit { // }; -// enum bits_wctld { +// enum wctld_bit { // }; -// enum bits_lwta0u { +// enum lwta0u_bit { // }; -// enum bits_lwta0l { +// enum lwta0l_bit { // }; -// enum bits_lwta1u { +// enum lwta1u_bit { // }; -// enum bits_lwta1l { +// enum lwta1l_bit { // }; -// enum bits_spctl { +// enum spctl_bit { // }; -// enum bits_sdctl { +// enum sdctl_bit { // }; -// enum bits_craofa { +// enum craofa_bit { // }; -// enum bits_craofb { +// enum craofb_bit { // }; -// enum bits_lnclen { +// enum lnclen_bit { // }; -// enum bits_sfprmd { +// enum sfprmd_bit { // }; -// enum bits_ccctl { +// enum ccctl_bit { // }; -// enum bits_sfccmd { +// enum sfccmd_bit { // }; -// enum bits_prisa { +// enum prisa_bit { // }; -// enum bits_prisb { +// enum prisb_bit { // }; -// enum bits_prisc { +// enum prisc_bit { // }; -// enum bits_prisd { +// enum prisd_bit { // }; -// enum bits_prina { +// enum prina_bit { // }; -// enum bits_prinb { +// enum prinb_bit { // }; -// enum bits_prir { +// enum prir_bit { // }; -// enum bits_ccrsa { +// enum ccrsa_bit { // }; -// enum bits_ccrsb { +// enum ccrsb_bit { // }; -// enum bits_ccrsc { +// enum ccrsc_bit { // }; -// enum bits_ccrsd { +// enum ccrsd_bit { // }; -// enum bits_ccrna { +// enum ccrna_bit { // }; -// enum bits_ccrnb { +// enum ccrnb_bit { // }; -// enum bits_ccrr { +// enum ccrr_bit { // }; -// enum bits_ccrlb { +// enum ccrlb_bit { // }; -// enum bits_clofen { +// enum clofen_bit { // }; -// enum bits_clofsl { +// enum clofsl_bit { // }; -// enum bits_coar { +// enum coar_bit { // }; -// enum bits_coag { +// enum coag_bit { // }; -// enum bits_coab { +// enum coab_bit { // }; -// enum bits_cobr { +// enum cobr_bit { // }; -// enum bits_cobg { +// enum cobg_bit { // }; -// enum bits_cobb { +// enum cobb_bit { // };