sh2: add serial bits
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42
sh2.h
42
sh2.h
@ -110,6 +110,48 @@ extern struct sh2 sh2 __asm("sh2");
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extern reg32 sh2_vec[0xff] __asm("sh2_vec");
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enum smr_bits {
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SMR__CA__ASYNCHRONOUS_MODE = (0 << 7),
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SMR__CA__CLOCKED_SYNCHRONOUS_MODE = (1 << 7),
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SMR__CHR__EIGHT_BIT_DATA = (0 << 6),
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SMR__CHR__SEVEN_BIT_DATA = (1 << 6),
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SMR__PE__PARITY_BIT_NOT_ADDED_OR_CHECKED = (0 << 5),
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SMR__PE__PARITY_BIT_ADDED_AND_CHECKED = (1 << 5),
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SMR__OE__EVEN_PARITY = (0 << 4),
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SMR__OE__ODD_PARITY = (1 << 4),
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SMR__STOP__ONE_STOP_BIT = (0 << 3),
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SMR__STOP__TWO_STOP_BITS = (1 << 3),
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SMR__MP__DISABLED = (0 << 2),
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SMR__MP__ENABLED = (1 << 2),
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SMR__CKS__PHI_4 = (0b00 << 0),
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SMR__CKS__PHI_16 = (0b01 << 0),
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SMR__CKS__PHI_64 = (0b10 << 0),
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SMR__CKS__PHI_256 = (0b11 << 0)
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};
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enum scr_bits {
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SCR__TIE__TRANSMITTER_INTERRUPT_ENABLE = (1 << 7),
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SCR__RIE__RECEIVE_INTERRUPT_ENABLE = (1 << 6),
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SCR__TE__TRANSMITTER_ENABLE = (1 << 5),
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SCR__RE__RECEIVER_ENABLE = (1 << 4),
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SCR__MPIE__MULTIPROCESSOR_INTERRUPT_ENABLE = (1 << 3),
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SCR__TEIE__TRANSMIT_END_INTERRUPT_ENABLE = (1 << 2),
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SCR__CKE__INTERNAL_CLOCK__SCK_INPUT = (0b00 << 0),
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SCR__CKE__INTERNAL_CLOCK__SCK_OUTPUT = (0b01 << 0),
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SCR__CKE__EXTERNAL_CLOCK__SCK_INPUT = (0b10 << 0),
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};
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enum ssr_bits {
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SSR__TDRE = (1 << 7),
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SSR__RDRF = (1 << 6),
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SSR__ORER = (1 << 5),
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SSR__FER = (1 << 4),
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SSR__PER = (1 << 3),
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SSR__TEND = (1 << 2),
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SSR__MPB = (1 << 1),
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SSR__MPBT = (1 << 0),
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};
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enum tier_bits {
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TIER__ICIE = (1 << 7),
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TIER__OCIAE = (1 << 3),
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