42 lines
3.2 KiB
Plaintext
42 lines
3.2 KiB
Plaintext
Field Name Bits Default Description
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RB_BUFSZ 5:0 0x0 Ring Buffer Size. This size is expressed in log2 of the
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actual size. Values 0 and 1 are clamped to an 8 DWORD
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ring buffer. A value of 2 to 22 will give a ring buffer:
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2^(RB_BUFSZ+1). Values greater than 22 will clamp to
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22. Default = 0
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RB_BLKSZ 13:8 0x0 Ring Buffer Block Size. This defines the number of
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quadwords that the Command Processor will read
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between updates to the host`s copy of the Read Pointer.
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This size is expressed in log2 of the actual size (in 64-bit
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quadwords). For example, for a block of 1024
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quadwords, you would program this field to 10(decimal).
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Default = 0
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BUF_SWAP 17:16 0x0 Endian Swap Control for Ring Buffer and Indirect
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Buffer. Only affects the chip behavior if the buffer
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resides in system memory.
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POSSIBLE VALUES:
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00 - No swap
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01 - 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC
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02 - 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA
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03 - Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB
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MAX_FETCH 19:18 0x0 Maximum Fetch Size for any read request that the CP
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makes to memory.
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POSSIBLE VALUES:
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00 - 1 double octword. (32 bytes)
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01 - 2 double octwords. (64 bytes)
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02 - 4 double octwords. (128 bytes)
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03 - 8 double octwords. (256 bytes).
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RB_NO_UPDATE 27 0x0 Ring Buffer No Write to Read Pointer. The purpose of this
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control bit is to have a fall-back position if the bus-
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mastered write to system memory doesn`t work, in which
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case the driver will have to read the Graphics
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Controller`s copy of the Read Pointer directly, with some
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performance penalty.
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POSSIBLE VALUES:
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00 - Write to Host`s copy of Read Pointer in system memory.
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01 - Do not write to Host`s copy of Read pointer.
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RB_RPTR_WR_ENA 31 0bx0 Ring Buffer Read Pointer Write Transfer Enable. When
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set the contents of the CP_RB_RPTR_WR register is
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transferred to the active read pointer (CP_RB_RPTR)
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whenever the CP_RB_WPTR register is written.
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