35 lines
2.5 KiB
Plaintext
35 lines
2.5 KiB
Plaintext
Field Name Bits Default Description
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INDIRECT2_START 6:0 none Start location of Indirect Queue #2 in the command
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cache. This value also sets the size in double octwords of
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the Indirect Queue #1 cache that will reside in locations
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INDIRECT1_START to (INDIRECT2_START - 1). The
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Indirect Queue #2 will reside in locations
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INDIRECT2_START to 0x5f. The minimum size of the
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Indirect Queues must be at least twice the MAX_FETCH
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size as programmed in the CP_RB_CNTL register.
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INDIRECT1_START 14:8 none Start location of Indirect Queue #1 in the command
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cache. This value is also the size in double octwords of
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the Primary Queue cache that will reside in locations 0 to
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(INDIRECT1_START - 1). The minimum size of the
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Primary Queue cache must be at least twice the
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MAX_FETCH size as programmed in the
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CP_RB_CNTL register.
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CSQ_INDIRECT2_MODE 26 0x0 POSSIBLE VALUES:
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00 - PIO
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01 - BM
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CSQ_INDIRECT2_ENABLE 27 0x0 Enables Indirect Buffer #2. If this bit is set, the
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CP_CSQ_MODE register overrides the operation of the
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CSQ_MODE variable in the CP_CSQ_CNTL register.
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CSQ_INDIRECT1_MODE 28 0x0 POSSIBLE VALUES:
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00 - PIO
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01 - BM
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CSQ_INDIRECT1_ENABLE 29 0x0 Enables Indirect Buffer #1. If this bit is set, the
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CP_CSQ_MODE register overrides the operation of the
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CSQ_MODE variable in the CP_CSQ_CNTL register.
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CSQ_PRIMARY_MODE 30 0x0 POSSIBLE VALUES:
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00 - PIO
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01 - BM
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CSQ_PRIMARY_ENABLE 31 0x0 Enables Primary Buffer. If this bit is set, the
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CP_CSQ_MODE register overrides the operation of the
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CSQ_MODE variable in the CP_CSQ_CNTL register.
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