Field Name            Bits    Description
PVS_SRC_REG_TYPE      1:0     Defines the Memory Select (Register Type) for the Source Operand. See Below.
SPARE_0               2
PVS_SRC_ABS_XYZW      3       If set, Take absolute value of all 4 components of input vector.
PVS_SRC_ADDR_MODE_0   4       Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE
PVS_SRC_OFFSET        12:5    Vector Offset into selected memory (Register Type)
PVS_SRC_SWIZZLE_X     15:13   X-Component Swizzle Select. See Below
PVS_SRC_SWIZZLE_Y     18:16   Y-Component Swizzle Select. See Below
PVS_SRC_SWIZZLE_Z     21:19   Z-Component Swizzle Select. See Below
PVS_SRC_SWIZZLE_W     24:22   W-Component Swizzle Select. See Below
PVS_SRC_MODIFIER_X    25      If set, Negate X Component of input vector.
PVS_SRC_MODIFIER_Y    26      If set, Negate Y Component of input vector.
PVS_SRC_MODIFIER_Z    27      If set, Negate Z Component of input vector.
PVS_SRC_MODIFIER_W    28      If set, Negate W Component of input vector.
PVS_SRC_ADDR_SEL      30:29   When PVS_SRC_ADDR_MODE is set, this selects which component of the 4-component address register to use.
PVS_SRC_ADDR_MODE_1   31      Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE