GEN_INT_STATUS
DISPDEC:0x104
2-339
VGA_RENDER_CONTROL
DISPDEC:0x300
2-186
VGA_SEQUENCER_RESET_CONTROL
DISPDEC:0x304
2-187
VGA_MODE_CONTROL
DISPDEC:0x308
2-187
VGA_SURFACE_PITCH_SELECT
DISPDEC:0x30C
2-187
VGA_MEMORY_BASE_ADDRESS
DISPDEC:0x310
2-188
VGA_DISPBUF1_SURFACE_ADDR
DISPDEC:0x318
2-188
VGA_DISPBUF2_SURFACE_ADDR
DISPDEC:0x320
2-188
VGA_HDP_CONTROL
DISPDEC:0x328
2-188
VGA_CACHE_CONTROL
DISPDEC:0x32C
2-189
D1VGA_CONTROL
DISPDEC:0x330
2-189
D2VGA_CONTROL
DISPDEC:0x338
2-190
VGA_STATUS
DISPDEC:0x340
2-190
VGA_INTERRUPT_CONTROL
DISPDEC:0x344
2-191
VGA_STATUS_CLEAR
DISPDEC:0x348
2-191
VGA_INTERRUPT_STATUS
DISPDEC:0x34C
2-191
VGA_MAIN_CONTROL
DISPDEC:0x350
2-192
VGA_TEST_CONTROL
DISPDEC:0x354
2-193
VGA_DEBUG_READBACK_INDEX
DISPDEC:0x358
2-193
VGA_DEBUG_READBACK_DATA
DISPDEC:0x35C
2-194
VGA_MEM_WRITE_PAGE_ADDR
DISPDEC:0x38
2-197
CRTC8_IDX
DISPDEC:0x3B4
2-171
CRTC8_IDX
DISPDEC:0x3B4
2-196
CRTC8_DATA
DISPDEC:0x3B5
2-171
CRTC8_DATA
DISPDEC:0x3B5
2-196
GENFC_WT
DISPDEC:0x3BA
2-165
GENS1
DISPDEC:0x3BA
2-167
VGA_MEM_READ_PAGE_ADDR
DISPDEC:0x3C
2-197
ATTRDW
DISPDEC:0x3C0
2-181
ATTRX
DISPDEC:0x3C0
2-181
ATTRDR
DISPDEC:0x3C1
2-181
GENMO_WT
DISPDEC:0x3C2
2-165
GENMO_WT
DISPDEC:0x3C2
2-194
GENS0
DISPDEC:0x3C2
2-166
SEQ8_IDX
DISPDEC:0x3C4
2-170
SEQ8_IDX
DISPDEC:0x3C4
2-195
SEQ8_DATA
DISPDEC:0x3C5
2-170
SEQ8_DATA
DISPDEC:0x3C5
2-195
DAC_MASK
DISPDEC:0x3C6
2-168
DAC_R_INDEX
DISPDEC:0x3C7
2-168
DAC_W_INDEX
DISPDEC:0x3C8
2-168
DAC_DATA
DISPDEC:0x3C9
2-168
GENFC_RD
DISPDEC:0x3CA
2-165
GENMO_RD
DISPDEC:0x3CC
2-166
GENMO_RD
DISPDEC:0x3CC
2-195
GRPH8_IDX
DISPDEC:0x3CE
2-178
GRPH8_IDX
DISPDEC:0x3CE
2-196
GRPH8_DATA
DISPDEC:0x3CF
2-178
GRPH8_DATA
DISPDEC:0x3CF
2-196
D1CRTC_H_TOTAL
DISPDEC:0x6000
2-267
D1CRTC_H_BLANK_START_END
DISPDEC:0x6004
2-267
D1CRTC_H_SYNC_A
DISPDEC:0x6008
2-267
D1CRTC_H_SYNC_A_CNTL
DISPDEC:0x600C
2-267
D1CRTC_H_SYNC_B
DISPDEC:0x6010
2-268
D1CRTC_H_SYNC_B_CNTL
DISPDEC:0x6014
2-268
D1CRTC_V_TOTAL
DISPDEC:0x6020
2-268
D1CRTC_V_BLANK_START_END
DISPDEC:0x6024
2-268
D1CRTC_V_SYNC_A
DISPDEC:0x6028
2-269
D1CRTC_V_SYNC_A_CNTL
DISPDEC:0x602C
2-269
D1CRTC_V_SYNC_B
DISPDEC:0x6030
2-269
D1CRTC_V_SYNC_B_CNTL
DISPDEC:0x6034
2-269
D1CRTC_TRIGA_CNTL
DISPDEC:0x6060
2-270
D1CRTC_TRIGA_MANUAL_TRIG
DISPDEC:0x6064
2-271
D1CRTC_TRIGB_CNTL
DISPDEC:0x6068
2-271
D1CRTC_TRIGB_MANUAL_TRIG
DISPDEC:0x606C
2-272
D1CRTC_FORCE_COUNT_NOW_CNTL
DISPDEC:0x6070
2-272
D1CRTC_FLOW_CONTROL
DISPDEC:0x6074
2-272
D1CRTC_PIXEL_DATA_READBACK
DISPDEC:0x6078
2-273
D1CRTC_STEREO_FORCE_NEXT_EYE
DISPDEC:0x607C
2-273
D1CRTC_CONTROL
DISPDEC:0x6080
2-273
D1CRTC_BLANK_CONTROL
DISPDEC:0x6084
2-274
D1CRTC_INTERLACE_CONTROL
DISPDEC:0x6088
2-274
D1CRTC_INTERLACE_STATUS
DISPDEC:0x608C
2-274
D1CRTC_BLANK_DATA_COLOR
DISPDEC:0x6090
2-275
D1CRTC_OVERSCAN_COLOR
DISPDEC:0x6094
2-275
D1CRTC_BLACK_COLOR
DISPDEC:0x6098
2-275
D1CRTC_STATUS
DISPDEC:0x609C
2-275
D1CRTC_STATUS_POSITION
DISPDEC:0x60A0
2-276
D1CRTC_STATUS_FRAME_COUNT
DISPDEC:0x60A4
2-276
D1CRTC_STATUS_VF_COUNT
DISPDEC:0x60A8
2-276
D1CRTC_STATUS_HV_COUNT
DISPDEC:0x60AC
2-276
D1CRTC_COUNT_RESET
DISPDEC:0x60B0
2-276
D1CRTC_COUNT_CONTROL
DISPDEC:0x60B4
2-276
D1CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
DISPDEC:0x60B8
2-276
D1CRTC_VERT_SYNC_CONTROL
DISPDEC:0x60BC
2-277
D1CRTC_STEREO_STATUS
DISPDEC:0x60C0
2-277
D1CRTC_STEREO_CONTROL
DISPDEC:0x60C4
2-277
D1CRTC_SNAPSHOT_STATUS
DISPDEC:0x60C8
2-278
D1CRTC_SNAPSHOT_CONTROL
DISPDEC:0x60CC
2-278
D1CRTC_SNAPSHOT_POSITION
DISPDEC:0x60D0
2-278
D1CRTC_SNAPSHOT_FRAME
DISPDEC:0x60D4
2-278
D1CRTC_START_LINE_CONTROL
DISPDEC:0x60D8
2-278
D1CRTC_INTERRUPT_CONTROL
DISPDEC:0x60DC
2-278
D1MODE_MASTER_UPDATE_LOCK
DISPDEC:0x60E0
2-279
D1MODE_MASTER_UPDATE_MODE
DISPDEC:0x60E4
2-279
D1CRTC_UPDATE_LOCK
DISPDEC:0x60E8
2-279
D1CRTC_DOUBLE_BUFFER_CONTROL
DISPDEC:0x60EC
2-280
D1CRTC_VGA_PARAMETER_CAPTURE_MODE
DISPDEC:0x60F0
2-280
DC_CRTC_MASTER_EN
DISPDEC:0x60F8
2-280
DC_CRTC_TV_CONTROL
DISPDEC:0x60FC
2-280
D1GRPH_ENABLE
DISPDEC:0x6100
2-198
D1GRPH_CONTROL
DISPDEC:0x6104
2-198
D1GRPH_LUT_SEL
DISPDEC:0x6108
2-199
D1GRPH_PRIMARY_SURFACE_ADDRESS
DISPDEC:0x6110
2-199
D1GRPH_SECONDARY_SURFACE_ADDRESS
DISPDEC:0x6118
2-200
D1GRPH_PITCH
DISPDEC:0x6120
2-200
D1GRPH_SURFACE_OFFSET_X
DISPDEC:0x6124
2-200
D1GRPH_SURFACE_OFFSET_Y
DISPDEC:0x6128
2-200
D1GRPH_X_START
DISPDEC:0x612C
2-200
D1GRPH_Y_START
DISPDEC:0x6130
2-201
D1GRPH_X_END
DISPDEC:0x6134
2-201
D1GRPH_Y_END
DISPDEC:0x6138
2-201
D1COLOR_SPACE_CONVERT
DISPDEC:0x613C
2-221
D1OVL_COLOR_MATRIX_TRANSFORMATION_CNTL
DISPDEC:0x6140
2-217
D1GRPH_UPDATE
DISPDEC:0x6144
2-201
D1GRPH_FLIP_CONTROL
DISPDEC:0x6148
2-202
D1GRPH_SURFACE_ADDRESS_INUSE
DISPDEC:0x614C
2-202
D1OVL_ENABLE
DISPDEC:0x6180
2-203
D1OVL_CONTROL1
DISPDEC:0x6184
2-203
D1OVL_CONTROL2
DISPDEC:0x6188
2-203
D1OVL_SURFACE_ADDRESS
DISPDEC:0x6190
2-204
D1OVL_PITCH
DISPDEC:0x6198
2-204
D1OVL_SURFACE_OFFSET_X
DISPDEC:0x619C
2-204
D1OVL_SURFACE_OFFSET_Y
DISPDEC:0x61A0
2-204
D1OVL_START
DISPDEC:0x61A4
2-204
D1OVL_END
DISPDEC:0x61A8
2-205
D1OVL_UPDATE
DISPDEC:0x61AC
2-205
D1OVL_SURFACE_ADDRESS_INUSE
DISPDEC:0x61B0
2-205
D1OVL_MATRIX_TRANSFORM_EN
DISPDEC:0x6200
2-206
D1OVL_MATRIX_COEF_1_1
DISPDEC:0x6204
2-206
D1OVL_MATRIX_COEF_1_2
DISPDEC:0x6208
2-206
D1OVL_MATRIX_COEF_1_3
DISPDEC:0x620C
2-206
D1OVL_MATRIX_COEF_1_4
DISPDEC:0x6210
2-206
D1OVL_MATRIX_COEF_2_1
DISPDEC:0x6214
2-207
D1OVL_MATRIX_COEF_2_2
DISPDEC:0x6218
2-207
D1OVL_MATRIX_COEF_2_3
DISPDEC:0x621C
2-207
D1OVL_MATRIX_COEF_2_4
DISPDEC:0x6220
2-207
D1OVL_MATRIX_COEF_3_1
DISPDEC:0x6224
2-207
D1OVL_MATRIX_COEF_3_2
DISPDEC:0x6228
2-208
D1OVL_MATRIX_COEF_3_3
DISPDEC:0x622C
2-208
D1OVL_MATRIX_COEF_3_4
DISPDEC:0x6230
2-208
D1OVL_PWL_TRANSFORM_EN
DISPDEC:0x6280
2-209
D1OVL_PWL_0TOF
DISPDEC:0x6284
2-209
D1OVL_PWL_10TO1F
DISPDEC:0x6288
2-209
D1OVL_PWL_20TO3F
DISPDEC:0x628C
2-209
D1OVL_PWL_40TO7F
DISPDEC:0x6290
2-209
D1OVL_PWL_80TOBF
DISPDEC:0x6294
2-210
D1OVL_PWL_C0TOFF
DISPDEC:0x6298
2-210
D1OVL_PWL_100TO13F
DISPDEC:0x629C
2-210
D1OVL_PWL_140TO17F
DISPDEC:0x62A0
2-210
D1OVL_PWL_180TO1BF
DISPDEC:0x62A4
2-210
D1OVL_PWL_1C0TO1FF
DISPDEC:0x62A8
2-210
D1OVL_PWL_200TO23F
DISPDEC:0x62AC
2-211
D1OVL_PWL_240TO27F
DISPDEC:0x62B0
2-211
D1OVL_PWL_280TO2BF
DISPDEC:0x62B4
2-211
D1OVL_PWL_2C0TO2FF
DISPDEC:0x62B8
2-211
D1OVL_PWL_300TO33F
DISPDEC:0x62BC
2-211
D1OVL_PWL_340TO37F
DISPDEC:0x62C0
2-212
D1OVL_PWL_380TO3BF
DISPDEC:0x62C4
2-212
D1OVL_PWL_3C0TO3FF
DISPDEC:0x62C8
2-212
D1OVL_KEY_CONTROL
DISPDEC:0x6300
2-213
D1GRPH_ALPHA
DISPDEC:0x6304
2-213
D1OVL_ALPHA
DISPDEC:0x6308
2-213
D1OVL_ALPHA_CONTROL
DISPDEC:0x630C
2-214
D1GRPH_KEY_RANGE_RED
DISPDEC:0x6310
2-214
D1GRPH_KEY_RANGE_GREEN
DISPDEC:0x6314
2-214
D1GRPH_KEY_RANGE_BLUE
DISPDEC:0x6318
2-215
D1GRPH_KEY_RANGE_ALPHA
DISPDEC:0x631C
2-215
D1OVL_KEY_RANGE_RED_CR
DISPDEC:0x6320
2-215
D1OVL_KEY_RANGE_GREEN_Y
DISPDEC:0x6324
2-215
D1OVL_KEY_RANGE_BLUE_CB
DISPDEC:0x6328
2-216
D1OVL_KEY_ALPHA
DISPDEC:0x632C
2-216
D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL
DISPDEC:0x6380
2-217
D1COLOR_MATRIX_COEF_1_1
DISPDEC:0x6384
2-217
D1COLOR_MATRIX_COEF_1_2
DISPDEC:0x6388
2-217
D1COLOR_MATRIX_COEF_1_3
DISPDEC:0x638C
2-218
D1COLOR_MATRIX_COEF_1_4
DISPDEC:0x6390
2-218
D1COLOR_MATRIX_COEF_2_1
DISPDEC:0x6394
2-218
D1COLOR_MATRIX_COEF_2_2
DISPDEC:0x6398
2-218
D1COLOR_MATRIX_COEF_2_3
DISPDEC:0x639C
2-218
D1COLOR_MATRIX_COEF_2_4
DISPDEC:0x63A0
2-219
D1COLOR_MATRIX_COEF_3_1
DISPDEC:0x63A4
2-219
D1COLOR_MATRIX_COEF_3_2
DISPDEC:0x63A8
2-219
D1COLOR_MATRIX_COEF_3_3
DISPDEC:0x63AC
2-219
D1COLOR_MATRIX_COEF_3_4
DISPDEC:0x63B0
2-220
D1CUR_CONTROL
DISPDEC:0x6400
2-222
D1CUR_SURFACE_ADDRESS
DISPDEC:0x6408
2-222
D1CUR_SIZE
DISPDEC:0x6410
2-222
D1CUR_POSITION
DISPDEC:0x6414
2-222
D1CUR_HOT_SPOT
DISPDEC:0x6418
2-223
D1CUR_COLOR1
DISPDEC:0x641C
2-223
D1CUR_COLOR2
DISPDEC:0x6420
2-223
D1CUR_UPDATE
DISPDEC:0x6424
2-223
D1ICON_CONTROL
DISPDEC:0x6440
2-224
D1ICON_SURFACE_ADDRESS
DISPDEC:0x6448
2-224
D1ICON_SIZE
DISPDEC:0x6450
2-224
D1ICON_START_POSITION
DISPDEC:0x6454
2-224
D1ICON_COLOR1
DISPDEC:0x6458
2-224
D1ICON_COLOR2
DISPDEC:0x645C
2-225
D1ICON_UPDATE
DISPDEC:0x6460
2-225
DC_LUT_RW_SELECT
DISPDEC:0x6480
2-226
DC_LUT_RW_MODE
DISPDEC:0x6484
2-226
DC_LUT_RW_INDEX
DISPDEC:0x6488
2-226
DC_LUT_SEQ_COLOR
DISPDEC:0x648C
2-226
DC_LUT_PWL_DATA
DISPDEC:0x6490
2-226
DC_LUT_30_COLOR
DISPDEC:0x6494
2-227
DC_LUT_READ_PIPE_SELECT
DISPDEC:0x6498
2-227
DC_LUT_WRITE_EN_MASK
DISPDEC:0x649C
2-227
DC_LUT_AUTOFILL
DISPDEC:0x64A0
2-227
DC_LUTA_CONTROL
DISPDEC:0x64C0
2-228
DC_LUTA_BLACK_OFFSET_BLUE
DISPDEC:0x64C4
2-229
DC_LUTA_BLACK_OFFSET_GREEN
DISPDEC:0x64C8
2-229
DC_LUTA_BLACK_OFFSET_RED
DISPDEC:0x64CC
2-229
DC_LUTA_WHITE_OFFSET_BLUE
DISPDEC:0x64D0
2-230
DC_LUTA_WHITE_OFFSET_GREEN
DISPDEC:0x64D4
2-230
DC_LUTA_WHITE_OFFSET_RED
DISPDEC:0x64D8
2-230
D2CRTC_H_TOTAL
DISPDEC:0x6800
2-280
D2CRTC_H_BLANK_START_END
DISPDEC:0x6804
2-281
D2CRTC_H_SYNC_A
DISPDEC:0x6808
2-281
D2CRTC_H_SYNC_A_CNTL
DISPDEC:0x680C
2-281
D2CRTC_H_SYNC_B
DISPDEC:0x6810
2-281
D2CRTC_H_SYNC_B_CNTL
DISPDEC:0x6814
2-282
D2CRTC_V_TOTAL
DISPDEC:0x6820
2-282
D2CRTC_V_BLANK_START_END
DISPDEC:0x6824
2-282
D2CRTC_V_SYNC_A
DISPDEC:0x6828
2-282
D2CRTC_V_SYNC_A_CNTL
DISPDEC:0x682C
2-283
D2CRTC_V_SYNC_B
DISPDEC:0x6830
2-283
D2CRTC_V_SYNC_B_CNTL
DISPDEC:0x6834
2-283
D2CRTC_TRIGA_CNTL
DISPDEC:0x6860
2-283
D2CRTC_TRIGA_MANUAL_TRIG
DISPDEC:0x6864
2-284
D2CRTC_TRIGB_CNTL
DISPDEC:0x6868
2-285
D2CRTC_TRIGB_MANUAL_TRIG
DISPDEC:0x686C
2-286
D2CRTC_FORCE_COUNT_NOW_CNTL
DISPDEC:0x6870
2-286
D2CRTC_FLOW_CONTROL
DISPDEC:0x6874
2-286
D2CRTC_PIXEL_DATA_READBACK
DISPDEC:0x6878
2-287
D2CRTC_STEREO_FORCE_NEXT_EYE
DISPDEC:0x687C
2-287
D2CRTC_CONTROL
DISPDEC:0x6880
2-287
D2CRTC_BLANK_CONTROL
DISPDEC:0x6884
2-287
D2CRTC_INTERLACE_CONTROL
DISPDEC:0x6888
2-288
D2CRTC_INTERLACE_STATUS
DISPDEC:0x688C
2-288
D2CRTC_BLANK_DATA_COLOR
DISPDEC:0x6890
2-288
D2CRTC_OVERSCAN_COLOR
DISPDEC:0x6894
2-288
D2CRTC_BLACK_COLOR
DISPDEC:0x6898
2-289
D2CRTC_STATUS
DISPDEC:0x689C
2-289
D2CRTC_STATUS_POSITION
DISPDEC:0x68A0
2-289
D2CRTC_STATUS_FRAME_COUNT
DISPDEC:0x68A4
2-290
D2CRTC_STATUS_VF_COUNT
DISPDEC:0x68A8
2-290
D2CRTC_STATUS_HV_COUNT
DISPDEC:0x68AC
2-290
D2CRTC_COUNT_RESET
DISPDEC:0x68B0
2-290
D2CRTC_COUNT_CONTROL
DISPDEC:0x68B4
2-290
D2CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE
DISPDEC:0x68B8
2-290
D2CRTC_VERT_SYNC_CONTROL
DISPDEC:0x68BC
2-290
D2CRTC_STEREO_STATUS
DISPDEC:0x68C0
2-291
D2CRTC_STEREO_CONTROL
DISPDEC:0x68C4
2-291
D2CRTC_SNAPSHOT_STATUS
DISPDEC:0x68C8
2-291
D2CRTC_SNAPSHOT_CONTROL
DISPDEC:0x68CC
2-292
D2CRTC_SNAPSHOT_POSITION
DISPDEC:0x68D0
2-292
D2CRTC_SNAPSHOT_FRAME
DISPDEC:0x68D4
2-292
D2CRTC_START_LINE_CONTROL
DISPDEC:0x68D8
2-292
D2CRTC_INTERRUPT_CONTROL
DISPDEC:0x68DC
2-292
D2MODE_MASTER_UPDATE_LOCK
DISPDEC:0x68E0
2-293
D2MODE_MASTER_UPDATE_MODE
DISPDEC:0x68E4
2-293
D2CRTC_UPDATE_LOCK
DISPDEC:0x68E8
2-293
D2CRTC_DOUBLE_BUFFER_CONTROL
DISPDEC:0x68EC
2-293
D2CRTC_VGA_PARAMETER_CAPTURE_MODE
DISPDEC:0x68F0
2-294
D2GRPH_ENABLE
DISPDEC:0x6900
2-231
D2GRPH_CONTROL
DISPDEC:0x6904
2-231
D2GRPH_LUT_SEL
DISPDEC:0x6908
2-232
D2GRPH_PRIMARY_SURFACE_ADDRESS
DISPDEC:0x6910
2-232
D2GRPH_SECONDARY_SURFACE_ADDRESS
DISPDEC:0x6918
2-233
D2GRPH_PITCH
DISPDEC:0x6920
2-233
D2GRPH_SURFACE_OFFSET_X
DISPDEC:0x6924
2-233
D2GRPH_SURFACE_OFFSET_Y
DISPDEC:0x6928
2-233
D2GRPH_X_START
DISPDEC:0x692C
2-233
D2GRPH_Y_START
DISPDEC:0x6930
2-234
D2GRPH_X_END
DISPDEC:0x6934
2-234
D2GRPH_Y_END
DISPDEC:0x6938
2-234
D2COLOR_SPACE_CONVERT
DISPDEC:0x693C
2-254
D2OVL_COLOR_MATRIX_TRANSFORMATION_CNTL
DISPDEC:0x6940
2-250
D2GRPH_UPDATE
DISPDEC:0x6944
2-234
D2GRPH_FLIP_CONTROL
DISPDEC:0x6948
2-235
D2GRPH_SURFACE_ADDRESS_INUSE
DISPDEC:0x694C
2-235
D2OVL_ENABLE
DISPDEC:0x6980
2-236
D2OVL_CONTROL1
DISPDEC:0x6984
2-236
D2OVL_CONTROL2
DISPDEC:0x6988
2-236
D2OVL_SURFACE_ADDRESS
DISPDEC:0x6990
2-237
D2OVL_PITCH
DISPDEC:0x6998
2-237
D2OVL_SURFACE_OFFSET_X
DISPDEC:0x699C
2-237
D2OVL_SURFACE_OFFSET_Y
DISPDEC:0x69A0
2-237
D2OVL_START
DISPDEC:0x69A4
2-237
D2OVL_END
DISPDEC:0x69A8
2-238
D2OVL_UPDATE
DISPDEC:0x69AC
2-238
D2OVL_SURFACE_ADDRESS_INUSE
DISPDEC:0x69B0
2-238
D2OVL_MATRIX_TRANSFORM_EN
DISPDEC:0x6A00
2-239
D2OVL_MATRIX_COEF_1_1
DISPDEC:0x6A04
2-239
D2OVL_MATRIX_COEF_1_2
DISPDEC:0x6A08
2-239
D2OVL_MATRIX_COEF_1_3
DISPDEC:0x6A0C
2-239
D2OVL_MATRIX_COEF_1_4
DISPDEC:0x6A10
2-239
D2OVL_MATRIX_COEF_2_1
DISPDEC:0x6A14
2-240
D2OVL_MATRIX_COEF_2_2
DISPDEC:0x6A18
2-240
D2OVL_MATRIX_COEF_2_3
DISPDEC:0x6A1C
2-240
D2OVL_MATRIX_COEF_2_4
DISPDEC:0x6A20
2-240
D2OVL_MATRIX_COEF_3_1
DISPDEC:0x6A24
2-240
D2OVL_MATRIX_COEF_3_2
DISPDEC:0x6A28
2-241
D2OVL_MATRIX_COEF_3_3
DISPDEC:0x6A2C
2-241
D2OVL_MATRIX_COEF_3_4
DISPDEC:0x6A30
2-241
D2OVL_PWL_TRANSFORM_EN
DISPDEC:0x6A80
2-242
D2OVL_PWL_0TOF
DISPDEC:0x6A84
2-242
D2OVL_PWL_10TO1F
DISPDEC:0x6A88
2-242
D2OVL_PWL_20TO3F
DISPDEC:0x6A8C
2-242
D2OVL_PWL_40TO7F
DISPDEC:0x6A90
2-242
D2OVL_PWL_80TOBF
DISPDEC:0x6A94
2-243
D2OVL_PWL_C0TOFF
DISPDEC:0x6A98
2-243
D2OVL_PWL_100TO13F
DISPDEC:0x6A9C
2-243
D2OVL_PWL_140TO17F
DISPDEC:0x6AA0
2-243
D2OVL_PWL_180TO1BF
DISPDEC:0x6AA4
2-243
D2OVL_PWL_1C0TO1FF
DISPDEC:0x6AA8
2-243
D2OVL_PWL_200TO23F
DISPDEC:0x6AAC
2-244
D2OVL_PWL_240TO27F
DISPDEC:0x6AB0
2-244
D2OVL_PWL_280TO2BF
DISPDEC:0x6AB4
2-244
D2OVL_PWL_2C0TO2FF
DISPDEC:0x6AB8
2-244
D2OVL_PWL_300TO33F
DISPDEC:0x6ABC
2-244
D2OVL_PWL_340TO37F
DISPDEC:0x6AC0
2-245
D2OVL_PWL_380TO3BF
DISPDEC:0x6AC4
2-245
D2OVL_PWL_3C0TO3FF
DISPDEC:0x6AC8
2-245
D2OVL_KEY_CONTROL
DISPDEC:0x6B00
2-246
D2GRPH_ALPHA
DISPDEC:0x6B04
2-246
D2OVL_ALPHA
DISPDEC:0x6B08
2-246
D2OVL_ALPHA_CONTROL
DISPDEC:0x6B0C
2-247
D2GRPH_KEY_RANGE_RED
DISPDEC:0x6B10
2-247
D2GRPH_KEY_RANGE_GREEN
DISPDEC:0x6B14
2-247
D2GRPH_KEY_RANGE_BLUE
DISPDEC:0x6B18
2-248
D2GRPH_KEY_RANGE_ALPHA
DISPDEC:0x6B1C
2-248
D2OVL_KEY_RANGE_RED_CR
DISPDEC:0x6B20
2-248
D2OVL_KEY_RANGE_GREEN_Y
DISPDEC:0x6B24
2-248
D2OVL_KEY_RANGE_BLUE_CB
DISPDEC:0x6B28
2-248
D2OVL_KEY_ALPHA
DISPDEC:0x6B2C
2-249
D2GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL
DISPDEC:0x6B80
2-250
D2COLOR_MATRIX_COEF_1_1
DISPDEC:0x6B84
2-250
D2COLOR_MATRIX_COEF_1_2
DISPDEC:0x6B88
2-250
D2COLOR_MATRIX_COEF_1_3
DISPDEC:0x6B8C
2-250
D2COLOR_MATRIX_COEF_1_4
DISPDEC:0x6B90
2-251
D2COLOR_MATRIX_COEF_2_1
DISPDEC:0x6B94
2-251
D2COLOR_MATRIX_COEF_2_2
DISPDEC:0x6B98
2-251
D2COLOR_MATRIX_COEF_2_3
DISPDEC:0x6B9C
2-251
D2COLOR_MATRIX_COEF_2_4
DISPDEC:0x6BA0
2-252
D2COLOR_MATRIX_COEF_3_1
DISPDEC:0x6BA4
2-252
D2COLOR_MATRIX_COEF_3_2
DISPDEC:0x6BA8
2-252
D2COLOR_MATRIX_COEF_3_3
DISPDEC:0x6BAC
2-252
D2COLOR_MATRIX_COEF_3_4
DISPDEC:0x6BB0
2-253
D2CUR_CONTROL
DISPDEC:0x6C00
2-255
D2CUR_SURFACE_ADDRESS
DISPDEC:0x6C08
2-255
D2CUR_SIZE
DISPDEC:0x6C10
2-255
D2CUR_POSITION
DISPDEC:0x6C14
2-255
D2CUR_HOT_SPOT
DISPDEC:0x6C18
2-256
D2CUR_COLOR1
DISPDEC:0x6C1C
2-256
D2CUR_COLOR2
DISPDEC:0x6C20
2-256
D2CUR_UPDATE
DISPDEC:0x6C24
2-256
D2ICON_CONTROL
DISPDEC:0x6C40
2-257
D2ICON_SURFACE_ADDRESS
DISPDEC:0x6C48
2-257
D2ICON_SIZE
DISPDEC:0x6C50
2-257
D2ICON_START_POSITION
DISPDEC:0x6C54
2-257
D2ICON_COLOR1
DISPDEC:0x6C58
2-257
D2ICON_COLOR2
DISPDEC:0x6C5C
2-258
D2ICON_UPDATE
DISPDEC:0x6C60
2-258
DCP_CRC_CONTROL
DISPDEC:0x6C80
2-262
DCP_CRC_MASK
DISPDEC:0x6C84
2-262
DCP_CRC_P0_CURRENT
DISPDEC:0x6C88
2-262
DCP_CRC_P1_CURRENT
DISPDEC:0x6C8C
2-262
DCP_CRC_P0_LAST
DISPDEC:0x6C90
2-262
DCP_CRC_P1_LAST
DISPDEC:0x6C94
2-263
DMIF_CONTROL
DISPDEC:0x6CB0
2-264
DMIF_STATUS
DISPDEC:0x6CB4
2-264
MCIF_CONTROL
DISPDEC:0x6CB8
2-265
DCP_LB_DATA_GAP_BETWEEN_CHUNK
DISPDEC:0x6CBC
2-266
DC_LUTB_CONTROL
DISPDEC:0x6CC0
2-259
DC_LUTB_BLACK_OFFSET_BLUE
DISPDEC:0x6CC4
2-260
DC_LUTB_BLACK_OFFSET_GREEN
DISPDEC:0x6CC8
2-260
DC_LUTB_BLACK_OFFSET_RED
DISPDEC:0x6CCC
2-260
DC_LUTB_WHITE_OFFSET_BLUE
DISPDEC:0x6CD0
2-261
DC_LUTB_WHITE_OFFSET_GREEN
DISPDEC:0x6CD4
2-261
DC_LUTB_WHITE_OFFSET_RED
DISPDEC:0x6CD8
2-261
DACA_ENABLE
DISPDEC:0x7800
2-295
DACA_SOURCE_SELECT
DISPDEC:0x7804
2-295
DACA_CRC_EN
DISPDEC:0x7808
2-295
DACA_CRC_CONTROL
DISPDEC:0x780C
2-295
DACA_CRC_SIG_RGB_MASK
DISPDEC:0x7810
2-295
DACA_CRC_SIG_CONTROL_MASK
DISPDEC:0x7814
2-296
DACA_CRC_SIG_RGB
DISPDEC:0x7818
2-296
DACA_CRC_SIG_CONTROL
DISPDEC:0x781C
2-296
DACA_SYNC_TRISTATE_CONTROL
DISPDEC:0x7820
2-296
DACA_SYNC_SELECT
DISPDEC:0x7824
2-296
DACA_AUTODETECT_CONTROL
DISPDEC:0x7828
2-297
DACA_AUTODETECT_CONTROL2
DISPDEC:0x782C
2-297
DACA_AUTODETECT_STATUS
DISPDEC:0x7834
2-297
DACA_AUTODETECT_INT_CONTROL
DISPDEC:0x7838
2-298
DACA_FORCE_OUTPUT_CNTL
DISPDEC:0x783C
2-298
DACA_FORCE_DATA
DISPDEC:0x7840
2-298
DACA_POWERDOWN
DISPDEC:0x7850
2-298
DACA_CONTROL1
DISPDEC:0x7854
2-298
DACA_CONTROL2
DISPDEC:0x7858
2-299
DACA_COMPARATOR_ENABLE
DISPDEC:0x785C
2-299
DACA_COMPARATOR_OUTPUT
DISPDEC:0x7860
2-300
DACA_TEST_ENABLE
DISPDEC:0x7864
2-300
DACA_PWR_CNTL
DISPDEC:0x7868
2-300
TMDSA_CNTL
DISPDEC:0x7880
2-306
TMDSA_SOURCE_SELECT
DISPDEC:0x7884
2-306
TMDSA_COLOR_FORMAT
DISPDEC:0x7888
2-307
TMDSA_FORCE_OUTPUT_CNTL
DISPDEC:0x788C
2-307
TMDSA_FORCE_DATA
DISPDEC:0x7890
2-307
TMDSA_BIT_DEPTH_CONTROL
DISPDEC:0x7894
2-307
TMDSA_CONTROL_CHAR
DISPDEC:0x7898
2-308
TMDSA_CONTROL0_FEEDBACK
DISPDEC:0x789C
2-308
TMDSA_STEREOSYNC_CTL_SEL
DISPDEC:0x78A0
2-308
TMDSA_SYNC_CHAR_PATTERN_SEL
DISPDEC:0x78A4
2-308
TMDSA_SYNC_CHAR_PATTERN_0_1
DISPDEC:0x78A8
2-308
TMDSA_SYNC_CHAR_PATTERN_2_3
DISPDEC:0x78AC
2-309
TMDSA_CRC_CNTL
DISPDEC:0x78B0
2-309
TMDSA_CRC_SIG_MASK
DISPDEC:0x78B4
2-309
TMDSA_CRC_SIG_RGB
DISPDEC:0x78B8
2-309
TMDSA_2ND_CRC_RESULT
DISPDEC:0x78BC
2-310
TMDSA_TEST_PATTERN
DISPDEC:0x78C0
2-310
TMDSA_RANDOM_PATTERN_SEED
DISPDEC:0x78C4
2-310
TMDSA_DEBUG
DISPDEC:0x78C8
2-311
TMDSA_CTL_BITS
DISPDEC:0x78CC
2-311
TMDSA_DCBALANCER_CONTROL
DISPDEC:0x78D0
2-311
TMDSA_RED_BLUE_SWITCH
DISPDEC:0x78D4
2-311
TMDSA_DATA_SYNCHRONIZATION
DISPDEC:0x78D8
2-311
TMDSA_CTL0_1_GEN_CNTL
DISPDEC:0x78DC
2-312
TMDSA_CTL2_3_GEN_CNTL
DISPDEC:0x78E0
2-313
TMDSA_TRANSMITTER_ENABLE
DISPDEC:0x7904
2-314
TMDSA_LOAD_DETECT
DISPDEC:0x7908
2-315
TMDSA_MACRO_CONTROL
DISPDEC:0x790C
2-315
TMDSA_TRANSMITTER_CONTROL
DISPDEC:0x7910
2-315
TMDSA_REG_TEST_OUTPUT
DISPDEC:0x7914
2-316
TMDSA_TRANSMITTER_DEBUG
DISPDEC:0x7918
2-316
DVOA_ENABLE
DISPDEC:0x7980
2-316
DVOA_SOURCE_SELECT
DISPDEC:0x7984
2-317
DVOA_BIT_DEPTH_CONTROL
DISPDEC:0x7988
2-317
DVOA_OUTPUT
DISPDEC:0x798C
2-317
DVOA_CONTROL
DISPDEC:0x7990
2-318
DVOA_CRC_EN
DISPDEC:0x7994
2-318
DVOA_CRC_CONTROL
DISPDEC:0x7998
2-318
DVOA_CRC_SIG_MASK1
DISPDEC:0x799C
2-319
DVOA_CRC_SIG_MASK2
DISPDEC:0x79A0
2-319
DVOA_CRC_SIG_RESULT1
DISPDEC:0x79A4
2-319
DVOA_CRC_SIG_RESULT2
DISPDEC:0x79A8
2-319
DVOA_CRC2_SIG_MASK
DISPDEC:0x79AC
2-319
DVOA_CRC2_SIG_RESULT
DISPDEC:0x79B0
2-319
DVOA_STRENGTH_CONTROL
DISPDEC:0x79B4
2-320
DVOA_FORCE_OUTPUT_CNTL
DISPDEC:0x79B8
2-320
DVOA_FORCE_DATA
DISPDEC:0x79BC
2-320
DACB_ENABLE
DISPDEC:0x7A00
2-300
DACB_SOURCE_SELECT
DISPDEC:0x7A04
2-300
DACB_CRC_EN
DISPDEC:0x7A08
2-301
DACB_CRC_CONTROL
DISPDEC:0x7A0C
2-301
DACB_CRC_SIG_RGB_MASK
DISPDEC:0x7A10
2-301
DACB_CRC_SIG_CONTROL_MASK
DISPDEC:0x7A14
2-301
DACB_CRC_SIG_RGB
DISPDEC:0x7A18
2-301
DACB_CRC_SIG_CONTROL
DISPDEC:0x7A1C
2-302
DACB_SYNC_TRISTATE_CONTROL
DISPDEC:0x7A20
2-302
DACB_SYNC_SELECT
DISPDEC:0x7A24
2-302
DACB_AUTODETECT_CONTROL
DISPDEC:0x7A28
2-302
DACB_AUTODETECT_CONTROL2
DISPDEC:0x7A2C
2-302
DACB_AUTODETECT_STATUS
DISPDEC:0x7A34
2-303
DACB_AUTODETECT_INT_CONTROL
DISPDEC:0x7A38
2-303
DACB_FORCE_OUTPUT_CNTL
DISPDEC:0x7A3C
2-303
DACB_FORCE_DATA
DISPDEC:0x7A40
2-304
DACB_POWERDOWN
DISPDEC:0x7A50
2-304
DACB_CONTROL1
DISPDEC:0x7A54
2-304
DACB_CONTROL2
DISPDEC:0x7A58
2-304
DACB_COMPARATOR_ENABLE
DISPDEC:0x7A5C
2-305
DACB_COMPARATOR_OUTPUT
DISPDEC:0x7A60
2-305
DACB_TEST_ENABLE
DISPDEC:0x7A64
2-305
DACB_PWR_CNTL
DISPDEC:0x7A68
2-306
LVTMA_CNTL
DISPDEC:0x7A80
2-340
LVTMA_SOURCE_SELECT
DISPDEC:0x7A84
2-340
LVTMA_COLOR_FORMAT
DISPDEC:0x7A88
2-341
LVTMA_FORCE_OUTPUT_CNTL
DISPDEC:0x7A8C
2-341
LVTMA_FORCE_DATA
DISPDEC:0x7A90
2-341
LVTMA_BIT_DEPTH_CONTROL
DISPDEC:0x7A94
2-341
LVTMA_CONTROL_CHAR
DISPDEC:0x7A98
2-342
LVTMA_CONTROL0_FEEDBACK
DISPDEC:0x7A9C
2-342
LVTMA_STEREOSYNC_CTL_SEL
DISPDEC:0x7AA0
2-342
LVTMA_SYNC_CHAR_PATTERN_SEL
DISPDEC:0x7AA4
2-342
LVTMA_SYNC_CHAR_PATTERN_0_1
DISPDEC:0x7AA8
2-342
LVTMA_SYNC_CHAR_PATTERN_2_3
DISPDEC:0x7AAC
2-343
LVTMA_CRC_CNTL
DISPDEC:0x7AB0
2-343
LVTMA_CRC_SIG_MASK
DISPDEC:0x7AB4
2-343
LVTMA_CRC_SIG_RGB
DISPDEC:0x7AB8
2-344
LVTMA_2ND_CRC_RESULT
DISPDEC:0x7ABC
2-344
LVTMA_TEST_PATTERN
DISPDEC:0x7AC0
2-344
LVTMA_RANDOM_PATTERN_SEED
DISPDEC:0x7AC4
2-345
LVTMA_DEBUG
DISPDEC:0x7AC8
2-345
LVTMA_CTL_BITS
DISPDEC:0x7ACC
2-345
LVTMA_DCBALANCER_CONTROL
DISPDEC:0x7AD0
2-345
LVTMA_RED_BLUE_SWITCH
DISPDEC:0x7AD4
2-345
LVTMA_DATA_SYNCHRONIZATION
DISPDEC:0x7AD8
2-346
LVTMA_CTL0_1_GEN_CNTL
DISPDEC:0x7ADC
2-346
LVTMA_CTL2_3_GEN_CNTL
DISPDEC:0x7AE0
2-347
LVTMA_PWRSEQ_REF_DIV
DISPDEC:0x7AE4
2-348
LVTMA_PWRSEQ_DELAY1
DISPDEC:0x7AE8
2-348
LVTMA_PWRSEQ_DELAY2
DISPDEC:0x7AEC
2-349
LVTMA_PWRSEQ_CNTL
DISPDEC:0x7AF0
2-349
LVTMA_PWRSEQ_STATE
DISPDEC:0x7AF4
2-350
LVTMA_BL_MOD_CNTL
DISPDEC:0x7AF8
2-350
LVTMA_LVDS_DATA_CNTL
DISPDEC:0x7AFC
2-351
LVTMA_MODE
DISPDEC:0x7B00
2-351
LVTMA_TRANSMITTER_ENABLE
DISPDEC:0x7B04
2-351
LVTMA_LOAD_DETECT
DISPDEC:0x7B08
2-352
LVTMA_MACRO_CONTROL
DISPDEC:0x7B0C
2-352
LVTMA_TRANSMITTER_CONTROL
DISPDEC:0x7B10
2-353
LVTMA_REG_TEST_OUTPUT
DISPDEC:0x7B14
2-354
LVTMA_TRANSMITTER_DEBUG
DISPDEC:0x7B18
2-354
DC_HOT_PLUG_DETECT1_CONTROL
DISPDEC:0x7D00
2-320
DC_HOT_PLUG_DETECT1_INT_STATUS
DISPDEC:0x7D04
2-321
DC_HOT_PLUG_DETECT1_INT_CONTROL
DISPDEC:0x7D08
2-321
DC_HOT_PLUG_DETECT2_CONTROL
DISPDEC:0x7D10
2-321
DC_HOT_PLUG_DETECT2_INT_STATUS
DISPDEC:0x7D14
2-321
DC_HOT_PLUG_DETECT2_INT_CONTROL
DISPDEC:0x7D18
2-321
DC_HOT_PLUG_DETECT_CLOCK_CONTROL
DISPDEC:0x7D20
2-322
DC_I2C_STATUS1
DISPDEC:0x7D30
2-322
DC_I2C_RESET
DISPDEC:0x7D34
2-322
DC_I2C_CONTROL1
DISPDEC:0x7D38
2-322
DC_I2C_CONTROL2
DISPDEC:0x7D3C
2-323
DC_I2C_CONTROL3
DISPDEC:0x7D40
2-323
DC_I2C_DATA
DISPDEC:0x7D44
2-323
DC_I2C_INTERRUPT_CONTROL
DISPDEC:0x7D48
2-323
DC_I2C_ARBITRATION
DISPDEC:0x7D50
2-324
DC_GENERICA
DISPDEC:0x7DC0
2-324
DC_GENERICB
DISPDEC:0x7DC4
2-325
DC_PAD_EXTERN_SIG
DISPDEC:0x7DCC
2-325
DC_REF_CLK_CNTL
DISPDEC:0x7DD4
2-325
DC_GPIO_GENERIC_MASK
DISPDEC:0x7DE0
2-326
DC_GPIO_GENERIC_A
DISPDEC:0x7DE4
2-326
DC_GPIO_GENERIC_EN
DISPDEC:0x7DE8
2-326
DC_GPIO_GENERIC_Y
DISPDEC:0x7DEC
2-326
DC_GPIO_VIP_DEBUG
DISPDEC:0x7E2C
2-326
DC_GPIO_DVODATA_MASK
DISPDEC:0x7E30
2-327
DC_GPIO_DVODATA_A
DISPDEC:0x7E34
2-327
DC_GPIO_DVODATA_EN
DISPDEC:0x7E38
2-327
DC_GPIO_DVODATA_Y
DISPDEC:0x7E3C
2-327
DC_GPIO_DDC1_MASK
DISPDEC:0x7E40
2-328
DC_GPIO_DDC1_A
DISPDEC:0x7E44
2-328
DC_GPIO_DDC1_EN
DISPDEC:0x7E48
2-328
DC_GPIO_DDC1_Y
DISPDEC:0x7E4C
2-328
DC_GPIO_DDC2_MASK
DISPDEC:0x7E50
2-328
DC_GPIO_DDC2_A
DISPDEC:0x7E54
2-329
DC_GPIO_DDC2_EN
DISPDEC:0x7E58
2-329
DC_GPIO_DDC2_Y
DISPDEC:0x7E5C
2-329
DC_GPIO_DDC3_MASK
DISPDEC:0x7E60
2-329
DC_GPIO_DDC3_A
DISPDEC:0x7E64
2-329
DC_GPIO_DDC3_EN
DISPDEC:0x7E68
2-330
DC_GPIO_DDC3_Y
DISPDEC:0x7E6C
2-330
DC_GPIO_SYNCA_MASK
DISPDEC:0x7E70
2-330
DC_GPIO_SYNCA_A
DISPDEC:0x7E74
2-330
DC_GPIO_SYNCA_EN
DISPDEC:0x7E78
2-330
DC_GPIO_SYNCA_Y
DISPDEC:0x7E7C
2-331
DC_GPIO_SYNCB_MASK
DISPDEC:0x7E80
2-331
DC_GPIO_SYNCB_A
DISPDEC:0x7E84
2-331
DC_GPIO_SYNCB_EN
DISPDEC:0x7E88
2-331
DC_GPIO_SYNCB_Y
DISPDEC:0x7E8C
2-331
DC_GPIO_HPD_MASK
DISPDEC:0x7E90
2-331
DC_GPIO_HPD_A
DISPDEC:0x7E94
2-332
DC_GPIO_HPD_EN
DISPDEC:0x7E98
2-332
DC_GPIO_HPD_Y
DISPDEC:0x7E9C
2-332
DC_GPIO_PWRSEQ_MASK
DISPDEC:0x7EA0
2-332
DC_GPIO_PWRSEQ_A
DISPDEC:0x7EA4
2-332
DC_GPIO_PWRSEQ_EN
DISPDEC:0x7EA8
2-333
DC_GPIO_PWRSEQ_Y
DISPDEC:0x7EAC
2-333
CAPTURE_START_STATUS
DISPDEC:0x7ED0
2-333
DC_GPIO_PAD_STRENGTH_1
DISPDEC:0x7ED4
2-334
DC_GPIO_PAD_STRENGTH_2
DISPDEC:0x7ED8
2-334
DISP_INTERRUPT_STATUS
DISPDEC:0x7EDC
2-335
DOUT_POWER_MANAGEMENT_CNTL
DISPDEC:0x7EE0
2-336
DISP_TIMER_CONTROL
DISPDEC:0x7EF0
2-337
DO_PERFCOUNTER0_SELECT
DISPDEC:0x7F00
2-338
DO_PERFCOUNTER0_HI
DISPDEC:0x7F04
2-338
DO_PERFCOUNTER0_LOW
DISPDEC:0x7F08
2-338
DO_PERFCOUNTER1_SELECT
DISPDEC:0x7F0C
2-338
DO_PERFCOUNTER1_HI
DISPDEC:0x7F10
2-338
DO_PERFCOUNTER1_LOW
DISPDEC:0x7F14
2-338
DCO_PERFMON_CNTL_R
DISPDEC:0x7F18
2-339
CRTC_EXT_CNTL
DISPDEC:0xE054
2-196