Compare commits
2 Commits
b6acb18500
...
99555adbc2
| Author | SHA1 | Date | |
|---|---|---|---|
| 99555adbc2 | |||
| 6c3b9d9f30 |
9
.gitignore
vendored
9
.gitignore
vendored
@ -1,2 +1,11 @@
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*.pyc
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*~
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*.cmd
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*.symvers
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*.o
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*.kko
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*.order
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*.mod
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*.mod.*
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*.ko
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@ -123,8 +123,7 @@ _opcodes = """
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121 debug debug 0
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"""
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def str_to_i(s):
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d = {
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_str_i_d = {
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"reg": 0,
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"ps": 1,
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"ws": 2,
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@ -133,12 +132,23 @@ def str_to_i(s):
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"imm": 5,
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"pll": 6,
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"mc": 7,
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}
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if s in d:
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return d[s]
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}
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_i_str_d = {
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v: k for k, v in _str_i_d.items()
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}
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def str_to_i(s):
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if s in _str_i_d:
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return _str_i_d[s]
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else:
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return s
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def i_to_str(i):
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if i in _i_str_d:
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return _i_str_d[i]
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else:
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return i
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opcodes = {
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int(k): (a, b, str_to_i(c))
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for k, a, b, c in map(str.split, _opcodes.strip().split("\n"))
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@ -1,6 +1,6 @@
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import sys
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import struct
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from opcodes import opcodes
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from opcodes import opcodes, i_to_str
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import types
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with open(sys.argv[1], 'rb') as f:
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@ -26,6 +26,15 @@ def rstr(offset, length):
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global rom
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return bytes(rom[offset:offset + length])
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def uN(offset, N):
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if N == 1:
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return u8(offset)
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if N == 2:
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return u16(offset)
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if N == 4:
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return u32(offset)
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assert False, N
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ATOM_BIOS_MAGIC = 0xaa55
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ATOM_ATI_MAGIC_OFFSET = 0x30
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ATOM_ATI_MAGIC = b" 761295520"
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@ -190,31 +199,64 @@ def dest_src_size(arg, src):
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case _:
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return 1
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def print_size(n, size):
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if size == 1:
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print(f"{n:02x}", end='')
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elif size == 2:
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print(f"{n:04x}", end='')
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else:
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assert False, size
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def opcode_type_dest_src(offset, dest_type):
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attr = u8(offset)
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arg = (attr >> 0) & 0b111
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src = (attr >> 3) & 0b111
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return (
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1
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+ dest_arg_size(dest_type)
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+ dest_src_size(arg, src)
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)
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arg_size = dest_arg_size(dest_type)
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src_size = dest_src_size(arg, src)
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arg_value = uN(offset + 1, arg_size)
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src_value = uN(offset + 1 + arg_size, src_size)
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print_size(arg_value, arg_size)
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print(" <- ", end='')
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print_size(src_value, src_size)
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return 1 + arg_size + src_size
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def opcode_type_1x16(offset, dest_type):
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arg = u16(offset)
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print_size(arg, 2)
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return 2
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def opcode_type_setregblock(offset, dest_type):
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arg = u16(offset)
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print_size(arg, 2)
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return 2
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def opcode_type_dest(offset, dest_type):
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attr = u8(offset)
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src = (attr >> 3) & 0b111
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return 1 + dest_src_size(dest_type, src)
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src_size = dest_src_size(dest_type, src)
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src_arg = uN(offset + 1, src_size)
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print_size(src_arg, src_size)
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return 1 + src_size
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def opcode_type_shift(offset, dest_type):
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attr = u8(offset)
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src = (attr >> 3) & 0b111
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return 1 + dest_src_size(dest_type, src)
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src_size = dest_src_size(dest_type, src)
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src_arg = uN(offset + 1, src_size)
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print_size(src_arg, src_size)
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shift_arg = u8(offset + 1 + src_size)
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print(" by ", end='')
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print_size(shift_arg, 1)
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return 1 + src_size + 1
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def opcode_0(offset, dest_type):
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return 0
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@ -237,10 +279,12 @@ def disassemble(start, length):
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opcode = u8(offset)
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arg_type, name, dest_type = opcodes[opcode]
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pc = (offset - start) + 6
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print(f"{pc:04x} opcode {opcode:02x} {name}:{dest_type}")
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offset += 1
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handler = argument_handlers[arg_type]
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offset += handler(offset, dest_type)
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print(f"{pc:04x} opcode {opcode:02x} {name.rjust(12)} {i_to_str(dest_type).ljust(8)} ", end='')
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length = handler(offset, dest_type)
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offset += length
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print()
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def parse_table(names, table):
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structure_size = u16(table + 0)
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19
pci/Makefile
Normal file
19
pci/Makefile
Normal file
@ -0,0 +1,19 @@
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BINARY := test_pci_module
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KERNEL := /lib/modules/$(shell uname -r)/build
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ARCH := x86
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C_FLAGS := -Wall
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KMOD_DIR := $(shell pwd)
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OBJECTS := main.o
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ccflags-y += $(C_FLAGS)
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obj-m += $(BINARY).o
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$(BINARY)-y := $(OBJECTS)
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$(BINARY).ko:
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make -C $(KERNEL) M=$(KMOD_DIR) modules
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clean:
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rm -f $(BINARY).ko
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131
pci/main.c
Normal file
131
pci/main.c
Normal file
@ -0,0 +1,131 @@
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#define R500 "r500"
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static struct pci_device_id r500_id_table[] = {
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{ PCI_DEVICE(0x121a, 0x0002) },
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{ 0,}
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};
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MODULE_DEVICE_TABLE(pci, r500_id_table);
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static int r500_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
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static void r500_remove(struct pci_dev *pdev);
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static struct pci_driver r500 = {
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.name = R500,
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.id_table = r500_id_table,
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.probe = r500_probe,
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.remove = r500_remove
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};
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struct r500_priv {
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volatile u32 __iomem *hwmem;
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};
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/* */
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static int __init r500_module_init(void)
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{
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return pci_register_driver(&r500);
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}
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static void __exit r500_module_exit(void)
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{
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pci_unregister_driver(&r500);
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}
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void release_device(struct pci_dev *pdev);
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void release_device(struct pci_dev *pdev)
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{
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/* Free memory region */
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pci_release_region(pdev, pci_select_bars(pdev, IORESOURCE_MEM));
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/* And disable device */
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pci_disable_device(pdev);
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}
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/* This function is called by the kernel */
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static int r500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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int bar, err;
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u16 vendor, device;
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unsigned long mmio_start, mmio_len;
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struct r500_priv *drv_priv;
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pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
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pci_read_config_word(pdev, PCI_DEVICE_ID, &device);
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printk(KERN_INFO "vid: %04x pid: %04x\n", vendor, device);
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/* Request IO BAR */
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bar = pci_select_bars(pdev, IORESOURCE_MEM);
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/* Enable device memory */
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err = pci_enable_device_mem(pdev);
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if (err) {
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printk(KERN_INFO "pci_enable_device_mem error\n");
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return err;
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}
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/* Request memory region for the BAR */
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err = pci_request_region(pdev, bar, R500);
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if (err) {
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printk(KERN_INFO "pci_request_region error\n");
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pci_disable_device(pdev);
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return err;
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}
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/* Get start and stop memory offsets */
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mmio_start = pci_resource_start(pdev, 0);
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mmio_len = pci_resource_len(pdev, 0);
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printk(KERN_INFO "mmio_start %p mmio_len %p\n", (void*)mmio_start, (void*)mmio_len);
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/* Allocate memory for the module private data */
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drv_priv = kzalloc(sizeof(struct r500_priv), GFP_KERNEL);
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if (!drv_priv) {
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release_device(pdev);
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return -ENOMEM;
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}
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/* Remap BAR to the local pointer */
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drv_priv->hwmem = ioremap(mmio_start, mmio_len);
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if (!drv_priv->hwmem) {
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release_device(pdev);
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return -EIO;
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}
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/* Set module private data */
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/* Now we can access mapped "hwmem" from the any module's function */
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pci_set_drvdata(pdev, drv_priv);
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return 0;
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}
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/* Clean up */
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static void r500_remove(struct pci_dev *pdev)
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{
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struct r500_priv *drv_priv = pci_get_drvdata(pdev);
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if (drv_priv) {
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if (drv_priv->hwmem) {
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iounmap(drv_priv->hwmem);
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}
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kfree(drv_priv);
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}
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release_device(pdev);
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}
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Zachary Buhman <zack@buhman.org>");
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MODULE_DESCRIPTION("R500 module");
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MODULE_VERSION("0.1");
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module_init(r500_module_init);
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module_exit(r500_module_exit);
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280
regs/3d_registers.txt
Normal file
280
regs/3d_registers.txt
Normal file
@ -0,0 +1,280 @@
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CP:CP_CSQ2_STAT · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7fc
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CP:CP_CSQ_ADDR · [W] · 32 bits · Access: 8/16/32 · MMReg:0x7f0
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CP:CP_CSQ_APER_INDIRECT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x1300-0x13fc
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CP:CP_CSQ_APER_INDIRECT2 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x1200-0x12fc
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CP:CP_CSQ_APER_PRIMARY · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x1000-0x11fc
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CP:CP_CSQ_AVAIL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7b8
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CP:CP_CSQ_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x740
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CP:CP_CSQ_DATA · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7f4
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CP:CP_CSQ_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x744
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CP:CP_CSQ_STAT · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7f8
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CP:CP_GUI_COMMAND · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x728
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CP:CP_GUI_DST_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x724
|
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CP:CP_GUI_SRC_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x720
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CP:CP_IB2_BASE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x730
|
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CP:CP_IB2_BUFSZ · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x734
|
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CP:CP_IB_BASE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x738
|
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CP:CP_IB_BUFSZ · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x73c
|
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CP:CP_ME_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7d0
|
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CP:CP_ME_RAM_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7d4
|
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CP:CP_ME_RAM_DATAH · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7dc
|
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CP:CP_ME_RAM_DATAL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7e0
|
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CP:CP_ME_RAM_RADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7d8
|
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CP:CP_RB_BASE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x700
|
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CP:CP_RB_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x704
|
||||
CP:CP_RB_RPTR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x710
|
||||
CP:CP_RB_RPTR_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x70c
|
||||
CP:CP_RB_RPTR_WR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x71c
|
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CP:CP_RB_WPTR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x714
|
||||
CP:CP_RB_WPTR_DELAY · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x718
|
||||
CP:CP_RESYNC_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x778
|
||||
CP:CP_RESYNC_DATA · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x77c
|
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CP:CP_STAT · [R] · 32 bits · Access: 8/16/32 · MMReg:0x7c0
|
||||
CP:CP_VID_COMMAND · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7cc
|
||||
CP:CP_VID_DST_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7c8
|
||||
CP:CP_VID_SRC_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7c4
|
||||
CP:CP_VP_ADDR_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x7e8
|
||||
CB:RB3D_AARESOLVE_CTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e88
|
||||
CB:RB3D_AARESOLVE_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e80
|
||||
CB:RB3D_AARESOLVE_PITCH · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e84
|
||||
CB:RB3D_ABLENDCNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e08
|
||||
CB:RB3D_BLENDCNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e04
|
||||
CB:RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4ea4
|
||||
CB:RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4ea0
|
||||
CB:RB3D_CCTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e00
|
||||
CB:RB3D_CLRCMP_CLR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e20
|
||||
CB:RB3D_CLRCMP_FLIPE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e1c
|
||||
CB:RB3D_CLRCMP_MSK · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e24
|
||||
CB:RB3D_COLOROFFSET[0-3] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e28-0x4e34
|
||||
CB:RB3D_COLORPITCH[0-3] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e38-0x4e44
|
||||
CB:RB3D_COLOR_CHANNEL_MASK · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e0c
|
||||
CB:RB3D_COLOR_CLEAR_VALUE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e14
|
||||
CB:RB3D_COLOR_CLEAR_VALUE_AR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x46c0
|
||||
CB:RB3D_COLOR_CLEAR_VALUE_GB · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x46c4
|
||||
CB:RB3D_CONSTANT_COLOR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e10
|
||||
CB:RB3D_CONSTANT_COLOR_AR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4ef8
|
||||
CB:RB3D_CONSTANT_COLOR_GB · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4efc
|
||||
CB:RB3D_DITHER_CTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e50
|
||||
CB:RB3D_DSTCACHE_CTLSTAT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e4c
|
||||
CB:RB3D_FIFO_SIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4ef4
|
||||
CB:RB3D_ROPCNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4e18
|
||||
FG:FG_ALPHA_FUNC · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bd4
|
||||
FG:FG_ALPHA_VALUE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4be0
|
||||
FG:FG_DEPTH_SRC · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bd8
|
||||
FG:FG_FOG_BLEND · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bc0
|
||||
FG:FG_FOG_COLOR_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bd0
|
||||
FG:FG_FOG_COLOR_G · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bcc
|
||||
FG:FG_FOG_COLOR_R · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bc8
|
||||
FG:FG_FOG_FACTOR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4bc4
|
||||
GA:GA_COLOR_CONTROL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4278
|
||||
GA:GA_COLOR_CONTROL_PS3 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4258
|
||||
GA:GA_ENHANCE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4274
|
||||
GA:GA_FIFO_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4270
|
||||
GA:GA_FILL_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x422c
|
||||
GA:GA_FILL_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4228
|
||||
GA:GA_FILL_R · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4220
|
||||
GA:GA_FOG_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4298
|
||||
GA:GA_FOG_SCALE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4294
|
||||
GA:GA_IDLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x425c
|
||||
GA:GA_LINE_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4234
|
||||
GA:GA_LINE_S0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4264
|
||||
GA:GA_LINE_S1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4268
|
||||
GA:GA_LINE_STIPPLE_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4238
|
||||
GA:GA_LINE_STIPPLE_VALUE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4260
|
||||
GA:GA_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4290
|
||||
GA:GA_POINT_MINMAX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4230
|
||||
GA:GA_POINT_S0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4200
|
||||
GA:GA_POINT_S1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4208
|
||||
GA:GA_POINT_SIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x421c
|
||||
GA:GA_POINT_T0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4204
|
||||
GA:GA_POINT_T1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x420c
|
||||
GA:GA_POLY_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4288
|
||||
GA:GA_ROUND_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x428c
|
||||
GA:GA_SOLID_BA · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4280
|
||||
GA:GA_SOLID_RG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x427c
|
||||
GA:GA_TRIANGLE_STIPPLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4214
|
||||
GA:GA_US_VECTOR_DATA · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4254
|
||||
GA:GA_US_VECTOR_INDEX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4250
|
||||
GB:GB_AA_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4020
|
||||
GB:GB_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4008
|
||||
GB:GB_FIFO_SIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4024
|
||||
GB:GB_FIFO_SIZE1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4070
|
||||
GB:GB_MSPOS0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4010
|
||||
GB:GB_MSPOS1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4014
|
||||
GB:GB_PIPE_SELECT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x402c
|
||||
GB:GB_SELECT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x401c
|
||||
GB:GB_TILE_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4018
|
||||
GB:GB_Z_PEQ_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4028
|
||||
GB:PS3_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4118
|
||||
GB:PS3_TEX_SOURCE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4120
|
||||
GB:PS3_VTX_FMT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x411c
|
||||
RS:RS_COUNT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4300
|
||||
RS:RS_INST_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4320-0x435c
|
||||
RS:RS_INST_COUNT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4304
|
||||
RS:RS_IP_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4074-0x40b0
|
||||
SC:SC_CLIP_0_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43b0
|
||||
SC:SC_CLIP_0_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43b4
|
||||
SC:SC_CLIP_1_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43b8
|
||||
SC:SC_CLIP_1_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43bc
|
||||
SC:SC_CLIP_2_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43c0
|
||||
SC:SC_CLIP_2_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43c4
|
||||
SC:SC_CLIP_3_A · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43c8
|
||||
SC:SC_CLIP_3_B · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43cc
|
||||
SC:SC_CLIP_RULE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43d0
|
||||
SC:SC_EDGERULE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43a8
|
||||
SC:SC_HYPERZ_EN · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43a4
|
||||
SC:SC_SCISSOR0 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43e0
|
||||
SC:SC_SCISSOR1 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43e4
|
||||
SC:SC_SCREENDOOR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x43e8
|
||||
SU:SU_CULL_MODE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42b8
|
||||
SU:SU_DEPTH_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42c4
|
||||
SU:SU_DEPTH_SCALE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42c0
|
||||
SU:SU_POLY_OFFSET_BACK_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42b0
|
||||
SU:SU_POLY_OFFSET_BACK_SCALE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42ac
|
||||
SU:SU_POLY_OFFSET_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42b4
|
||||
SU:SU_POLY_OFFSET_FRONT_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42a8
|
||||
SU:SU_POLY_OFFSET_FRONT_SCALE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42a4
|
||||
SU:SU_REG_DEST · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42c8
|
||||
SU:SU_TEX_WRAP · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x42a0
|
||||
SU:SU_TEX_WRAP_PS3 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4114
|
||||
TX:TX_BORDER_COLOR_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x45c0-0x45fc
|
||||
TX:TX_CHROMA_KEY_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4580-0x45bc
|
||||
TX:TX_ENABLE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4104
|
||||
TX:TX_FILTER0_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4400-0x443c
|
||||
TX:TX_FILTER1_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4440-0x447c
|
||||
TX:TX_FILTER4 · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4110
|
||||
TX:TX_FORMAT0_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4480-0x44bc
|
||||
TX:TX_FORMAT1_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x44c0-0x44fc
|
||||
TX:TX_FORMAT2_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4500-0x453c
|
||||
TX:TX_INVALTAGS · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4100
|
||||
TX:TX_OFFSET_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4540-0x457c
|
||||
US:US_ALU_ALPHA_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa800-0xaffc
|
||||
US:US_ALU_ALPHA_ADDR_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9800-0x9ffc
|
||||
US:US_ALU_RGBA_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xb000-0xb7fc
|
||||
US:US_ALU_RGB_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa000-0xa7fc
|
||||
US:US_ALU_RGB_ADDR_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9000-0x97fc
|
||||
US:US_CMN_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xb800-0xbffc
|
||||
US:US_CODE_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4630
|
||||
US:US_CODE_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4638
|
||||
US:US_CODE_RANGE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4634
|
||||
US:US_CONFIG · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4600
|
||||
US:US_FC_ADDR_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa000-0xa7fc
|
||||
US:US_FC_BOOL_CONST · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4620
|
||||
US:US_FC_CTRL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4624
|
||||
US:US_FC_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9800-0x9ffc
|
||||
US:US_FC_INT_CONST_[0-31] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4c00-0x4c7c
|
||||
US:US_FORMAT0_[0-15] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4640-0x467c
|
||||
US:US_OUT_FMT_[0-3] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x46a4-0x46b0
|
||||
US:US_PIXSIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4604
|
||||
US:US_TEX_ADDR_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9800-0x9ffc
|
||||
US:US_TEX_ADDR_DXDY_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0xa000-0xa7fc
|
||||
US:US_TEX_INST_[0-511] · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x9000-0x97fc
|
||||
US:US_W_FMT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x46b4
|
||||
VAP:VAP_ALT_NUM_VERTICES · [R/W] · 32 bits · Access: 32 · MMReg:0x2088
|
||||
VAP:VAP_CLIP_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x221c
|
||||
VAP:VAP_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2080
|
||||
VAP:VAP_CNTL_STATUS · [R/W] · 32 bits · Access: 32 · MMReg:0x2140
|
||||
VAP:VAP_GB_HORZ_CLIP_ADJ · [R/W] · 32 bits · Access: 32 · MMReg:0x2228
|
||||
VAP:VAP_GB_HORZ_DISC_ADJ · [R/W] · 32 bits · Access: 32 · MMReg:0x222c
|
||||
VAP:VAP_GB_VERT_CLIP_ADJ · [R/W] · 32 bits · Access: 32 · MMReg:0x2220
|
||||
VAP:VAP_GB_VERT_DISC_ADJ · [R/W] · 32 bits · Access: 32 · MMReg:0x2224
|
||||
VAP:VAP_INDEX_OFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x208c
|
||||
VAP:VAP_OUT_VTX_FMT_0 · [R/W] · 32 bits · Access: 32 · MMReg:0x2090
|
||||
VAP:VAP_OUT_VTX_FMT_1 · [R/W] · 32 bits · Access: 32 · MMReg:0x2094
|
||||
VAP:VAP_PORT_DATA[0-15] · [W] · 32 bits · Access: 32 · MMReg:0x2000-0x203c
|
||||
VAP:VAP_PORT_DATA_IDX_128 · [W] · 32 bits · Access: 32 · MMReg:0x20b8
|
||||
VAP:VAP_PORT_IDX[0-15] · [W] · 32 bits · Access: 32 · MMReg:0x2040-0x207c
|
||||
VAP:VAP_PROG_STREAM_CNTL_[0-7] · [R/W] · 32 bits · Access: 32 · MMReg:0x2150-0x216c
|
||||
VAP:VAP_PROG_STREAM_CNTL_EXT_[0-7] · [R/W] · 32 bits · Access: 32 · MMReg:0x21e0-0x21fc
|
||||
VAP:VAP_PSC_SGN_NORM_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x21dc
|
||||
VAP:VAP_PVS_CODE_CNTL_0 · [R/W] · 32 bits · Access: 32 · MMReg:0x22d0
|
||||
VAP:VAP_PVS_CODE_CNTL_1 · [R/W] · 32 bits · Access: 32 · MMReg:0x22d8
|
||||
VAP:VAP_PVS_CONST_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x22d4
|
||||
VAP:VAP_PVS_FLOW_CNTL_ADDRS_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2230-0x226c
|
||||
VAP:VAP_PVS_FLOW_CNTL_ADDRS_LW_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2500-0x2578
|
||||
VAP:VAP_PVS_FLOW_CNTL_ADDRS_UW_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2504-0x257c
|
||||
VAP:VAP_PVS_FLOW_CNTL_LOOP_INDEX_[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x2290-0x22cc
|
||||
VAP:VAP_PVS_FLOW_CNTL_OPC · [R/W] · 32 bits · Access: 32 · MMReg:0x22dc
|
||||
VAP:VAP_PVS_STATE_FLUSH_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2284
|
||||
VAP:VAP_PVS_VECTOR_DATA_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2204
|
||||
VAP:VAP_PVS_VECTOR_DATA_REG_128 · [W] · 32 bits · Access: 32 · MMReg:0x2208
|
||||
VAP:VAP_PVS_VECTOR_INDX_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2200
|
||||
VAP:VAP_PVS_VTX_TIMEOUT_REG · [R/W] · 32 bits · Access: 32 · MMReg:0x2288
|
||||
VAP:VAP_TEX_TO_COLOR_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2218
|
||||
VAP:VAP_VF_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2084
|
||||
VAP:VAP_VF_MAX_VTX_INDX · [R/W] · 32 bits · Access: 32 · MMReg:0x2134
|
||||
VAP:VAP_VF_MIN_VTX_INDX · [R/W] · 32 bits · Access: 32 · MMReg:0x2138
|
||||
VAP:VAP_VPORT_XOFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x1d9c, MMReg:0x209c
|
||||
VAP:VAP_VPORT_XSCALE · [R/W] · 32 bits · Access: 32 · MMReg:0x1d98, MMReg:0x2098
|
||||
VAP:VAP_VPORT_YOFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x1da4, MMReg:0x20a4
|
||||
VAP:VAP_VPORT_YSCALE · [R/W] · 32 bits · Access: 32 · MMReg:0x1da0, MMReg:0x20a0
|
||||
VAP:VAP_VPORT_ZOFFSET · [R/W] · 32 bits · Access: 32 · MMReg:0x1dac, MMReg:0x20ac
|
||||
VAP:VAP_VPORT_ZSCALE · [R/W] · 32 bits · Access: 32 · MMReg:0x1da8, MMReg:0x20a8
|
||||
VAP:VAP_VTE_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x20b0
|
||||
VAP:VAP_VTX_AOS_ADDR[0-15] · [R/W] · 32 bits · Access: 32 · MMReg:0x20c8-0x2120
|
||||
VAP:VAP_VTX_AOS_ATTR[01-1415] · [R/W] · 32 bits · Access: 32 · MMReg:0x20c4-0x2118
|
||||
VAP:VAP_VTX_NUM_ARRAYS · [R/W] · 32 bits · Access: 32 · MMReg:0x20c0
|
||||
VAP:VAP_VTX_SIZE · [R/W] · 32 bits · Access: 32 · MMReg:0x204b
|
||||
VAP:VAP_VTX_STATE_CNTL · [R/W] · 32 bits · Access: 32 · MMReg:0x2180
|
||||
VAP:VAP_VTX_ST_BLND_WT_[0-3] · [R/W] · 32 bits · Access: 32 · MMReg:0x2430-0x243c
|
||||
VAP:VAP_VTX_ST_CLR_[0-7]_A · [R/W] · 32 bits · Access: 32 · MMReg:0x232c-0x239c
|
||||
VAP:VAP_VTX_ST_CLR_[0-7]_B · [R/W] · 32 bits · Access: 32 · MMReg:0x2328-0x2398
|
||||
VAP:VAP_VTX_ST_CLR_[0-7]_G · [R/W] · 32 bits · Access: 32 · MMReg:0x2324-0x2394
|
||||
VAP:VAP_VTX_ST_CLR_[0-7]_PKD · [W] · 32 bits · Access: 32 · MMReg:0x2470-0x248c
|
||||
VAP:VAP_VTX_ST_CLR_[0-7]_R · [R/W] · 32 bits · Access: 32 · MMReg:0x2320-0x2390
|
||||
VAP:VAP_VTX_ST_DISC_FOG · [R/W] · 32 bits · Access: 32 · MMReg:0x2424
|
||||
VAP:VAP_VTX_ST_EDGE_FLAGS · [R/W] · 32 bits · Access: 32 · MMReg:0x245c
|
||||
VAP:VAP_VTX_ST_END_OF_PKT · [W] · 32 bits · Access: 32 · MMReg:0x24ac
|
||||
VAP:VAP_VTX_ST_NORM_0_PKD · [W] · 32 bits · Access: 32 · MMReg:0x2498
|
||||
VAP:VAP_VTX_ST_NORM_0_X · [R/W] · 32 bits · Access: 32 · MMReg:0x2310
|
||||
VAP:VAP_VTX_ST_NORM_0_Y · [R/W] · 32 bits · Access: 32 · MMReg:0x2314
|
||||
VAP:VAP_VTX_ST_NORM_0_Z · [R/W] · 32 bits · Access: 32 · MMReg:0x2318
|
||||
VAP:VAP_VTX_ST_NORM_1_X · [R/W] · 32 bits · Access: 32 · MMReg:0x2450
|
||||
VAP:VAP_VTX_ST_NORM_1_Y · [R/W] · 32 bits · Access: 32 · MMReg:0x2454
|
||||
VAP:VAP_VTX_ST_NORM_1_Z · [R/W] · 32 bits · Access: 32 · MMReg:0x2458
|
||||
VAP:VAP_VTX_ST_PNT_SPRT_SZ · [R/W] · 32 bits · Access: 32 · MMReg:0x2420
|
||||
VAP:VAP_VTX_ST_POS_0_W_4 · [R/W] · 32 bits · Access: 32 · MMReg:0x230c
|
||||
VAP:VAP_VTX_ST_POS_0_X_2 · [W] · 32 bits · Access: 32 · MMReg:0x2490
|
||||
VAP:VAP_VTX_ST_POS_0_X_3 · [W] · 32 bits · Access: 32 · MMReg:0x24a0
|
||||
VAP:VAP_VTX_ST_POS_0_X_4 · [R/W] · 32 bits · Access: 32 · MMReg:0x2300
|
||||
VAP:VAP_VTX_ST_POS_0_Y_2 · [W] · 32 bits · Access: 32 · MMReg:0x2494
|
||||
VAP:VAP_VTX_ST_POS_0_Y_3 · [W] · 32 bits · Access: 32 · MMReg:0x24a4
|
||||
VAP:VAP_VTX_ST_POS_0_Y_4 · [R/W] · 32 bits · Access: 32 · MMReg:0x2304
|
||||
VAP:VAP_VTX_ST_POS_0_Z_3 · [W] · 32 bits · Access: 32 · MMReg:0x24a8
|
||||
VAP:VAP_VTX_ST_POS_0_Z_4 · [R/W] · 32 bits · Access: 32 · MMReg:0x2308
|
||||
VAP:VAP_VTX_ST_POS_1_W · [R/W] · 32 bits · Access: 32 · MMReg:0x244c
|
||||
VAP:VAP_VTX_ST_POS_1_X · [R/W] · 32 bits · Access: 32 · MMReg:0x2440
|
||||
VAP:VAP_VTX_ST_POS_1_Y · [R/W] · 32 bits · Access: 32 · MMReg:0x2444
|
||||
VAP:VAP_VTX_ST_POS_1_Z · [R/W] · 32 bits · Access: 32 · MMReg:0x2448
|
||||
VAP:VAP_VTX_ST_PVMS · [R/W] · 32 bits · Access: 32 · MMReg:0x231c
|
||||
VAP:VAP_VTX_ST_SHININESS_0 · [R/W] · 32 bits · Access: 32 · MMReg:0x2428
|
||||
VAP:VAP_VTX_ST_SHININESS_1 · [R/W] · 32 bits · Access: 32 · MMReg:0x242c
|
||||
VAP:VAP_VTX_ST_TEX_[0-7]_Q · [R/W] · 32 bits · Access: 32 · MMReg:0x23ac-0x241c
|
||||
VAP:VAP_VTX_ST_TEX_[0-7]_R · [R/W] · 32 bits · Access: 32 · MMReg:0x23a8-0x2418
|
||||
VAP:VAP_VTX_ST_TEX_[0-7]_S · [R/W] · 32 bits · Access: 32 · MMReg:0x23a0-0x2410
|
||||
VAP:VAP_VTX_ST_TEX_[0-7]_T · [R/W] · 32 bits · Access: 32 · MMReg:0x23a4-0x2414
|
||||
VAP:VAP_VTX_ST_USR_CLR_A · [R/W] · 32 bits · Access: 32 · MMReg:0x246c
|
||||
VAP:VAP_VTX_ST_USR_CLR_B · [R/W] · 32 bits · Access: 32 · MMReg:0x2468
|
||||
VAP:VAP_VTX_ST_USR_CLR_G · [R/W] · 32 bits · Access: 32 · MMReg:0x2464
|
||||
VAP:VAP_VTX_ST_USR_CLR_PKD · [W] · 32 bits · Access: 32 · MMReg:0x249c
|
||||
VAP:VAP_VTX_ST_USR_CLR_R · [R/W] · 32 bits · Access: 32 · MMReg:0x2460
|
||||
ZB:ZB_BW_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f1c
|
||||
ZB:ZB_CNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f00
|
||||
ZB:ZB_DEPTHCLEARVALUE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f28
|
||||
ZB:ZB_DEPTHOFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f20
|
||||
ZB:ZB_DEPTHPITCH · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f24
|
||||
ZB:ZB_DEPTHXY_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f60
|
||||
ZB:ZB_FIFO_SIZE · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4fd0
|
||||
ZB:ZB_FORMAT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f10
|
||||
ZB:ZB_HIZ_DWORD · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f4c
|
||||
ZB:ZB_HIZ_OFFSET · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f44
|
||||
ZB:ZB_HIZ_PITCH · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f54
|
||||
ZB:ZB_HIZ_RDINDEX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f50
|
||||
ZB:ZB_HIZ_WRINDEX · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f48
|
||||
ZB:ZB_STENCILREFMASK · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f08
|
||||
ZB:ZB_STENCILREFMASK_BF · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4fd4
|
||||
ZB:ZB_ZCACHE_CTLSTAT · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f18
|
||||
ZB:ZB_ZPASS_ADDR · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f5c
|
||||
ZB:ZB_ZPASS_DATA · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f58
|
||||
ZB:ZB_ZSTENCILCNTL · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f04
|
||||
ZB:ZB_ZTOP · [R/W] · 32 bits · Access: 8/16/32 · MMReg:0x4f14
|
||||
Loading…
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Reference in New Issue
Block a user