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7 Commits
6fe4e55a24
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9bedf5e1a9
| Author | SHA1 | Date | |
|---|---|---|---|
| 9bedf5e1a9 | |||
| 960694b184 | |||
| a6e5d755ce | |||
| 4b49077792 | |||
| c8b9a0f992 | |||
| 7dcbf79605 | |||
| 54451811e0 |
4
drm/.gitignore
vendored
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4
drm/.gitignore
vendored
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@ -0,0 +1,4 @@
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*
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!*.*
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!*/
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!Makefile
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969
drm/3d_registers_bits.h
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969
drm/3d_registers_bits.h
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@ -0,0 +1,969 @@
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#pragma once
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#define CP_CSQ2_STAT__CSQ_WPTR_INDIRECT(n) (((n) & 0x3ff) << 0)
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#define CP_CSQ2_STAT__CSQ_RPTR_INDIRECT2(n) (((n) & 0x3ff) << 10)
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#define CP_CSQ2_STAT__CSQ_WPTR_INDIRECT2(n) (((n) & 0x3ff) << 20)
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#define CP_CSQ_ADDR__CSQ_ADDR(n) (((n) & 0x3ff) << 2)
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#define CP_CSQ_APER_INDIRECT__CP_CSQ_APER_INDIRECT(n) (((n) & 0xffffffff) << 0)
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#define CP_CSQ_APER_INDIRECT2__CP_CSQ_APER_INDIRECT2(n) (((n) & 0xffffffff) << 0)
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#define CP_CSQ_APER_PRIMARY__CP_CSQ_APER_PRIMARY(n) (((n) & 0xffffffff) << 0)
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#define CP_CSQ_AVAIL__CSQ_CNT_PRIMARY(n) (((n) & 0x3ff) << 0)
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#define CP_CSQ_AVAIL__CSQ_CNT_INDIRECT(n) (((n) & 0x3ff) << 10)
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#define CP_CSQ_AVAIL__CSQ_CNT_INDIRECT2(n) (((n) & 0x3ff) << 20)
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#define CP_CSQ_CNTL__CSQ_MODE(n) (((n) & 0xf) << 28)
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#define CP_CSQ_DATA__CSQ_DATA(n) (((n) & 0xffffffff) << 0)
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#define CP_CSQ_MODE__INDIRECT2_START(n) (((n) & 0x7f) << 0)
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#define CP_CSQ_MODE__INDIRECT1_START(n) (((n) & 0x7f) << 8)
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#define CP_CSQ_MODE__CSQ_INDIRECT2_ENABLE(n) (((n) & 0x1) << 27)
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#define CP_CSQ_MODE__CSQ_INDIRECT1_ENABLE(n) (((n) & 0x1) << 29)
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#define CP_CSQ_MODE__CSQ_PRIMARY_ENABLE(n) (((n) & 0x1) << 31)
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#define CP_CSQ_STAT__CSQ_RPTR_PRIMARY(n) (((n) & 0x3ff) << 0)
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#define CP_CSQ_STAT__CSQ_WPTR_PRIMARY(n) (((n) & 0x3ff) << 10)
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#define CP_CSQ_STAT__CSQ_RPTR_INDIRECT(n) (((n) & 0x3ff) << 20)
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#define CP_GUI_COMMAND__CP_GUI_COMMAND(n) (((n) & 0xffffffff) << 0)
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#define CP_GUI_DST_ADDR__CP_GUI_DST_ADDR(n) (((n) & 0xffffffff) << 0)
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#define CP_GUI_SRC_ADDR__CP_GUI_SRC_ADDR(n) (((n) & 0xffffffff) << 0)
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#define CP_IB2_BASE__IB2_BASE(n) (((n) & 0x3fffffff) << 2)
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#define CP_IB2_BUFZ__IB2_BUFSZ(n) (((n) & 0x7fffff) << 0)
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#define CP_IB_BASE__IB_BASE(n) (((n) & 0x3fffffff) << 2)
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#define CP_IB_BUFSZ__IB_BUFSZ(n) (((n) & 0x7fffff) << 0)
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#define CP_ME_CNTL__ME_STAT(n) (((n) & 0xffff) << 0)
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#define CP_ME_CNTL__ME_STATMUX(n) (((n) & 0x1f) << 16)
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#define CP_ME_CNTL__ME_BUSY(n) (((n) & 0x1) << 29)
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#define CP_ME_CNTL__ME_MODE(n) (((n) & 0x1) << 30)
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#define CP_ME_CNTL__ME_STEP(n) (((n) & 0x1) << 31)
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#define CP_ME_RAM_ADDR__ME_RAM_ADDR(n) (((n) & 0xff) << 0)
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#define CP_ME_RAM_DATAH__ME_RAM_DATAH(n) (((n) & 0xff) << 0)
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#define CP_ME_RAM_DATAL__ME_RAM_DATAL(n) (((n) & 0xffffffff) << 0)
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#define CP_ME_RAM_RADDR__ME_RAM_RADDR(n) (((n) & 0xff) << 0)
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#define CP_RB_BASE__RB_BASE(n) (((n) & 0x3fffffff) << 2)
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#define CP_RB_CNTL__RB_BUFSZ(n) (((n) & 0x3f) << 0)
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#define CP_RB_CNTL__RB_BLKSZ(n) (((n) & 0x3f) << 8)
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#define CP_RB_CNTL__BUF_SWAP(n) (((n) & 0x3) << 16)
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#define CP_RB_CNTL__MAX_FETCH(n) (((n) & 0x3) << 18)
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#define CP_RB_CNTL__RB_NO_UPDATE(n) (((n) & 0x1) << 27)
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#define CP_RB_CNTL__RB_RPTR_WR_ENA(n) (((n) & 0x1) << 31)
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#define CP_RB_RPTR__RB_RPTR(n) (((n) & 0x7fffff) << 0)
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#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP(n) (((n) & 0x3) << 0)
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#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR(n) (((n) & 0x3fffffff) << 2)
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#define CP_RB_RPTR_WR__RB_RPTR_WR(n) (((n) & 0x7fffff) << 0)
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#define CP_RB_WPTR__RB_WPTR(n) (((n) & 0x7fffff) << 0)
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#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER(n) (((n) & 0xfffffff) << 0)
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#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT(n) (((n) & 0xf) << 28)
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#define CP_RESYNC_ADDR__RESYNC_ADDR(n) (((n) & 0x7) << 0)
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#define CP_RESYNC_DATA__RESYNC_DATA(n) (((n) & 0xffffffff) << 0)
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#define CP_STAT__MRU_BUSY(n) (((n) & 0x1) << 0)
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#define CP_STAT__MWU_BUSY(n) (((n) & 0x1) << 1)
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#define CP_STAT__RSIU_BUSY(n) (((n) & 0x1) << 2)
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#define CP_STAT__RCIU_BUSY(n) (((n) & 0x1) << 3)
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#define CP_STAT__CSF_PRIMARY_BUSY(n) (((n) & 0x1) << 9)
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#define CP_STAT__CSF_INDIRECT_BUSY(n) (((n) & 0x1) << 10)
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#define CP_STAT__CSQ_PRIMARY_BUSY(n) (((n) & 0x1) << 11)
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#define CP_STAT__CSQ_INDIRECT_BUSY(n) (((n) & 0x1) << 12)
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#define CP_STAT__CSI_BUSY(n) (((n) & 0x1) << 13)
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#define CP_STAT__CSF_INDIRECT2_BUSY(n) (((n) & 0x1) << 14)
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#define CP_STAT__CSQ_INDIRECT2_BUSY(n) (((n) & 0x1) << 15)
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#define CP_STAT__GUIDMA_BUSY(n) (((n) & 0x1) << 28)
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#define CP_STAT__VIDDMA_BUSY(n) (((n) & 0x1) << 29)
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#define CP_STAT__CMDSTRM_BUSY(n) (((n) & 0x1) << 30)
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#define CP_STAT__CP_BUSY(n) (((n) & 0x1) << 31)
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#define CP_VID_ADDR_CNTL__SCRATCH_ALT_VP_WR(n) (((n) & 0x1) << 0)
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#define CP_VID_ADDR_CNTL__SCRATCH_VP_WR(n) (((n) & 0x1) << 1)
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#define CP_VID_ADDR_CNTL__RPTR_VP_UPDATE(n) (((n) & 0x1) << 2)
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#define CP_VID_ADDR_CNTL__VIDDMA_VP_WR(n) (((n) & 0x1) << 3)
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#define CP_VID_ADDR_CNTL__VIDDMA_VP_RD(n) (((n) & 0x1) << 4)
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#define CP_VID_ADDR_CNTL__GUIDMA_VP_WR(n) (((n) & 0x1) << 5)
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#define CP_VID_ADDR_CNTL__GUIDMA_VP_RD(n) (((n) & 0x1) << 6)
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#define CP_VID_ADDR_CNTL__INDR2_VP_FETCH(n) (((n) & 0x1) << 7)
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#define CP_VID_ADDR_CNTL__INDR1_VP_FETCH(n) (((n) & 0x1) << 8)
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#define CP_VID_ADDR_CNTL__RING_VP_FETCH(n) (((n) & 0x1) << 9)
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#define CP_VID_COMMAND__CP_VID_COMMAND(n) (((n) & 0xffffffff) << 0)
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#define CP_VID_DST_ADDR__CP_VID_DST_ADDR(n) (((n) & 0xffffffff) << 0)
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#define CP_VID_SRC_ADDR__CP_VID_SRC_ADDR(n) (((n) & 0xffffffff) << 0)
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#define FG_ALPHA_FUNC__AF_VAL(n) (((n) & 0xff) << 0)
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#define FG_ALPHA_FUNC__AF_FUNC(n) (((n) & 0x7) << 8)
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#define FG_ALPHA_FUNC__AF_EN(n) (((n) & 0x1) << 11)
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#define FG_ALPHA_FUNC__AF_EN_8BIT(n) (((n) & 0x1) << 12)
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#define FG_ALPHA_FUNC__AM_EN(n) (((n) & 0x1) << 16)
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#define FG_ALPHA_FUNC__AM_CFG(n) (((n) & 0x1) << 17)
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#define FG_ALPHA_FUNC__DITH_EN(n) (((n) & 0x1) << 20)
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#define FG_ALPHA_FUNC__ALP_OFF_EN(n) (((n) & 0x1) << 24)
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#define FG_ALPHA_FUNC__DISCARD_ZERO_MASK_QUAD(n) (((n) & 0x1) << 25)
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#define FG_ALPHA_FUNC__FP16_ENABLE(n) (((n) & 0x1) << 28)
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#define FG_ALPHA_VALUE__AF_VAL(n) (((n) & 0xffff) << 0)
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#define FG_DEPTH_SRC__DEPTH_SRC(n) (((n) & 0x1) << 0)
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#define FG_FOG_BLEND__ENABLE(n) (((n) & 0x1) << 0)
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#define FG_FOG_BLEND__FN(n) (((n) & 0x3) << 1)
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#define FG_FOG_COLOR_B__BLUE(n) (((n) & 0x3ff) << 0)
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#define FG_FOG_COLOR_G__GREEN(n) (((n) & 0x3ff) << 0)
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#define FG_FOG_COLOR_R__RED(n) (((n) & 0x3ff) << 0)
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#define FG_FOG_FACTOR__FACTOR(n) (((n) & 0x3ff) << 0)
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#define GA_COLOR_CONTROL__RGB0_SHADING(n) (((n) & 0x3) << 0)
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#define GA_COLOR_CONTROL__ALPHA0_SHADING(n) (((n) & 0x3) << 2)
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#define GA_COLOR_CONTROL__RGB1_SHADING(n) (((n) & 0x3) << 4)
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#define GA_COLOR_CONTROL__ALPHA1_SHADING(n) (((n) & 0x3) << 6)
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#define GA_COLOR_CONTROL__RGB2_SHADING(n) (((n) & 0x3) << 8)
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#define GA_COLOR_CONTROL__ALPHA2_SHADING(n) (((n) & 0x3) << 10)
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#define GA_COLOR_CONTROL__RGB3_SHADING(n) (((n) & 0x3) << 12)
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#define GA_COLOR_CONTROL__ALPHA3_SHADING(n) (((n) & 0x3) << 14)
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#define GA_COLOR_CONTROL__PROVOKING_VERTEX(n) (((n) & 0x3) << 16)
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#define GA_COLOR_CONTROL_PS3__TEX0_SHADING_PS3(n) (((n) & 0x3) << 0)
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#define GA_COLOR_CONTROL_PS3__TEX1_SHADING_PS3(n) (((n) & 0x3) << 2)
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#define GA_COLOR_CONTROL_PS3__TEX2_SHADING_PS3(n) (((n) & 0x3) << 4)
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#define GA_COLOR_CONTROL_PS3__TEX3_SHADING_PS3(n) (((n) & 0x3) << 6)
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#define GA_COLOR_CONTROL_PS3__TEX4_SHADING_PS3(n) (((n) & 0x3) << 8)
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#define GA_COLOR_CONTROL_PS3__TEX5_SHADING_PS3(n) (((n) & 0x3) << 10)
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#define GA_COLOR_CONTROL_PS3__TEX6_SHADING_PS3(n) (((n) & 0x3) << 12)
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#define GA_COLOR_CONTROL_PS3__TEX7_SHADING_PS3(n) (((n) & 0x3) << 14)
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#define GA_COLOR_CONTROL_PS3__TEX8_SHADING_PS3(n) (((n) & 0x3) << 16)
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#define GA_COLOR_CONTROL_PS3__TEX9_SHADING_PS3(n) (((n) & 0x3) << 18)
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#define GA_COLOR_CONTROL_PS3__TEX10_SHADING_PS3(n) (((n) & 0x3) << 20)
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#define GA_COLOR_CONTROL_PS3__COLOR0_TEX_OVERRIDE(n) (((n) & 0xf) << 22)
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#define GA_COLOR_CONTROL_PS3__COLOR1_TEX_OVERRIDE(n) (((n) & 0xf) << 26)
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#define GA_ENHANCE__DEADLOCK_CNTL(n) (((n) & 0x1) << 0)
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#define GA_ENHANCE__FASTSYNC_CNTL(n) (((n) & 0x1) << 1)
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#define GA_ENHANCE__REG_READWRITE(n) (((n) & 0x1) << 2)
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#define GA_ENHANCE__REG_NOSTALL(n) (((n) & 0x1) << 3)
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#define GA_FIFO_CNTL__VERTEX_FIFO(n) (((n) & 0x7) << 0)
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#define GA_FIFO_CNTL__INDEX_FIFO(n) (((n) & 0x7) << 3)
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#define GA_FIFO_CNTL__REG_FIFO(n) (((n) & 0xff) << 6)
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#define GA_FILL_A__COLOR_ALPHA(n) (((n) & 0xffffffff) << 0)
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#define GA_FILL_B__COLOR_BLUE(n) (((n) & 0xffffffff) << 0)
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#define GA_FILL_G__COLOR_GREEN(n) (((n) & 0xffffffff) << 0)
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#define GA_FILL_R__COLOR_RED(n) (((n) & 0xffffffff) << 0)
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#define GA_FOG_OFFSET__VALUE(n) (((n) & 0xffffffff) << 0)
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#define GA_FOG_SCALE__VALUE(n) (((n) & 0xffffffff) << 0)
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#define GA_IDLE__PIPE3_Z_IDLE(n) (((n) & 0x1) << 0)
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#define GA_IDLE__PIPE2_Z_IDLE(n) (((n) & 0x1) << 1)
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#define GA_IDLE__PIPE3_CB_IDLE(n) (((n) & 0x1) << 2)
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#define GA_IDLE__PIPE2_CB_IDLE(n) (((n) & 0x1) << 3)
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#define GA_IDLE__PIPE3_FG_IDLE(n) (((n) & 0x1) << 4)
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#define GA_IDLE__PIPE2_FG_IDLE(n) (((n) & 0x1) << 5)
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#define GA_IDLE__PIPE3_US_IDLE(n) (((n) & 0x1) << 6)
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#define GA_IDLE__PIPE2_US_IDLE(n) (((n) & 0x1) << 7)
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#define GA_IDLE__PIPE3_SC_IDLE(n) (((n) & 0x1) << 8)
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#define GA_IDLE__PIPE2_SC_IDLE(n) (((n) & 0x1) << 9)
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#define GA_IDLE__PIPE3_RS_IDLE(n) (((n) & 0x1) << 10)
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#define GA_IDLE__PIPE2_RS_IDLE(n) (((n) & 0x1) << 11)
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#define GA_IDLE__PIPE1_Z_IDLE(n) (((n) & 0x1) << 12)
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#define GA_IDLE__PIPE0_Z_IDLE(n) (((n) & 0x1) << 13)
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#define GA_IDLE__PIPE1_CB_IDLE(n) (((n) & 0x1) << 14)
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#define GA_IDLE__PIPE0_CB_IDLE(n) (((n) & 0x1) << 15)
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#define GA_IDLE__PIPE1_FG_IDLE(n) (((n) & 0x1) << 16)
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#define GA_IDLE__PIPE0_FG_IDLE(n) (((n) & 0x1) << 17)
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#define GA_IDLE__PIPE1_US_IDLE(n) (((n) & 0x1) << 18)
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#define GA_IDLE__PIPE0_US_IDLE(n) (((n) & 0x1) << 19)
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#define GA_IDLE__PIPE1_SC_IDLE(n) (((n) & 0x1) << 20)
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#define GA_IDLE__PIPE0_SC_IDLE(n) (((n) & 0x1) << 21)
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#define GA_IDLE__PIPE1_RS_IDLE(n) (((n) & 0x1) << 22)
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#define GA_IDLE__PIPE0_RS_IDLE(n) (((n) & 0x1) << 23)
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#define GA_IDLE__SU_IDLE(n) (((n) & 0x1) << 24)
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#define GA_IDLE__GA_IDLE(n) (((n) & 0x1) << 25)
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#define GA_IDLE__GA_UNIT2_IDLE(n) (((n) & 0x1) << 26)
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#define GA_LINE_CNTL__WIDTH(n) (((n) & 0xffff) << 0)
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#define GA_LINE_CNTL__END_TYPE(n) (((n) & 0x3) << 16)
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#define GA_LINE_CNTL__SORT(n) (((n) & 0x1) << 18)
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#define GA_LINE_S0__S0(n) (((n) & 0xffffffff) << 0)
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#define GA_LINE_S1__S1(n) (((n) & 0xffffffff) << 0)
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#define GA_LINE_STIPPLE_CONFIG__LINE_RESET(n) (((n) & 0x3) << 0)
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#define GA_LINE_STIPPLE_CONFIG__STIPPLE_SCALE(n) (((n) & 0x3fffffff) << 2)
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#define GA_OFFSET__X_OFFSET(n) (((n) & 0xffff) << 0)
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#define GA_OFFSET__Y_OFFSET(n) (((n) & 0xffff) << 16)
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#define GA_POINT_MINMAX__MIN_SIZE(n) (((n) & 0xffff) << 0)
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#define GA_POINT_MINMAX__MAX_SIZE(n) (((n) & 0xffff) << 16)
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#define GA_POINT_S0__S0(n) (((n) & 0xffffffff) << 0)
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#define GA_POINT_S1__S1(n) (((n) & 0xffffffff) << 0)
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#define GA_POINT_SIZE__HEIGHT(n) (((n) & 0xffff) << 0)
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#define GA_POINT_SIZE__WIDTH(n) (((n) & 0xffff) << 16)
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#define GA_POINT_T0__T0(n) (((n) & 0xffffffff) << 0)
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#define GA_POINT_T1__T1(n) (((n) & 0xffffffff) << 0)
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#define GA_POLY_MODE__POLY_MODE(n) (((n) & 0x3) << 0)
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#define GA_POLY_MODE__FRONT_PTYPE(n) (((n) & 0x7) << 4)
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#define GA_POLY_MODE__BACK_PTYPE(n) (((n) & 0x7) << 7)
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#define GA_ROUND_MODE__GEOMETRY_ROUND(n) (((n) & 0x3) << 0)
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#define GA_ROUND_MODE__COLOR_ROUND(n) (((n) & 0x3) << 2)
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#define GA_ROUND_MODE__RGB_CLAMP(n) (((n) & 0x1) << 4)
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#define GA_ROUND_MODE__ALPHA_CLAMP(n) (((n) & 0x1) << 5)
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#define GA_ROUND_MODE__GEOMETRY_MASK(n) (((n) & 0xf) << 6)
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#define GA_SOLID_BA__COLOR_ALPHA(n) (((n) & 0xffff) << 0)
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#define GA_SOLID_BA__COLOR_BLUE(n) (((n) & 0xffff) << 16)
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#define GA_SOLID_RG__COLOR_GREEN(n) (((n) & 0xffff) << 0)
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#define GA_SOLID_RG__COLOR_RED(n) (((n) & 0xffff) << 16)
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#define GA_TRIANGLE_STIPPLE__X_SHIFT(n) (((n) & 0xf) << 0)
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#define GA_TRIANGLE_STIPPLE__Y_SHIFT(n) (((n) & 0xf) << 16)
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#define GA_US_VECTOR_DATA__DATA(n) (((n) & 0xffffffff) << 0)
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#define GA_US_VECTOR_INDEX__INDEX(n) (((n) & 0x1ff) << 0)
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#define GA_US_VECTOR_INDEX__TYPE(n) (((n) & 0x1) << 16)
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#define GA_US_VECTOR_INDEX__CLAMP(n) (((n) & 0x1) << 17)
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#define GB_AA_CONFIG__AA_ENABLE(n) (((n) & 0x1) << 0)
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#define GB_AA_CONFIG__NUM_AA_SUBSAMPLES(n) (((n) & 0x3) << 1)
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#define GB_ENABLE__POINT_STUFF_ENABLE(n) (((n) & 0x1) << 0)
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#define GB_ENABLE__LINE_STUFF_ENABLE(n) (((n) & 0x1) << 1)
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#define GB_ENABLE__TRIANGLE_STUFF_ENABLE(n) (((n) & 0x1) << 2)
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#define GB_ENABLE__STENCIL_AUTO(n) (((n) & 0x3) << 4)
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#define GB_ENABLE__TEX0_SOURCE(n) (((n) & 0x3) << 16)
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#define GB_ENABLE__TEX1_SOURCE(n) (((n) & 0x3) << 18)
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#define GB_ENABLE__TEX2_SOURCE(n) (((n) & 0x3) << 20)
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#define GB_ENABLE__TEX3_SOURCE(n) (((n) & 0x3) << 22)
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#define GB_ENABLE__TEX4_SOURCE(n) (((n) & 0x3) << 24)
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#define GB_ENABLE__TEX5_SOURCE(n) (((n) & 0x3) << 26)
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#define GB_ENABLE__TEX6_SOURCE(n) (((n) & 0x3) << 28)
|
||||
#define GB_ENABLE__TEX7_SOURCE(n) (((n) & 0x3) << 30)
|
||||
#define GB_FIFO_SIZE__SC_IFIFO_SIZE(n) (((n) & 0x3) << 0)
|
||||
#define GB_FIFO_SIZE__SC_TZFIFO_SIZE(n) (((n) & 0x3) << 2)
|
||||
#define GB_FIFO_SIZE__SC_BFIFO_SIZE(n) (((n) & 0x3) << 4)
|
||||
#define GB_FIFO_SIZE__RS_TFIFO_SIZE(n) (((n) & 0x3) << 6)
|
||||
#define GB_FIFO_SIZE__RS_CFIFO_SIZE(n) (((n) & 0x3) << 8)
|
||||
#define GB_FIFO_SIZE__US_RAM_SIZE(n) (((n) & 0x3) << 10)
|
||||
#define GB_FIFO_SIZE__US_OFIFO_SIZE(n) (((n) & 0x3) << 12)
|
||||
#define GB_FIFO_SIZE__US_WFIFO_SIZE(n) (((n) & 0x3) << 14)
|
||||
#define GB_FIFO_SIZE__RS_HIGHWATER_COL(n) (((n) & 0x7) << 16)
|
||||
#define GB_FIFO_SIZE__RS_HIGHWATER_TEX(n) (((n) & 0x7) << 19)
|
||||
#define GB_FIFO_SIZE__US_OFIFO_HIGHWATER(n) (((n) & 0x3) << 22)
|
||||
#define GB_FIFO_SIZE__US_CUBE_FIFO_HIGHWATER(n) (((n) & 0x1f) << 24)
|
||||
#define GB_FIFO_SIZE1__SC_HIGHWATER_IFIFO(n) (((n) & 0x3f) << 0)
|
||||
#define GB_FIFO_SIZE1__SC_HIGHWATER_BFIFO(n) (((n) & 0x3f) << 6)
|
||||
#define GB_FIFO_SIZE1__RS_HIGHWATER_COL(n) (((n) & 0x3f) << 12)
|
||||
#define GB_FIFO_SIZE1__RS_HIGHWATER_TEX(n) (((n) & 0x3f) << 18)
|
||||
#define GB_MSPOS0__MS_X0(n) (((n) & 0xf) << 0)
|
||||
#define GB_MSPOS0__MS_Y0(n) (((n) & 0xf) << 4)
|
||||
#define GB_MSPOS0__MS_X1(n) (((n) & 0xf) << 8)
|
||||
#define GB_MSPOS0__MS_Y1(n) (((n) & 0xf) << 12)
|
||||
#define GB_MSPOS0__MS_X2(n) (((n) & 0xf) << 16)
|
||||
#define GB_MSPOS0__MS_Y2(n) (((n) & 0xf) << 20)
|
||||
#define GB_MSPOS0__MSBD0_Y(n) (((n) & 0xf) << 24)
|
||||
#define GB_MSPOS0__MSBD0_X(n) (((n) & 0xf) << 28)
|
||||
#define GB_MSPOS1__MS_X3(n) (((n) & 0xf) << 0)
|
||||
#define GB_MSPOS1__MS_Y3(n) (((n) & 0xf) << 4)
|
||||
#define GB_MSPOS1__MS_X4(n) (((n) & 0xf) << 8)
|
||||
#define GB_MSPOS1__MS_Y4(n) (((n) & 0xf) << 12)
|
||||
#define GB_MSPOS1__MS_X5(n) (((n) & 0xf) << 16)
|
||||
#define GB_MSPOS1__MS_Y5(n) (((n) & 0xf) << 20)
|
||||
#define GB_MSPOS1__MSBD1(n) (((n) & 0xf) << 24)
|
||||
#define GB_PIPE_SELECT__PIPE0_ID(n) (((n) & 0x3) << 0)
|
||||
#define GB_PIPE_SELECT__PIPE1_ID(n) (((n) & 0x3) << 2)
|
||||
#define GB_PIPE_SELECT__PIPE2_ID(n) (((n) & 0x3) << 4)
|
||||
#define GB_PIPE_SELECT__PIPE3_ID(n) (((n) & 0x3) << 6)
|
||||
#define GB_PIPE_SELECT__PIPE_MASK(n) (((n) & 0xf) << 8)
|
||||
#define GB_PIPE_SELECT__MAX_PIPE(n) (((n) & 0x3) << 12)
|
||||
#define GB_PIPE_SELECT__BAD_PIPES(n) (((n) & 0xf) << 14)
|
||||
#define GB_PIPE_SELECT__CONFIG_PIPES(n) (((n) & 0x1) << 18)
|
||||
#define GB_SELECT__FOG_SELECT(n) (((n) & 0x7) << 0)
|
||||
#define GB_SELECT__DEPTH_SELECT(n) (((n) & 0x1) << 3)
|
||||
#define GB_SELECT__W_SELECT(n) (((n) & 0x1) << 4)
|
||||
#define GB_SELECT__FOG_STUFF_ENABLE(n) (((n) & 0x1) << 5)
|
||||
#define GB_SELECT__FOG_STUFF_TEX(n) (((n) & 0xf) << 6)
|
||||
#define GB_SELECT__FOG_STUFF_COMP(n) (((n) & 0x3) << 10)
|
||||
#define GB_TILE_CONFIG__ENABLE(n) (((n) & 0x1) << 0)
|
||||
#define GB_TILE_CONFIG__PIPE_COUNT(n) (((n) & 0x7) << 1)
|
||||
#define GB_TILE_CONFIG__TILE_SIZE(n) (((n) & 0x3) << 4)
|
||||
#define GB_TILE_CONFIG__SUPER_SIZE(n) (((n) & 0x7) << 6)
|
||||
#define GB_TILE_CONFIG__SUPER_X(n) (((n) & 0x7) << 9)
|
||||
#define GB_TILE_CONFIG__SUPER_Y(n) (((n) & 0x7) << 12)
|
||||
#define GB_TILE_CONFIG__SUPER_TILE(n) (((n) & 0x1) << 15)
|
||||
#define GB_TILE_CONFIG__SUBPIXEL(n) (((n) & 0x1) << 16)
|
||||
#define GB_TILE_CONFIG__QUADS_PER_RAS(n) (((n) & 0x3) << 17)
|
||||
#define GB_TILE_CONFIG__BB_SCAN(n) (((n) & 0x1) << 19)
|
||||
#define GB_TILE_CONFIG__ALT_SCAN_EN(n) (((n) & 0x1) << 20)
|
||||
#define GB_TILE_CONFIG__ALT_OFFSET(n) (((n) & 0x1) << 21)
|
||||
#define GB_TILE_CONFIG__SUBPRECISION(n) (((n) & 0x1) << 22)
|
||||
#define GB_TILE_CONFIG__ALT_TILING(n) (((n) & 0x1) << 23)
|
||||
#define GB_TILE_CONFIG__Z_EXTENDED(n) (((n) & 0x1) << 24)
|
||||
#define GB_Z_PEQ_CONFIG__Z_PEQ_SIZE(n) (((n) & 0x1) << 0)
|
||||
#define PS3_ENABLE__PS3_MODE(n) (((n) & 0x1) << 0)
|
||||
#define PS3_TEX_SOURCE__TEX0_SOURCE(n) (((n) & 0x3) << 0)
|
||||
#define PS3_TEX_SOURCE__TEX1_SOURCE(n) (((n) & 0x3) << 2)
|
||||
#define PS3_TEX_SOURCE__TEX2_SOURCE(n) (((n) & 0x3) << 4)
|
||||
#define PS3_TEX_SOURCE__TEX3_SOURCE(n) (((n) & 0x3) << 6)
|
||||
#define PS3_TEX_SOURCE__TEX4_SOURCE(n) (((n) & 0x3) << 8)
|
||||
#define PS3_TEX_SOURCE__TEX5_SOURCE(n) (((n) & 0x3) << 10)
|
||||
#define PS3_TEX_SOURCE__TEX6_SOURCE(n) (((n) & 0x3) << 12)
|
||||
#define PS3_TEX_SOURCE__TEX7_SOURCE(n) (((n) & 0x3) << 14)
|
||||
#define PS3_TEX_SOURCE__TEX8_SOURCE(n) (((n) & 0x3) << 16)
|
||||
#define PS3_TEX_SOURCE__TEX9_SOURCE(n) (((n) & 0x3) << 18)
|
||||
#define PS3_VTX_FMT__TEX_0_COMP_CNT(n) (((n) & 0x7) << 0)
|
||||
#define PS3_VTX_FMT__TEX_1_COMP_CNT(n) (((n) & 0x7) << 3)
|
||||
#define PS3_VTX_FMT__TEX_2_COMP_CNT(n) (((n) & 0x7) << 6)
|
||||
#define PS3_VTX_FMT__TEX_3_COMP_CNT(n) (((n) & 0x7) << 9)
|
||||
#define PS3_VTX_FMT__TEX_4_COMP_CNT(n) (((n) & 0x7) << 12)
|
||||
#define PS3_VTX_FMT__TEX_5_COMP_CNT(n) (((n) & 0x7) << 15)
|
||||
#define PS3_VTX_FMT__TEX_6_COMP_CNT(n) (((n) & 0x7) << 18)
|
||||
#define PS3_VTX_FMT__TEX_7_COMP_CNT(n) (((n) & 0x7) << 21)
|
||||
#define PS3_VTX_FMT__TEX_8_COMP_CNT(n) (((n) & 0x7) << 24)
|
||||
#define PS3_VTX_FMT__TEX_9_COMP_CNT(n) (((n) & 0x7) << 27)
|
||||
#define PS3_VTX_FMT__TEX_10_COMP_CNT(n) (((n) & 0x3) << 30)
|
||||
#define RB3D_AARESOLVE_CTL__AARESOLVE_MODE(n) (((n) & 0x1) << 0)
|
||||
#define RB3D_AARESOLVE_CTL__AARESOLVE_GAMMA(n) (((n) & 0x1) << 1)
|
||||
#define RB3D_AARESOLVE_CTL__AARESOLVE_ALPHA(n) (((n) & 0x1) << 2)
|
||||
#define RB3D_AARESOLVE_OFFSET__AARESOLVE_OFFSET(n) (((n) & 0x7ffffff) << 5)
|
||||
#define RB3D_AARESOLVE_PITCH__AARESOLVE_PITCH(n) (((n) & 0x1fff) << 1)
|
||||
#define RB3D_ABLENDCNTL__COMB_FCN(n) (((n) & 0x7) << 12)
|
||||
#define RB3D_ABLENDCNTL__SRCBLEND(n) (((n) & 0x3f) << 16)
|
||||
#define RB3D_ABLENDCNTL__DESTBLEND(n) (((n) & 0x3f) << 24)
|
||||
#define RB3D_BLENDCNTL__ALPHA_BLEND_ENABLE(n) (((n) & 0x1) << 0)
|
||||
#define RB3D_BLENDCNTL__SEPARATE_ALPHA_ENABLE(n) (((n) & 0x1) << 1)
|
||||
#define RB3D_BLENDCNTL__READ_ENABLE(n) (((n) & 0x1) << 2)
|
||||
#define RB3D_BLENDCNTL__DISCARD_SRC_PIXELS(n) (((n) & 0x7) << 3)
|
||||
#define RB3D_BLENDCNTL__COMB_FCN(n) (((n) & 0x7) << 12)
|
||||
#define RB3D_BLENDCNTL__SRCBLEND(n) (((n) & 0x3f) << 16)
|
||||
#define RB3D_BLENDCNTL__DESTBLEND(n) (((n) & 0x3f) << 24)
|
||||
#define RB3D_BLENDCNTL__SRC_ALPHA_0_NO_READ(n) (((n) & 0x1) << 30)
|
||||
#define RB3D_BLENDCNTL__SRC_ALPHA_1_NO_READ(n) (((n) & 0x1) << 31)
|
||||
#define RB3D_CCTL__NUM_MULTIWRITES(n) (((n) & 0x3) << 5)
|
||||
#define RB3D_CCTL__CLRCMP_FLIPE_ENABLE(n) (((n) & 0x1) << 7)
|
||||
#define RB3D_CCTL__AA_COMPRESSION_ENABLE(n) (((n) & 0x1) << 9)
|
||||
#define RB3D_CCTL__CMASK_ENABLE(n) (((n) & 0x1) << 10)
|
||||
#define RB3D_CCTL__INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE(n) (((n) & 0x1) << 12)
|
||||
#define RB3D_CCTL__WRITE_COMPRESSION_DISABLE(n) (((n) & 0x1) << 13)
|
||||
#define RB3D_CCTL__INDEPENDENT_COLORFORMAT_ENABLE(n) (((n) & 0x1) << 14)
|
||||
#define RB3D_CLRCMP_CLR__CLRCMP_CLR(n) (((n) & 0xffffffff) << 0)
|
||||
#define RB3D_CLRCMP_FLIPE__CLRCMP_FLIPE(n) (((n) & 0xffffffff) << 0)
|
||||
#define RB3D_CLRCMP_MSK__CLRCMP_MSK(n) (((n) & 0xffffffff) << 0)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__BLUE_MASK(n) (((n) & 0x1) << 0)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__GREEN_MASK(n) (((n) & 0x1) << 1)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__RED_MASK(n) (((n) & 0x1) << 2)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__ALPHA_MASK(n) (((n) & 0x1) << 3)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__BLUE_MASK1(n) (((n) & 0x1) << 4)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__GREEN_MASK1(n) (((n) & 0x1) << 5)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__RED_MASK1(n) (((n) & 0x1) << 6)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__ALPHA_MASK1(n) (((n) & 0x1) << 7)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__BLUE_MASK2(n) (((n) & 0x1) << 8)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__GREEN_MASK2(n) (((n) & 0x1) << 9)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__RED_MASK2(n) (((n) & 0x1) << 10)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__ALPHA_MASK2(n) (((n) & 0x1) << 11)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__BLUE_MASK3(n) (((n) & 0x1) << 12)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__GREEN_MASK3(n) (((n) & 0x1) << 13)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__RED_MASK3(n) (((n) & 0x1) << 14)
|
||||
#define RB3D_COLOR_CHANNEL_MASK__ALPHA_MASK3(n) (((n) & 0x1) << 15)
|
||||
#define RB3D_COLOR_CLEAR_VALUE__BLUE(n) (((n) & 0xff) << 0)
|
||||
#define RB3D_COLOR_CLEAR_VALUE__GREEN(n) (((n) & 0xff) << 8)
|
||||
#define RB3D_COLOR_CLEAR_VALUE__RED(n) (((n) & 0xff) << 16)
|
||||
#define RB3D_COLOR_CLEAR_VALUE__ALPHA(n) (((n) & 0xff) << 24)
|
||||
#define RB3D_COLOR_CLEAR_VALUE_AR__RED(n) (((n) & 0xffff) << 0)
|
||||
#define RB3D_COLOR_CLEAR_VALUE_AR__ALPHA(n) (((n) & 0xffff) << 16)
|
||||
#define RB3D_COLOR_CLEAR_VALUE_GB__BLUE(n) (((n) & 0xffff) << 0)
|
||||
#define RB3D_COLOR_CLEAR_VALUE_GB__GREEN(n) (((n) & 0xffff) << 16)
|
||||
#define RB3D_COLOROFFSET__COLOROFFSET(n) (((n) & 0x7ffffff) << 5)
|
||||
#define RB3D_COLORPITCH__COLORPITCH(n) (((n) & 0x1fff) << 1)
|
||||
#define RB3D_COLORPITCH__COLORTILE(n) (((n) & 0x1) << 16)
|
||||
#define RB3D_COLORPITCH__COLORMICROTILE(n) (((n) & 0x3) << 17)
|
||||
#define RB3D_COLORPITCH__COLORENDIAN(n) (((n) & 0x3) << 19)
|
||||
#define RB3D_COLORPITCH__COLORFORMAT(n) (((n) & 0xf) << 21)
|
||||
#define RB3D_CONSTANT_COLOR__BLUE(n) (((n) & 0xff) << 0)
|
||||
#define RB3D_CONSTANT_COLOR__GREEN(n) (((n) & 0xff) << 8)
|
||||
#define RB3D_CONSTANT_COLOR__RED(n) (((n) & 0xff) << 16)
|
||||
#define RB3D_CONSTANT_COLOR__ALPHA(n) (((n) & 0xff) << 24)
|
||||
#define RB3D_CONSTANT_COLOR_AR__RED(n) (((n) & 0xffff) << 0)
|
||||
#define RB3D_CONSTANT_COLOR_AR__ALPHA(n) (((n) & 0xffff) << 16)
|
||||
#define RB3D_CONSTANT_COLOR_GB__BLUE(n) (((n) & 0xffff) << 0)
|
||||
#define RB3D_CONSTANT_COLOR_GB__GREEN(n) (((n) & 0xffff) << 16)
|
||||
#define RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__BLUE(n) (((n) & 0xff) << 0)
|
||||
#define RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__GREEN(n) (((n) & 0xff) << 8)
|
||||
#define RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__RED(n) (((n) & 0xff) << 16)
|
||||
#define RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__ALPHA(n) (((n) & 0xff) << 24)
|
||||
#define RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__BLUE(n) (((n) & 0xff) << 0)
|
||||
#define RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__GREEN(n) (((n) & 0xff) << 8)
|
||||
#define RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__RED(n) (((n) & 0xff) << 16)
|
||||
#define RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__ALPHA(n) (((n) & 0xff) << 24)
|
||||
#define RB3D_DITHER_CTL__DITHER_MODE(n) (((n) & 0x3) << 0)
|
||||
#define RB3D_DITHER_CTL__ALPHA_DITHER_MODE(n) (((n) & 0x3) << 2)
|
||||
#define RB3D_DSTCACHE_CTLSTAT__DC_FLUSH(n) (((n) & 0x3) << 0)
|
||||
#define RB3D_DSTCACHE_CTLSTAT__DC_FREE(n) (((n) & 0x3) << 2)
|
||||
#define RB3D_DSTCACHE_CTLSTAT__DC_FINISH(n) (((n) & 0x1) << 4)
|
||||
#define RB3D_FIFO_SIZE__OP_FIFO_SIZE(n) (((n) & 0x3) << 0)
|
||||
#define RB3D_ROPCNTL__ROP_ENABLE(n) (((n) & 0x1) << 2)
|
||||
#define RB3D_ROPCNTL__ROP(n) (((n) & 0xf) << 8)
|
||||
#define RS_COUNT__IT_COUNT(n) (((n) & 0x7f) << 0)
|
||||
#define RS_COUNT__IC_COUNT(n) (((n) & 0xf) << 7)
|
||||
#define RS_COUNT__W_ADDR(n) (((n) & 0x3f) << 12)
|
||||
#define RS_COUNT__HIRES_EN(n) (((n) & 0x1) << 18)
|
||||
#define RS_INST__TEX_ID(n) (((n) & 0xf) << 0)
|
||||
#define RS_INST__TEX_CN(n) (((n) & 0x1) << 4)
|
||||
#define RS_INST__TEX_ADDR(n) (((n) & 0x7f) << 5)
|
||||
#define RS_INST__COL_ID(n) (((n) & 0xf) << 12)
|
||||
#define RS_INST__COL_CN(n) (((n) & 0x3) << 16)
|
||||
#define RS_INST__COL_ADDR(n) (((n) & 0x7f) << 18)
|
||||
#define RS_INST__TEX_ADJ(n) (((n) & 0x1) << 25)
|
||||
#define RS_INST__W_CN(n) (((n) & 0x1) << 26)
|
||||
#define RS_INST_COUNT__INST_COUNT(n) (((n) & 0xf) << 0)
|
||||
#define RS_INST_COUNT__TX_OFFSET(n) (((n) & 0x7) << 5)
|
||||
#define RS_IP__TEX_PTR_S(n) (((n) & 0x3f) << 0)
|
||||
#define RS_IP__TEX_PTR_T(n) (((n) & 0x3f) << 6)
|
||||
#define RS_IP__TEX_PTR_R(n) (((n) & 0x3f) << 12)
|
||||
#define RS_IP__TEX_PTR_Q(n) (((n) & 0x3f) << 18)
|
||||
#define RS_IP__COL_PTR(n) (((n) & 0x7) << 24)
|
||||
#define RS_IP__COL_FMT(n) (((n) & 0xf) << 27)
|
||||
#define RS_IP__OFFSET_EN(n) (((n) & 0x1) << 31)
|
||||
#define SC_CLIP_0_A__XS0(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_CLIP_0_A__YS0(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_CLIP_0_B__XS1(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_CLIP_0_B__YS1(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_CLIP_1_A__XS0(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_CLIP_1_A__YS0(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_CLIP_1_B__XS1(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_CLIP_1_B__YS1(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_CLIP_2_A__XS0(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_CLIP_2_A__YS0(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_CLIP_2_B__XS1(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_CLIP_2_B__YS1(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_CLIP_3_A__XS0(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_CLIP_3_A__YS0(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_CLIP_3_B__XS1(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_CLIP_3_B__YS1(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_CLIP_RULE__CLIP_RULE(n) (((n) & 0xffff) << 0)
|
||||
#define SC_EDGERULE__ER_TRI(n) (((n) & 0x1f) << 0)
|
||||
#define SC_EDGERULE__ER_POINT(n) (((n) & 0x1f) << 5)
|
||||
#define SC_EDGERULE__ER_LINE_LR(n) (((n) & 0x1f) << 10)
|
||||
#define SC_EDGERULE__ER_LINE_RL(n) (((n) & 0x1f) << 15)
|
||||
#define SC_EDGERULE__ER_LINE_TB(n) (((n) & 0x1f) << 20)
|
||||
#define SC_EDGERULE__ER_LINE_BT(n) (((n) & 0x1f) << 25)
|
||||
#define SC_HYPERZ_EN__HZ_EN(n) (((n) & 0x1) << 0)
|
||||
#define SC_HYPERZ_EN__HZ_MAX(n) (((n) & 0x1) << 1)
|
||||
#define SC_HYPERZ_EN__HZ_ADJ(n) (((n) & 0x7) << 2)
|
||||
#define SC_HYPERZ_EN__HZ_Z0MIN(n) (((n) & 0x1) << 5)
|
||||
#define SC_HYPERZ_EN__HZ_Z0MAX(n) (((n) & 0x1) << 6)
|
||||
#define SC_SCISSOR0__XS0(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_SCISSOR0__YS0(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_SCISSOR1__XS1(n) (((n) & 0x1fff) << 0)
|
||||
#define SC_SCISSOR1__YS1(n) (((n) & 0x1fff) << 13)
|
||||
#define SC_SCREENDOOR__SCREENDOOR(n) (((n) & 0xffffff) << 0)
|
||||
#define SU_CULL_MODE__CULL_FRONT(n) (((n) & 0x1) << 0)
|
||||
#define SU_CULL_MODE__CULL_BACK(n) (((n) & 0x1) << 1)
|
||||
#define SU_CULL_MODE__FACE(n) (((n) & 0x1) << 2)
|
||||
#define SU_DEPTH_OFFSET__OFFSET(n) (((n) & 0xffffffff) << 0)
|
||||
#define SU_DEPTH_SCALE__SCALE(n) (((n) & 0xffffffff) << 0)
|
||||
#define SU_POLY_OFFSET_BACK_OFFSET__OFFSET(n) (((n) & 0xffffffff) << 0)
|
||||
#define SU_POLY_OFFSET_BACK_SCALE__SCALE(n) (((n) & 0xffffffff) << 0)
|
||||
#define SU_POLY_OFFSET_ENABLE__FRONT_ENABLE(n) (((n) & 0x1) << 0)
|
||||
#define SU_POLY_OFFSET_ENABLE__BACK_ENABLE(n) (((n) & 0x1) << 1)
|
||||
#define SU_POLY_OFFSET_ENABLE__PARA_ENABLE(n) (((n) & 0x1) << 2)
|
||||
#define SU_POLY_OFFSET_FRONT_OFFSET__OFFSET(n) (((n) & 0xffffffff) << 0)
|
||||
#define SU_POLY_OFFSET_FRONT_SCALE__SCALE(n) (((n) & 0xffffffff) << 0)
|
||||
#define SU_REG_DEST__SELECT(n) (((n) & 0xf) << 0)
|
||||
#define SU_TEX_WRAP__T0C0(n) (((n) & 0x1) << 0)
|
||||
#define SU_TEX_WRAP__T0C1(n) (((n) & 0x1) << 1)
|
||||
#define SU_TEX_WRAP__T0C2(n) (((n) & 0x1) << 2)
|
||||
#define SU_TEX_WRAP__T0C3(n) (((n) & 0x1) << 3)
|
||||
#define SU_TEX_WRAP__T1C0(n) (((n) & 0x1) << 4)
|
||||
#define SU_TEX_WRAP__T1C1(n) (((n) & 0x1) << 5)
|
||||
#define SU_TEX_WRAP__T1C2(n) (((n) & 0x1) << 6)
|
||||
#define SU_TEX_WRAP__T1C3(n) (((n) & 0x1) << 7)
|
||||
#define SU_TEX_WRAP__T2C0(n) (((n) & 0x1) << 8)
|
||||
#define SU_TEX_WRAP__T2C1(n) (((n) & 0x1) << 9)
|
||||
#define SU_TEX_WRAP__T2C2(n) (((n) & 0x1) << 10)
|
||||
#define SU_TEX_WRAP__T2C3(n) (((n) & 0x1) << 11)
|
||||
#define SU_TEX_WRAP__T3C0(n) (((n) & 0x1) << 12)
|
||||
#define SU_TEX_WRAP__T3C1(n) (((n) & 0x1) << 13)
|
||||
#define SU_TEX_WRAP__T3C2(n) (((n) & 0x1) << 14)
|
||||
#define SU_TEX_WRAP__T3C3(n) (((n) & 0x1) << 15)
|
||||
#define SU_TEX_WRAP__T4C0(n) (((n) & 0x1) << 16)
|
||||
#define SU_TEX_WRAP__T4C1(n) (((n) & 0x1) << 17)
|
||||
#define SU_TEX_WRAP__T4C2(n) (((n) & 0x1) << 18)
|
||||
#define SU_TEX_WRAP__T4C3(n) (((n) & 0x1) << 19)
|
||||
#define SU_TEX_WRAP__T5C0(n) (((n) & 0x1) << 20)
|
||||
#define SU_TEX_WRAP__T5C1(n) (((n) & 0x1) << 21)
|
||||
#define SU_TEX_WRAP__T5C2(n) (((n) & 0x1) << 22)
|
||||
#define SU_TEX_WRAP__T5C3(n) (((n) & 0x1) << 23)
|
||||
#define SU_TEX_WRAP__T6C0(n) (((n) & 0x1) << 24)
|
||||
#define SU_TEX_WRAP__T6C1(n) (((n) & 0x1) << 25)
|
||||
#define SU_TEX_WRAP__T6C2(n) (((n) & 0x1) << 26)
|
||||
#define SU_TEX_WRAP__T6C3(n) (((n) & 0x1) << 27)
|
||||
#define SU_TEX_WRAP__T7C0(n) (((n) & 0x1) << 28)
|
||||
#define SU_TEX_WRAP__T7C1(n) (((n) & 0x1) << 29)
|
||||
#define SU_TEX_WRAP__T7C2(n) (((n) & 0x1) << 30)
|
||||
#define SU_TEX_WRAP__T7C3(n) (((n) & 0x1) << 31)
|
||||
#define SU_TEX_WRAP_PS3__T9C0(n) (((n) & 0x1) << 0)
|
||||
#define SU_TEX_WRAP_PS3__T9C1(n) (((n) & 0x1) << 1)
|
||||
#define SU_TEX_WRAP_PS3__T9C2(n) (((n) & 0x1) << 2)
|
||||
#define SU_TEX_WRAP_PS3__T9C3(n) (((n) & 0x1) << 3)
|
||||
#define SU_TEX_WRAP_PS3__T8C0(n) (((n) & 0x1) << 4)
|
||||
#define SU_TEX_WRAP_PS3__T8C1(n) (((n) & 0x1) << 5)
|
||||
#define SU_TEX_WRAP_PS3__T8C2(n) (((n) & 0x1) << 6)
|
||||
#define SU_TEX_WRAP_PS3__T8C3(n) (((n) & 0x1) << 7)
|
||||
#define TX_BORDER_COLOR__BORDER_COLOR(n) (((n) & 0xffffffff) << 0)
|
||||
#define TX_CHROMA_KEY__CHROMA_KEY(n) (((n) & 0xffffffff) << 0)
|
||||
#define TX_ENABLE__TEX_0_ENABLE(n) (((n) & 0x1) << 0)
|
||||
#define TX_ENABLE__TEX_1_ENABLE(n) (((n) & 0x1) << 1)
|
||||
#define TX_ENABLE__TEX_2_ENABLE(n) (((n) & 0x1) << 2)
|
||||
#define TX_ENABLE__TEX_3_ENABLE(n) (((n) & 0x1) << 3)
|
||||
#define TX_ENABLE__TEX_4_ENABLE(n) (((n) & 0x1) << 4)
|
||||
#define TX_ENABLE__TEX_5_ENABLE(n) (((n) & 0x1) << 5)
|
||||
#define TX_ENABLE__TEX_6_ENABLE(n) (((n) & 0x1) << 6)
|
||||
#define TX_ENABLE__TEX_7_ENABLE(n) (((n) & 0x1) << 7)
|
||||
#define TX_ENABLE__TEX_8_ENABLE(n) (((n) & 0x1) << 8)
|
||||
#define TX_ENABLE__TEX_9_ENABLE(n) (((n) & 0x1) << 9)
|
||||
#define TX_ENABLE__TEX_10_ENABLE(n) (((n) & 0x1) << 10)
|
||||
#define TX_ENABLE__TEX_11_ENABLE(n) (((n) & 0x1) << 11)
|
||||
#define TX_ENABLE__TEX_12_ENABLE(n) (((n) & 0x1) << 12)
|
||||
#define TX_ENABLE__TEX_13_ENABLE(n) (((n) & 0x1) << 13)
|
||||
#define TX_ENABLE__TEX_14_ENABLE(n) (((n) & 0x1) << 14)
|
||||
#define TX_ENABLE__TEX_15_ENABLE(n) (((n) & 0x1) << 15)
|
||||
#define TX_FILTER0__CLAMP_S(n) (((n) & 0x7) << 0)
|
||||
#define TX_FILTER0__CLAMP_T(n) (((n) & 0x7) << 3)
|
||||
#define TX_FILTER0__CLAMP_R(n) (((n) & 0x7) << 6)
|
||||
#define TX_FILTER0__MAG_FILTER(n) (((n) & 0x3) << 9)
|
||||
#define TX_FILTER0__MIN_FILTER(n) (((n) & 0x3) << 11)
|
||||
#define TX_FILTER0__MIP_FILTER(n) (((n) & 0x3) << 13)
|
||||
#define TX_FILTER0__VOL_FILTER(n) (((n) & 0x3) << 15)
|
||||
#define TX_FILTER0__MAX_MIP_LEVEL(n) (((n) & 0xf) << 17)
|
||||
#define TX_FILTER0__ID(n) (((n) & 0xf) << 28)
|
||||
#define TX_FILTER1__CHROMA_KEY_MODE(n) (((n) & 0x3) << 0)
|
||||
#define TX_FILTER1__MC_ROUND(n) (((n) & 0x1) << 2)
|
||||
#define TX_FILTER1__LOD_BIAS(n) (((n) & 0x3ff) << 3)
|
||||
#define TX_FILTER1__MC_COORD_TRUNCATE(n) (((n) & 0x1) << 14)
|
||||
#define TX_FILTER1__TRI_PERF(n) (((n) & 0x3) << 15)
|
||||
#define TX_FILTER1__MACRO_SWITCH(n) (((n) & 0x1) << 22)
|
||||
#define TX_FILTER1__BORDER_FIX(n) (((n) & 0x1) << 31)
|
||||
#define TX_FILTER4__WEIGHT_1(n) (((n) & 0x7ff) << 0)
|
||||
#define TX_FILTER4__WEIGHT_0(n) (((n) & 0x7ff) << 11)
|
||||
#define TX_FILTER4__WEIGHT_PAIR(n) (((n) & 0x1) << 22)
|
||||
#define TX_FILTER4__PHASE(n) (((n) & 0xf) << 23)
|
||||
#define TX_FILTER4__DIRECTION(n) (((n) & 0x1) << 27)
|
||||
#define TX_FORMAT0__TXWIDTH(n) (((n) & 0x7ff) << 0)
|
||||
#define TX_FORMAT0__TXHEIGHT(n) (((n) & 0x7ff) << 11)
|
||||
#define TX_FORMAT0__TXDEPTH(n) (((n) & 0xf) << 22)
|
||||
#define TX_FORMAT0__NUM_LEVELS(n) (((n) & 0xf) << 26)
|
||||
#define TX_FORMAT0__PROJECTED(n) (((n) & 0x1) << 30)
|
||||
#define TX_FORMAT0__TXPITCH_EN(n) (((n) & 0x1) << 31)
|
||||
#define TX_FORMAT1__TXFORMAT(n) (((n) & 0x1f) << 0)
|
||||
#define TX_FORMAT1__SIGNED_COMP0(n) (((n) & 0x1) << 5)
|
||||
#define TX_FORMAT1__SIGNED_COMP1(n) (((n) & 0x1) << 6)
|
||||
#define TX_FORMAT1__SIGNED_COMP2(n) (((n) & 0x1) << 7)
|
||||
#define TX_FORMAT1__SIGNED_COMP3(n) (((n) & 0x1) << 8)
|
||||
#define TX_FORMAT1__SEL_ALPHA(n) (((n) & 0x7) << 9)
|
||||
#define TX_FORMAT1__SEL_RED(n) (((n) & 0x7) << 12)
|
||||
#define TX_FORMAT1__SEL_GREEN(n) (((n) & 0x7) << 15)
|
||||
#define TX_FORMAT1__SEL_BLUE(n) (((n) & 0x7) << 18)
|
||||
#define TX_FORMAT1__GAMMA(n) (((n) & 0x1) << 21)
|
||||
#define TX_FORMAT1__YUV_TO_RGB(n) (((n) & 0x3) << 22)
|
||||
#define TX_FORMAT1__SWAP_YUV(n) (((n) & 0x1) << 24)
|
||||
#define TX_FORMAT1__TEX_COORD_TYPE(n) (((n) & 0x3) << 25)
|
||||
#define TX_FORMAT1__CACHE(n) (((n) & 0x1f) << 27)
|
||||
#define TX_FORMAT2__TXPITCH(n) (((n) & 0x3fff) << 0)
|
||||
#define TX_FORMAT2__TXFORMAT_MSB(n) (((n) & 0x1) << 14)
|
||||
#define TX_FORMAT2__TXWIDTH_11(n) (((n) & 0x1) << 15)
|
||||
#define TX_FORMAT2__TXHEIGHT_11(n) (((n) & 0x1) << 16)
|
||||
#define TX_FORMAT2__POW2FIX2FLT(n) (((n) & 0x1) << 17)
|
||||
#define TX_FORMAT2__SEL_FILTER4(n) (((n) & 0x3) << 18)
|
||||
#define TX_INVALTAGS__RESERVED(n) (((n) & 0xffffffff) << 0)
|
||||
#define TX_OFFSET__ENDIAN_SWAP(n) (((n) & 0x3) << 0)
|
||||
#define TX_OFFSET__MACRO_TILE(n) (((n) & 0x1) << 2)
|
||||
#define TX_OFFSET__MICRO_TILE(n) (((n) & 0x3) << 3)
|
||||
#define TX_OFFSET__TXOFFSET(n) (((n) & 0x7ffffff) << 5)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR0(n) (((n) & 0xff) << 0)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR0_CONST(n) (((n) & 0x1) << 8)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR0_REL(n) (((n) & 0x1) << 9)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR1(n) (((n) & 0xff) << 10)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR1_CONST(n) (((n) & 0x1) << 18)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR1_REL(n) (((n) & 0x1) << 19)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR2(n) (((n) & 0xff) << 20)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR2_CONST(n) (((n) & 0x1) << 28)
|
||||
#define US_ALU_ALPHA_ADDR__ADDR2_REL(n) (((n) & 0x1) << 29)
|
||||
#define US_ALU_ALPHA_ADDR__SRCP_OP(n) (((n) & 0x3) << 30)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_OP(n) (((n) & 0xf) << 0)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_ADDRD(n) (((n) & 0x7f) << 4)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_ADDRD_REL(n) (((n) & 0x1) << 11)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_SEL_A(n) (((n) & 0x3) << 12)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_SWIZ_A(n) (((n) & 0x7) << 14)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_MOD_A(n) (((n) & 0x3) << 17)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_SEL_B(n) (((n) & 0x3) << 19)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_SWIZ_B(n) (((n) & 0x7) << 21)
|
||||
#define US_ALU_ALPHA_INST__ALPHA_MOD_B(n) (((n) & 0x3) << 24)
|
||||
#define US_ALU_ALPHA_INST__OMOD(n) (((n) & 0x7) << 26)
|
||||
#define US_ALU_ALPHA_INST__TARGET(n) (((n) & 0x3) << 29)
|
||||
#define US_ALU_ALPHA_INST__W_OMASK(n) (((n) & 0x1) << 31)
|
||||
#define US_ALU_RGB_ADDR__ADDR0(n) (((n) & 0xff) << 0)
|
||||
#define US_ALU_RGB_ADDR__ADDR0_CONST(n) (((n) & 0x1) << 8)
|
||||
#define US_ALU_RGB_ADDR__ADDR0_REL(n) (((n) & 0x1) << 9)
|
||||
#define US_ALU_RGB_ADDR__ADDR1(n) (((n) & 0xff) << 10)
|
||||
#define US_ALU_RGB_ADDR__ADDR1_CONST(n) (((n) & 0x1) << 18)
|
||||
#define US_ALU_RGB_ADDR__ADDR1_REL(n) (((n) & 0x1) << 19)
|
||||
#define US_ALU_RGB_ADDR__ADDR2(n) (((n) & 0xff) << 20)
|
||||
#define US_ALU_RGB_ADDR__ADDR2_CONST(n) (((n) & 0x1) << 28)
|
||||
#define US_ALU_RGB_ADDR__ADDR2_REL(n) (((n) & 0x1) << 29)
|
||||
#define US_ALU_RGB_ADDR__SRCP_OP(n) (((n) & 0x3) << 30)
|
||||
#define US_ALU_RGB_INST__RGB_SEL_A(n) (((n) & 0x3) << 0)
|
||||
#define US_ALU_RGB_INST__RED_SWIZ_A(n) (((n) & 0x7) << 2)
|
||||
#define US_ALU_RGB_INST__GREEN_SWIZ_A(n) (((n) & 0x7) << 5)
|
||||
#define US_ALU_RGB_INST__BLUE_SWIZ_A(n) (((n) & 0x7) << 8)
|
||||
#define US_ALU_RGB_INST__RGB_MOD_A(n) (((n) & 0x3) << 11)
|
||||
#define US_ALU_RGB_INST__RGB_SEL_B(n) (((n) & 0x3) << 13)
|
||||
#define US_ALU_RGB_INST__RED_SWIZ_B(n) (((n) & 0x7) << 15)
|
||||
#define US_ALU_RGB_INST__GREEN_SWIZ_B(n) (((n) & 0x7) << 18)
|
||||
#define US_ALU_RGB_INST__BLUE_SWIZ_B(n) (((n) & 0x7) << 21)
|
||||
#define US_ALU_RGB_INST__RGB_MOD_B(n) (((n) & 0x3) << 24)
|
||||
#define US_ALU_RGB_INST__OMOD(n) (((n) & 0x7) << 26)
|
||||
#define US_ALU_RGB_INST__TARGET(n) (((n) & 0x3) << 29)
|
||||
#define US_ALU_RGB_INST__ALU_WMASK(n) (((n) & 0x1) << 31)
|
||||
#define US_ALU_RGBA_INST__RGB_OP(n) (((n) & 0xf) << 0)
|
||||
#define US_ALU_RGBA_INST__RGB_ADDRD(n) (((n) & 0x7f) << 4)
|
||||
#define US_ALU_RGBA_INST__RGB_ADDRD_REL(n) (((n) & 0x1) << 11)
|
||||
#define US_ALU_RGBA_INST__RGB_SEL_C(n) (((n) & 0x3) << 12)
|
||||
#define US_ALU_RGBA_INST__RED_SWIZ_C(n) (((n) & 0x7) << 14)
|
||||
#define US_ALU_RGBA_INST__GREEN_SWIZ_C(n) (((n) & 0x7) << 17)
|
||||
#define US_ALU_RGBA_INST__BLUE_SWIZ_C(n) (((n) & 0x7) << 20)
|
||||
#define US_ALU_RGBA_INST__RGB_MOD_C(n) (((n) & 0x3) << 23)
|
||||
#define US_ALU_RGBA_INST__ALPHA_SEL_C(n) (((n) & 0x3) << 25)
|
||||
#define US_ALU_RGBA_INST__ALPHA_SWIZ_C(n) (((n) & 0x7) << 27)
|
||||
#define US_ALU_RGBA_INST__ALPHA_MOD_C(n) (((n) & 0x3) << 30)
|
||||
#define US_CMN_INST__TYPE(n) (((n) & 0x3) << 0)
|
||||
#define US_CMN_INST__TEX_SEM_WAIT(n) (((n) & 0x1) << 2)
|
||||
#define US_CMN_INST__RGB_PRED_SEL(n) (((n) & 0x7) << 3)
|
||||
#define US_CMN_INST__RGB_PRED_INV(n) (((n) & 0x1) << 6)
|
||||
#define US_CMN_INST__WRITE_INACTIVE(n) (((n) & 0x1) << 7)
|
||||
#define US_CMN_INST__LAST(n) (((n) & 0x1) << 8)
|
||||
#define US_CMN_INST__NOP(n) (((n) & 0x1) << 9)
|
||||
#define US_CMN_INST__ALU_WAIT(n) (((n) & 0x1) << 10)
|
||||
#define US_CMN_INST__RGB_WMASK(n) (((n) & 0x7) << 11)
|
||||
#define US_CMN_INST__ALPHA_WMASK(n) (((n) & 0x1) << 14)
|
||||
#define US_CMN_INST__RGB_OMASK(n) (((n) & 0x7) << 15)
|
||||
#define US_CMN_INST__ALPHA_OMASK(n) (((n) & 0x1) << 18)
|
||||
#define US_CMN_INST__RGB_CLAMP(n) (((n) & 0x1) << 19)
|
||||
#define US_CMN_INST__ALPHA_CLAMP(n) (((n) & 0x1) << 20)
|
||||
#define US_CMN_INST__ALU_RESULT_SEL(n) (((n) & 0x1) << 21)
|
||||
#define US_CMN_INST__ALPHA_PRED_INV(n) (((n) & 0x1) << 22)
|
||||
#define US_CMN_INST__ALU_RESULT_OP(n) (((n) & 0x3) << 23)
|
||||
#define US_CMN_INST__ALPHA_PRED_SEL(n) (((n) & 0x7) << 25)
|
||||
#define US_CMN_INST__STAT_WE(n) (((n) & 0xf) << 28)
|
||||
#define US_CODE_ADDR__START_ADDR(n) (((n) & 0x1ff) << 0)
|
||||
#define US_CODE_ADDR__END_ADDR(n) (((n) & 0x1ff) << 16)
|
||||
#define US_CODE_OFFSET__OFFSET_ADDR(n) (((n) & 0x1ff) << 0)
|
||||
#define US_CODE_RANGE__CODE_ADDR(n) (((n) & 0x1ff) << 0)
|
||||
#define US_CODE_RANGE__CODE_SIZE(n) (((n) & 0x1ff) << 16)
|
||||
#define US_CONFIG__ZERO_TIMES_ANYTHING_EQUALS_ZERO(n) (((n) & 0x1) << 1)
|
||||
#define US_FC_ADDR__BOOL_ADDR(n) (((n) & 0x1f) << 0)
|
||||
#define US_FC_ADDR__INT_ADDR(n) (((n) & 0x1f) << 8)
|
||||
#define US_FC_ADDR__JUMP_ADDR(n) (((n) & 0x1ff) << 16)
|
||||
#define US_FC_ADDR__JUMP_GLOBAL(n) (((n) & 0x1) << 31)
|
||||
#define US_FC_BOOL_CONST__KBOOL(n) (((n) & 0xffffffff) << 0)
|
||||
#define US_FC_CTRL__TEST_EN(n) (((n) & 0x1) << 30)
|
||||
#define US_FC_CTRL__FULL_FC_EN(n) (((n) & 0x1) << 31)
|
||||
#define US_FC_INST__OP(n) (((n) & 0x7) << 0)
|
||||
#define US_FC_INST__B_ELSE(n) (((n) & 0x1) << 4)
|
||||
#define US_FC_INST__JUMP_ANY(n) (((n) & 0x1) << 5)
|
||||
#define US_FC_INST__A_OP(n) (((n) & 0x3) << 6)
|
||||
#define US_FC_INST__JUMP_FUNC(n) (((n) & 0xff) << 8)
|
||||
#define US_FC_INST__B_POP_CNT(n) (((n) & 0x1f) << 16)
|
||||
#define US_FC_INST__B_OP0(n) (((n) & 0x3) << 24)
|
||||
#define US_FC_INST__B_OP1(n) (((n) & 0x3) << 26)
|
||||
#define US_FC_INST__IGNORE_UNCOVERED(n) (((n) & 0x1) << 28)
|
||||
#define US_FC_INT_CONST__KR(n) (((n) & 0xff) << 0)
|
||||
#define US_FC_INT_CONST__KG(n) (((n) & 0xff) << 8)
|
||||
#define US_FC_INT_CONST__KB(n) (((n) & 0xff) << 16)
|
||||
#define US_FORMAT__TXWIDTH(n) (((n) & 0x7ff) << 0)
|
||||
#define US_FORMAT__TXHEIGHT(n) (((n) & 0x7ff) << 11)
|
||||
#define US_OUT_FMT__OUT_FMT(n) (((n) & 0x1f) << 0)
|
||||
#define US_OUT_FMT__C0_SEL(n) (((n) & 0x3) << 8)
|
||||
#define US_OUT_FMT__C1_SEL(n) (((n) & 0x3) << 10)
|
||||
#define US_OUT_FMT__C2_SEL(n) (((n) & 0x3) << 12)
|
||||
#define US_OUT_FMT__C3_SEL(n) (((n) & 0x3) << 14)
|
||||
#define US_OUT_FMT__OUT_SIGN(n) (((n) & 0xf) << 16)
|
||||
#define US_PIXSIZE__PIX_SIZE(n) (((n) & 0x7f) << 0)
|
||||
#define US_TEX_ADDR__SRC_ADDR(n) (((n) & 0x7f) << 0)
|
||||
#define US_TEX_ADDR__SRC_ADDR_REL(n) (((n) & 0x1) << 7)
|
||||
#define US_TEX_ADDR__SRC_S_SWIZ(n) (((n) & 0x3) << 8)
|
||||
#define US_TEX_ADDR__SRC_T_SWIZ(n) (((n) & 0x3) << 10)
|
||||
#define US_TEX_ADDR__SRC_R_SWIZ(n) (((n) & 0x3) << 12)
|
||||
#define US_TEX_ADDR__SRC_Q_SWIZ(n) (((n) & 0x3) << 14)
|
||||
#define US_TEX_ADDR__DST_ADDR(n) (((n) & 0x7f) << 16)
|
||||
#define US_TEX_ADDR__DST_ADDR_REL(n) (((n) & 0x1) << 23)
|
||||
#define US_TEX_ADDR__DST_R_SWIZ(n) (((n) & 0x3) << 24)
|
||||
#define US_TEX_ADDR__DST_G_SWIZ(n) (((n) & 0x3) << 26)
|
||||
#define US_TEX_ADDR__DST_B_SWIZ(n) (((n) & 0x3) << 28)
|
||||
#define US_TEX_ADDR__DST_A_SWIZ(n) (((n) & 0x3) << 30)
|
||||
#define US_TEX_ADDR_DXDY__DX_ADDR(n) (((n) & 0x7f) << 0)
|
||||
#define US_TEX_ADDR_DXDY__DX_ADDR_REL(n) (((n) & 0x1) << 7)
|
||||
#define US_TEX_ADDR_DXDY__DX_S_SWIZ(n) (((n) & 0x3) << 8)
|
||||
#define US_TEX_ADDR_DXDY__DX_T_SWIZ(n) (((n) & 0x3) << 10)
|
||||
#define US_TEX_ADDR_DXDY__DX_R_SWIZ(n) (((n) & 0x3) << 12)
|
||||
#define US_TEX_ADDR_DXDY__DX_Q_SWIZ(n) (((n) & 0x3) << 14)
|
||||
#define US_TEX_ADDR_DXDY__DY_ADDR(n) (((n) & 0x7f) << 16)
|
||||
#define US_TEX_ADDR_DXDY__DY_ADDR_REL(n) (((n) & 0x1) << 23)
|
||||
#define US_TEX_ADDR_DXDY__DY_S_SWIZ(n) (((n) & 0x3) << 24)
|
||||
#define US_TEX_ADDR_DXDY__DY_T_SWIZ(n) (((n) & 0x3) << 26)
|
||||
#define US_TEX_ADDR_DXDY__DY_R_SWIZ(n) (((n) & 0x3) << 28)
|
||||
#define US_TEX_ADDR_DXDY__DY_Q_SWIZ(n) (((n) & 0x3) << 30)
|
||||
#define US_TEX_INST__TEX_ID(n) (((n) & 0xf) << 16)
|
||||
#define US_TEX_INST__INST(n) (((n) & 0x7) << 22)
|
||||
#define US_TEX_INST__TEX_SEM_ACQUIRE(n) (((n) & 0x1) << 25)
|
||||
#define US_TEX_INST__IGNORE_UNCOVERED(n) (((n) & 0x1) << 26)
|
||||
#define US_TEX_INST__UNSCALED(n) (((n) & 0x1) << 27)
|
||||
#define US_W_FMT__W_FMT(n) (((n) & 0x3) << 0)
|
||||
#define US_W_FMT__W_SRC(n) (((n) & 0x1) << 2)
|
||||
#define VAP_ALT_NUM_VERTICES__NUM_VERTICES(n) (((n) & 0xffffff) << 0)
|
||||
#define VAP_CLIP_CNTL__UCP_ENA_0(n) (((n) & 0x1) << 0)
|
||||
#define VAP_CLIP_CNTL__UCP_ENA_1(n) (((n) & 0x1) << 1)
|
||||
#define VAP_CLIP_CNTL__UCP_ENA_2(n) (((n) & 0x1) << 2)
|
||||
#define VAP_CLIP_CNTL__UCP_ENA_3(n) (((n) & 0x1) << 3)
|
||||
#define VAP_CLIP_CNTL__UCP_ENA_4(n) (((n) & 0x1) << 4)
|
||||
#define VAP_CLIP_CNTL__UCP_ENA_5(n) (((n) & 0x1) << 5)
|
||||
#define VAP_CLIP_CNTL__PS_UCP_MODE(n) (((n) & 0x3) << 14)
|
||||
#define VAP_CLIP_CNTL__CLIP_DISABLE(n) (((n) & 0x1) << 16)
|
||||
#define VAP_CLIP_CNTL__UCP_CULL_ONLY_ENA(n) (((n) & 0x1) << 17)
|
||||
#define VAP_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA(n) (((n) & 0x1) << 18)
|
||||
#define VAP_CLIP_CNTL__COLOR2_IS_TEXTURE(n) (((n) & 0x1) << 20)
|
||||
#define VAP_CLIP_CNTL__COLOR3_IS_TEXTURE(n) (((n) & 0x1) << 21)
|
||||
#define VAP_CNTL__PVS_NUM_SLOTS(n) (((n) & 0xf) << 0)
|
||||
#define VAP_CNTL__PVS_NUM_CNTLRS(n) (((n) & 0xf) << 4)
|
||||
#define VAP_CNTL__PVS_NUM_FPUS(n) (((n) & 0xf) << 8)
|
||||
#define VAP_CNTL__VAP_NO_RENDER(n) (((n) & 0x1) << 17)
|
||||
#define VAP_CNTL__VF_MAX_VTX_NUM(n) (((n) & 0xf) << 18)
|
||||
#define VAP_CNTL__DX_CLIP_SPACE_DEF(n) (((n) & 0x1) << 22)
|
||||
#define VAP_CNTL__TCL_STATE_OPTIMIZATION(n) (((n) & 0x1) << 23)
|
||||
#define VAP_CNTL_STATUS__VC_SWAP(n) (((n) & 0x3) << 0)
|
||||
#define VAP_CNTL_STATUS__PVS_BYPASS(n) (((n) & 0x1) << 8)
|
||||
#define VAP_CNTL_STATUS__PVS_BUSY(n) (((n) & 0x1) << 11)
|
||||
#define VAP_CNTL_STATUS__MAX_MPS(n) (((n) & 0xf) << 16)
|
||||
#define VAP_CNTL_STATUS__VS_BUSY(n) (((n) & 0x1) << 24)
|
||||
#define VAP_CNTL_STATUS__RCP_BUSY(n) (((n) & 0x1) << 25)
|
||||
#define VAP_CNTL_STATUS__VTE_BUSY(n) (((n) & 0x1) << 26)
|
||||
#define VAP_CNTL_STATUS__MIU_BUSY(n) (((n) & 0x1) << 27)
|
||||
#define VAP_CNTL_STATUS__VC_BUSY(n) (((n) & 0x1) << 28)
|
||||
#define VAP_CNTL_STATUS__VF_BUSY(n) (((n) & 0x1) << 29)
|
||||
#define VAP_CNTL_STATUS__REGPIPE_BUSY(n) (((n) & 0x1) << 30)
|
||||
#define VAP_CNTL_STATUS__VAP_BUSY(n) (((n) & 0x1) << 31)
|
||||
#define VAP_GB_HORZ_CLIP_ADJ__DATA_REGISTER(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_GB_HORZ_DISC_ADJ__DATA_REGISTER(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_GB_VERT_CLIP_ADJ__DATA_REGISTER(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_GB_VERT_DISC_ADJ__DATA_REGISTER(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_INDEX_OFFSET__INDEX_OFFSET(n) (((n) & 0x1ffffff) << 0)
|
||||
#define VAP_OUT_VTX_FMT_0__VTX_POS_PRESENT(n) (((n) & 0x1) << 0)
|
||||
#define VAP_OUT_VTX_FMT_0__VTX_COLOR_0_PRESENT(n) (((n) & 0x1) << 1)
|
||||
#define VAP_OUT_VTX_FMT_0__VTX_COLOR_1_PRESENT(n) (((n) & 0x1) << 2)
|
||||
#define VAP_OUT_VTX_FMT_0__VTX_COLOR_2_PRESENT(n) (((n) & 0x1) << 3)
|
||||
#define VAP_OUT_VTX_FMT_0__VTX_COLOR_3_PRESENT(n) (((n) & 0x1) << 4)
|
||||
#define VAP_OUT_VTX_FMT_0__VTX_PT_SIZE_PRESENT(n) (((n) & 0x1) << 16)
|
||||
#define VAP_OUT_VTX_FMT_1__TEX_0_COMP_CNT(n) (((n) & 0x7) << 0)
|
||||
#define VAP_OUT_VTX_FMT_1__TEX_1_COMP_CNT(n) (((n) & 0x7) << 3)
|
||||
#define VAP_OUT_VTX_FMT_1__TEX_2_COMP_CNT(n) (((n) & 0x7) << 6)
|
||||
#define VAP_OUT_VTX_FMT_1__TEX_3_COMP_CNT(n) (((n) & 0x7) << 9)
|
||||
#define VAP_OUT_VTX_FMT_1__TEX_4_COMP_CNT(n) (((n) & 0x7) << 12)
|
||||
#define VAP_OUT_VTX_FMT_1__TEX_5_COMP_CNT(n) (((n) & 0x7) << 15)
|
||||
#define VAP_OUT_VTX_FMT_1__TEX_6_COMP_CNT(n) (((n) & 0x7) << 18)
|
||||
#define VAP_OUT_VTX_FMT_1__TEX_7_COMP_CNT(n) (((n) & 0x7) << 21)
|
||||
#define VAP_PORT_DATA__DATAPORT0(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_PORT_DATA_IDX_128__DATA_IDX_PORT_128(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_PORT_IDX__IDXPORT0(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_PROG_STREAM_CNTL__DATA_TYPE_0(n) (((n) & 0xf) << 0)
|
||||
#define VAP_PROG_STREAM_CNTL__SKIP_DWORDS_0(n) (((n) & 0xf) << 4)
|
||||
#define VAP_PROG_STREAM_CNTL__DST_VEC_LOC_0(n) (((n) & 0x1f) << 8)
|
||||
#define VAP_PROG_STREAM_CNTL__LAST_VEC_0(n) (((n) & 0x1) << 13)
|
||||
#define VAP_PROG_STREAM_CNTL__SIGNED_0(n) (((n) & 0x1) << 14)
|
||||
#define VAP_PROG_STREAM_CNTL__NORMALIZE_0(n) (((n) & 0x1) << 15)
|
||||
#define VAP_PROG_STREAM_CNTL__DATA_TYPE_1(n) (((n) & 0xf) << 16)
|
||||
#define VAP_PROG_STREAM_CNTL__SKIP_DWORDS_1(n) (((n) & 0xf) << 20)
|
||||
#define VAP_PROG_STREAM_CNTL__DST_VEC_LOC_1(n) (((n) & 0x1f) << 24)
|
||||
#define VAP_PROG_STREAM_CNTL__LAST_VEC_1(n) (((n) & 0x1) << 29)
|
||||
#define VAP_PROG_STREAM_CNTL__SIGNED_1(n) (((n) & 0x1) << 30)
|
||||
#define VAP_PROG_STREAM_CNTL__NORMALIZE_1(n) (((n) & 0x1) << 31)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_X_0(n) (((n) & 0x7) << 0)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Y_0(n) (((n) & 0x7) << 3)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Z_0(n) (((n) & 0x7) << 6)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_W_0(n) (((n) & 0x7) << 9)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__WRITE_ENA_0(n) (((n) & 0xf) << 12)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_X_1(n) (((n) & 0x7) << 16)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Y_1(n) (((n) & 0x7) << 19)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Z_1(n) (((n) & 0x7) << 22)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_W_1(n) (((n) & 0x7) << 25)
|
||||
#define VAP_PROG_STREAM_CNTL_EXT__WRITE_ENA_1(n) (((n) & 0xf) << 28)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_0(n) (((n) & 0x3) << 0)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_1(n) (((n) & 0x3) << 2)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_2(n) (((n) & 0x3) << 4)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_3(n) (((n) & 0x3) << 6)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_4(n) (((n) & 0x3) << 8)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_5(n) (((n) & 0x3) << 10)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_6(n) (((n) & 0x3) << 12)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_7(n) (((n) & 0x3) << 14)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_8(n) (((n) & 0x3) << 16)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_9(n) (((n) & 0x3) << 18)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_10(n) (((n) & 0x3) << 20)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_11(n) (((n) & 0x3) << 22)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_12(n) (((n) & 0x3) << 24)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_13(n) (((n) & 0x3) << 26)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_14(n) (((n) & 0x3) << 28)
|
||||
#define VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_15(n) (((n) & 0x3) << 30)
|
||||
#define VAP_PVS_CODE_CNTL_0__PVS_FIRST_INST(n) (((n) & 0x3ff) << 0)
|
||||
#define VAP_PVS_CODE_CNTL_0__PVS_XYZW_VALID_INST(n) (((n) & 0x3ff) << 10)
|
||||
#define VAP_PVS_CODE_CNTL_0__PVS_LAST_INST(n) (((n) & 0x3ff) << 20)
|
||||
#define VAP_PVS_CODE_CNTL_1__PVS_LAST_VTX_SRC_INST(n) (((n) & 0x3ff) << 0)
|
||||
#define VAP_PVS_CONST_CNTL__PVS_CONST_BASE_OFFSET(n) (((n) & 0xff) << 0)
|
||||
#define VAP_PVS_CONST_CNTL__PVS_MAX_CONST_ADDR(n) (((n) & 0xff) << 16)
|
||||
#define VAP_PVS_FLOW_CNTL_ADDRS__PVS_FC_ACT_ADRS_0(n) (((n) & 0xff) << 0)
|
||||
#define VAP_PVS_FLOW_CNTL_ADDRS__PVS_FC_LOOP_CNT_JMP_INST_0(n) (((n) & 0xff) << 8)
|
||||
#define VAP_PVS_FLOW_CNTL_ADDRS__PVS_FC_LAST_INST_0(n) (((n) & 0xff) << 16)
|
||||
#define VAP_PVS_FLOW_CNTL_ADDRS__PVS_FC_RTN_INST_0(n) (((n) & 0xff) << 24)
|
||||
#define VAP_PVS_FLOW_CNTL_ADDRS_LW__PVS_FC_ACT_ADRS_0(n) (((n) & 0xffff) << 0)
|
||||
#define VAP_PVS_FLOW_CNTL_ADDRS_LW__PVS_FC_LOOP_CNT_JMP_INST_0(n) (((n) & 0xffff) << 16)
|
||||
#define VAP_PVS_FLOW_CNTL_ADDRS_UW__PVS_FC_LAST_INST_0(n) (((n) & 0xffff) << 0)
|
||||
#define VAP_PVS_FLOW_CNTL_ADDRS_UW__PVS_FC_RTN_INST_0(n) (((n) & 0xffff) << 16)
|
||||
#define VAP_PVS_FLOW_CNTL_LOOP_INDEX__PVS_FC_LOOP_INIT_VAL_0(n) (((n) & 0xff) << 0)
|
||||
#define VAP_PVS_FLOW_CNTL_LOOP_INDEX__PVS_FC_LOOP_STEP_VAL_0(n) (((n) & 0xff) << 8)
|
||||
#define VAP_PVS_FLOW_CNTL_LOOP_INDEX__PVS_FC_LOOP_REPEAT_NO_FLI_0(n) (((n) & 0x1) << 31)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_0(n) (((n) & 0x3) << 0)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_1(n) (((n) & 0x3) << 2)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_2(n) (((n) & 0x3) << 4)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_3(n) (((n) & 0x3) << 6)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_4(n) (((n) & 0x3) << 8)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_5(n) (((n) & 0x3) << 10)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_6(n) (((n) & 0x3) << 12)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_7(n) (((n) & 0x3) << 14)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_8(n) (((n) & 0x3) << 16)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_9(n) (((n) & 0x3) << 18)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_10(n) (((n) & 0x3) << 20)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_11(n) (((n) & 0x3) << 22)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_12(n) (((n) & 0x3) << 24)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_13(n) (((n) & 0x3) << 26)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_14(n) (((n) & 0x3) << 28)
|
||||
#define VAP_PVS_FLOW_CNTL_OPC__PVS_FC_OPC_15(n) (((n) & 0x3) << 30)
|
||||
#define VAP_PVS_STATE_FLUSH_REG__DATA_REGISTER(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_PVS_VECTOR_DATA_REG__DATA_REGISTER(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_PVS_VECTOR_DATA_REG_128__DATA_REGISTER(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_PVS_VECTOR_INDX_REG__OCTWORD_OFFSET(n) (((n) & 0x7ff) << 0)
|
||||
#define VAP_PVS_VTX_TIMEOUT_REG__CLK_COUNT(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGB_SHADE_FUNC_0(n) (((n) & 0x1) << 0)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_ALPHA_SHADE_FUNC_0(n) (((n) & 0x1) << 1)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGBA_CLAMP_0(n) (((n) & 0x1) << 2)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGB_SHADE_FUNC_1(n) (((n) & 0x1) << 4)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_ALPHA_SHADE_FUNC_1(n) (((n) & 0x1) << 5)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGBA_CLAMP_1(n) (((n) & 0x1) << 6)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGB_SHADE_FUNC_2(n) (((n) & 0x1) << 8)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_ALPHA_SHADE_FUNC_2(n) (((n) & 0x1) << 9)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGBA_CLAMP_2(n) (((n) & 0x1) << 10)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGB_SHADE_FUNC_3(n) (((n) & 0x1) << 12)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_ALPHA_SHADE_FUNC_3(n) (((n) & 0x1) << 13)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGBA_CLAMP_3(n) (((n) & 0x1) << 14)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGB_SHADE_FUNC_4(n) (((n) & 0x1) << 16)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_ALPHA_SHADE_FUNC_4(n) (((n) & 0x1) << 17)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGBA_CLAMP_4(n) (((n) & 0x1) << 18)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGB_SHADE_FUNC_5(n) (((n) & 0x1) << 20)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_ALPHA_SHADE_FUNC_5(n) (((n) & 0x1) << 21)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGBA_CLAMP_5(n) (((n) & 0x1) << 22)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGB_SHADE_FUNC_6(n) (((n) & 0x1) << 24)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_ALPHA_SHADE_FUNC_6(n) (((n) & 0x1) << 25)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGBA_CLAMP_6(n) (((n) & 0x1) << 26)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGB_SHADE_FUNC_7(n) (((n) & 0x1) << 28)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_ALPHA_SHADE_FUNC_7(n) (((n) & 0x1) << 29)
|
||||
#define VAP_TEX_TO_COLOR_CNTL__TEX_RGBA_CLAMP_7(n) (((n) & 0x1) << 30)
|
||||
#define VAP_VF_CNTL__PRIM_TYPE(n) (((n) & 0xf) << 0)
|
||||
#define VAP_VF_CNTL__PRIM_WALK(n) (((n) & 0x3) << 4)
|
||||
#define VAP_VF_CNTL__INDEX_SIZE(n) (((n) & 0x1) << 11)
|
||||
#define VAP_VF_CNTL__VTX_REUSE_DIS(n) (((n) & 0x1) << 12)
|
||||
#define VAP_VF_CNTL__DUAL_INDEX_MODE(n) (((n) & 0x1) << 13)
|
||||
#define VAP_VF_CNTL__USE_ALT_NUM_VERTS(n) (((n) & 0x1) << 14)
|
||||
#define VAP_VF_CNTL__NUM_VERTICES(n) (((n) & 0xffff) << 16)
|
||||
#define VAP_VF_MAX_VTX_INDX__MAX_INDX(n) (((n) & 0xffffff) << 0)
|
||||
#define VAP_VF_MIN_VTX_INDX__MIN_INDX(n) (((n) & 0xffffff) << 0)
|
||||
#define VAP_VPORT_XOFFSET__VPORT_XOFFSET(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_VPORT_XSCALE__VPORT_XSCALE(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_VPORT_YOFFSET__VPORT_YOFFSET(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_VPORT_YSCALE__VPORT_YSCALE(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_VPORT_ZOFFSET__VPORT_ZOFFSET(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_VPORT_ZSCALE__VPORT_ZSCALE(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_VTE_CNTL__VPORT_X_SCALE_ENA(n) (((n) & 0x1) << 0)
|
||||
#define VAP_VTE_CNTL__VPORT_X_OFFSET_ENA(n) (((n) & 0x1) << 1)
|
||||
#define VAP_VTE_CNTL__VPORT_Y_SCALE_ENA(n) (((n) & 0x1) << 2)
|
||||
#define VAP_VTE_CNTL__VPORT_Y_OFFSET_ENA(n) (((n) & 0x1) << 3)
|
||||
#define VAP_VTE_CNTL__VPORT_Z_SCALE_ENA(n) (((n) & 0x1) << 4)
|
||||
#define VAP_VTE_CNTL__VPORT_Z_OFFSET_ENA(n) (((n) & 0x1) << 5)
|
||||
#define VAP_VTE_CNTL__VTX_XY_FMT(n) (((n) & 0x1) << 8)
|
||||
#define VAP_VTE_CNTL__VTX_Z_FMT(n) (((n) & 0x1) << 9)
|
||||
#define VAP_VTE_CNTL__VTX_W0_FMT(n) (((n) & 0x1) << 10)
|
||||
#define VAP_VTE_CNTL__SERIAL_PROC_ENA(n) (((n) & 0x1) << 11)
|
||||
#define VAP_VTX_AOS_ADDR__VTX_AOS_ADDR0(n) (((n) & 0x3fffffff) << 2)
|
||||
#define VAP_VTX_AOS_ATTR__VTX_AOS_COUNT0(n) (((n) & 0x7f) << 0)
|
||||
#define VAP_VTX_AOS_ATTR__VTX_AOS_STRIDE0(n) (((n) & 0x7f) << 8)
|
||||
#define VAP_VTX_AOS_ATTR__VTX_AOS_COUNT1(n) (((n) & 0x7f) << 16)
|
||||
#define VAP_VTX_AOS_ATTR__VTX_AOS_STRIDE1(n) (((n) & 0x7f) << 24)
|
||||
#define VAP_VTX_NUM_ARRAYS__VTX_NUM_ARRAYS(n) (((n) & 0x1f) << 0)
|
||||
#define VAP_VTX_NUM_ARRAYS__VC_FORCE_PREFETCH(n) (((n) & 0x1) << 5)
|
||||
#define VAP_VTX_NUM_ARRAYS__VC_DIS_CACHE_INVLD(n) (((n) & 0x1) << 6)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_0_FETCH_SIZE(n) (((n) & 0x1) << 16)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_1_FETCH_SIZE(n) (((n) & 0x1) << 17)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_2_FETCH_SIZE(n) (((n) & 0x1) << 18)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_3_FETCH_SIZE(n) (((n) & 0x1) << 19)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_4_FETCH_SIZE(n) (((n) & 0x1) << 20)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_5_FETCH_SIZE(n) (((n) & 0x1) << 21)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_6_FETCH_SIZE(n) (((n) & 0x1) << 22)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_7_FETCH_SIZE(n) (((n) & 0x1) << 23)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_8_FETCH_SIZE(n) (((n) & 0x1) << 24)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_9_FETCH_SIZE(n) (((n) & 0x1) << 25)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_10_FETCH_SIZE(n) (((n) & 0x1) << 26)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_11_FETCH_SIZE(n) (((n) & 0x1) << 27)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_12_FETCH_SIZE(n) (((n) & 0x1) << 28)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_13_FETCH_SIZE(n) (((n) & 0x1) << 29)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_14_FETCH_SIZE(n) (((n) & 0x1) << 30)
|
||||
#define VAP_VTX_NUM_ARRAYS__AOS_15_FETCH_SIZE(n) (((n) & 0x1) << 31)
|
||||
#define VAP_VTX_SIZE__DWORDS_PER_VTX(n) (((n) & 0x7f) << 0)
|
||||
#define VAP_VTX_ST_BLEND_WT__DATA_REGISTER(n) (((n) & 0xffffffff) << 0)
|
||||
#define VAP_VTX_STATE_CNTL__COLOR_0_ASSEMBLY_CNTL(n) (((n) & 0x3) << 0)
|
||||
#define VAP_VTX_STATE_CNTL__COLOR_1_ASSEMBLY_CNTL(n) (((n) & 0x3) << 2)
|
||||
#define VAP_VTX_STATE_CNTL__COLOR_2_ASSEMBLY_CNTL(n) (((n) & 0x3) << 4)
|
||||
#define VAP_VTX_STATE_CNTL__COLOR_3_ASSEMBLY_CNTL(n) (((n) & 0x3) << 6)
|
||||
#define VAP_VTX_STATE_CNTL__COLOR_4_ASSEMBLY_CNTL(n) (((n) & 0x3) << 8)
|
||||
#define VAP_VTX_STATE_CNTL__COLOR_5_ASSEMBLY_CNTL(n) (((n) & 0x3) << 10)
|
||||
#define VAP_VTX_STATE_CNTL__COLOR_6_ASSEMBLY_CNTL(n) (((n) & 0x3) << 12)
|
||||
#define VAP_VTX_STATE_CNTL__COLOR_7_ASSEMBLY_CNTL(n) (((n) & 0x3) << 14)
|
||||
#define VAP_VTX_STATE_CNTL__UPDATE_USER_COLOR_0_ENA(n) (((n) & 0x1) << 16)
|
||||
#define ZB_BW_CNTL__HIZ_ENABLE(n) (((n) & 0x1) << 0)
|
||||
#define ZB_BW_CNTL__HIZ_MIN(n) (((n) & 0x1) << 1)
|
||||
#define ZB_BW_CNTL__FAST_FILL(n) (((n) & 0x1) << 2)
|
||||
#define ZB_BW_CNTL__RD_COMP_ENABLE(n) (((n) & 0x1) << 3)
|
||||
#define ZB_BW_CNTL__WR_COMP_ENABLE(n) (((n) & 0x1) << 4)
|
||||
#define ZB_BW_CNTL__ZB_CB_CLEAR(n) (((n) & 0x1) << 5)
|
||||
#define ZB_BW_CNTL__FORCE_COMPRESSED_STENCIL_VALUE(n) (((n) & 0x1) << 6)
|
||||
#define ZB_BW_CNTL__ZEQUAL_OPTIMIZE_DISABLE(n) (((n) & 0x1) << 7)
|
||||
#define ZB_BW_CNTL__SEQUAL_OPTIMIZE_DISABLE(n) (((n) & 0x1) << 8)
|
||||
#define ZB_BW_CNTL__BMASK_DISABLE(n) (((n) & 0x1) << 10)
|
||||
#define ZB_BW_CNTL__HIZ_EQUAL_REJECT_ENABLE(n) (((n) & 0x1) << 11)
|
||||
#define ZB_BW_CNTL__HIZ_FP_EXP_BITS(n) (((n) & 0x7) << 12)
|
||||
#define ZB_BW_CNTL__HIZ_FP_INVERT(n) (((n) & 0x1) << 15)
|
||||
#define ZB_BW_CNTL__TILE_OVERWRITE_RECOMPRESSION_DISABLE(n) (((n) & 0x1) << 16)
|
||||
#define ZB_BW_CNTL__CONTIGUOUS_6XAA_SAMPLES_DISABLE(n) (((n) & 0x1) << 17)
|
||||
#define ZB_BW_CNTL__PEQ_PACKING_ENABLE(n) (((n) & 0x1) << 18)
|
||||
#define ZB_BW_CNTL__COVERED_PTR_MASKING_ENABLE(n) (((n) & 0x1) << 19)
|
||||
#define ZB_CNTL__STENCIL_ENABLE(n) (((n) & 0x1) << 0)
|
||||
#define ZB_CNTL__Z_ENABLE(n) (((n) & 0x1) << 1)
|
||||
#define ZB_CNTL__ZWRITEENABLE(n) (((n) & 0x1) << 2)
|
||||
#define ZB_CNTL__ZSIGNED_COMPARE(n) (((n) & 0x1) << 3)
|
||||
#define ZB_CNTL__STENCIL_FRONT_BACK(n) (((n) & 0x1) << 4)
|
||||
#define ZB_CNTL__ZSIGNED_MAGNITUDE(n) (((n) & 0x1) << 5)
|
||||
#define ZB_CNTL__STENCIL_REFMASK_FRONT_BACK(n) (((n) & 0x1) << 6)
|
||||
#define ZB_DEPTHCLEARVALUE__DEPTHCLEARVALUE(n) (((n) & 0xffffffff) << 0)
|
||||
#define ZB_DEPTHOFFSET__DEPTHOFFSET(n) (((n) & 0x7ffffff) << 5)
|
||||
#define ZB_DEPTHPITCH__DEPTHPITCH(n) (((n) & 0xfff) << 2)
|
||||
#define ZB_DEPTHPITCH__DEPTHMACROTILE(n) (((n) & 0x1) << 16)
|
||||
#define ZB_DEPTHPITCH__DEPTHMICROTILE(n) (((n) & 0x3) << 17)
|
||||
#define ZB_DEPTHPITCH__DEPTHENDIAN(n) (((n) & 0x3) << 19)
|
||||
#define ZB_DEPTHXY_OFFSET__DEPTHX_OFFSET(n) (((n) & 0x7ff) << 1)
|
||||
#define ZB_DEPTHXY_OFFSET__DEPTHY_OFFSET(n) (((n) & 0x7ff) << 17)
|
||||
#define ZB_FIFO_SIZE__OP_FIFO_SIZE(n) (((n) & 0x3) << 0)
|
||||
#define ZB_FORMAT__DEPTHFORMAT(n) (((n) & 0xf) << 0)
|
||||
#define ZB_FORMAT__INVERT(n) (((n) & 0x1) << 4)
|
||||
#define ZB_FORMAT__PEQ8(n) (((n) & 0x1) << 5)
|
||||
#define ZB_HIZ_DWORD__HIZ_DWORD(n) (((n) & 0xffffffff) << 0)
|
||||
#define ZB_HIZ_OFFSET__HIZ_OFFSET(n) (((n) & 0xffff) << 2)
|
||||
#define ZB_HIZ_PITCH__HIZ_PITCH(n) (((n) & 0x3ff) << 4)
|
||||
#define ZB_HIZ_RDINDEX__HIZ_RDINDEX(n) (((n) & 0xffff) << 2)
|
||||
#define ZB_HIZ_WRINDEX__HIZ_WRINDEX(n) (((n) & 0xffff) << 2)
|
||||
#define ZB_STENCILCNTL__ZFUNC(n) (((n) & 0x7) << 0)
|
||||
#define ZB_STENCILCNTL__STENCILFUNC(n) (((n) & 0x7) << 3)
|
||||
#define ZB_STENCILCNTL__STENCILFAIL(n) (((n) & 0x7) << 6)
|
||||
#define ZB_STENCILCNTL__STENCILZPASS(n) (((n) & 0x7) << 9)
|
||||
#define ZB_STENCILCNTL__STENCILZFAIL(n) (((n) & 0x7) << 12)
|
||||
#define ZB_STENCILCNTL__STENCILFUNC_BF(n) (((n) & 0x7) << 15)
|
||||
#define ZB_STENCILCNTL__STENCILFAIL_BF(n) (((n) & 0x7) << 18)
|
||||
#define ZB_STENCILCNTL__STENCILZPASS_BF(n) (((n) & 0x7) << 21)
|
||||
#define ZB_STENCILCNTL__STENCILZFAIL_BF(n) (((n) & 0x7) << 24)
|
||||
#define ZB_STENCILCNTL__ZERO_OUTPUT_MASK(n) (((n) & 0x1) << 27)
|
||||
#define ZB_STENCILREFMASK__STENCILREF(n) (((n) & 0xff) << 0)
|
||||
#define ZB_STENCILREFMASK__STENCILMASK(n) (((n) & 0xff) << 8)
|
||||
#define ZB_STENCILREFMASK__STENCILWRITEMASK(n) (((n) & 0xff) << 16)
|
||||
#define ZB_STENCILREFMASK_BF__STENCILREF(n) (((n) & 0xff) << 0)
|
||||
#define ZB_STENCILREFMASK_BF__STENCILMASK(n) (((n) & 0xff) << 8)
|
||||
#define ZB_STENCILREFMASK_BF__STENCILWRITEMASK(n) (((n) & 0xff) << 16)
|
||||
#define ZB_ZCACHE_CTLSTAT__ZC_FLUSH(n) (((n) & 0x1) << 0)
|
||||
#define ZB_ZCACHE_CTLSTAT__ZC_FREE(n) (((n) & 0x1) << 1)
|
||||
#define ZB_ZCACHE_CTLSTAT__ZC_BUSY(n) (((n) & 0x1) << 31)
|
||||
#define ZB_ZPASS_ADDR__ZPASS_ADDR(n) (((n) & 0x3fffffff) << 2)
|
||||
#define ZB_ZPASS_DATA__ZPASS_DATA(n) (((n) & 0xffffffff) << 0)
|
||||
#define ZB_ZTOP__ZTOP(n) (((n) & 0x1) << 0)
|
||||
24
drm/Makefile
Normal file
24
drm/Makefile
Normal file
@ -0,0 +1,24 @@
|
||||
OPT = -O0
|
||||
|
||||
CFLAGS += -g
|
||||
CFLAGS += -Wall -Werror -Wfatal-errors
|
||||
CFLAGS += $(shell pkg-config --cflags libdrm)
|
||||
|
||||
LDFLAGS += $(shell pkg-config --libs libdrm)
|
||||
|
||||
%: %.c
|
||||
$(CC) $(ARCH) $(CFLAGS) $(LDFLAGS) $(OPT) $< -o $@
|
||||
|
||||
clean:
|
||||
find . -type f ! -name "*.*" -delete
|
||||
|
||||
.SUFFIXES:
|
||||
.INTERMEDIATE:
|
||||
.SECONDARY:
|
||||
.PHONY: all clean phony
|
||||
|
||||
%: RCS/%,v
|
||||
%: RCS/%
|
||||
%: %,v
|
||||
%: s.%
|
||||
%: SCCS/s.%
|
||||
37
drm/command_processor.h
Normal file
37
drm/command_processor.h
Normal file
@ -0,0 +1,37 @@
|
||||
#pragma once
|
||||
|
||||
#define TYPE_0_COUNT(c) (((c) & 0x3fff) << 16)
|
||||
#define TYPE_0_ONE_REG (1 << 15)
|
||||
#define TYPE_0_BASE_INDEX(i) (((i) & 0x1fff) << 0)
|
||||
|
||||
#define TYPE_3_COUNT(c) (((c) & 0x3fff) << 16)
|
||||
#define TYPE_3_OPCODE(o) (((o) & 0xff) << 8)
|
||||
|
||||
#define T0(address, count) \
|
||||
do { \
|
||||
ib[ix++].u32 = TYPE_0_COUNT(count) | TYPE_0_BASE_INDEX(address >> 2); \
|
||||
} while (0);
|
||||
|
||||
#define T0_ONE_REG(address, count) \
|
||||
do { \
|
||||
ib[ix++].u32 = TYPE_0_COUNT(count) | TYPE_0_ONE_REG | TYPE_0_BASE_INDEX(address >> 2); \
|
||||
} while (0);
|
||||
|
||||
#define T0V(address, value) \
|
||||
do { \
|
||||
ib[ix++].u32 = TYPE_0_COUNT(0) | TYPE_0_BASE_INDEX(address >> 2); \
|
||||
ib[ix++].u32 = value; \
|
||||
} while (0);
|
||||
|
||||
#define T0Vf(address, value) \
|
||||
do { \
|
||||
ib[ix++].u32 = TYPE_0_COUNT(0) | TYPE_0_BASE_INDEX(address >> 2); \
|
||||
ib[ix++].f32 = value; \
|
||||
} while (0);
|
||||
|
||||
#define T3(opcode, count) \
|
||||
do { \
|
||||
ib[ix++].u32 = (0b11 << 30) | TYPE_3_COUNT(count) | TYPE_3_OPCODE(opcode); \
|
||||
} while (0);
|
||||
|
||||
#define _3D_DRAW_IMMD_2 0x35
|
||||
380
drm/main.c
380
drm/main.c
@ -1,380 +0,0 @@
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <sys/mman.h>
|
||||
|
||||
#include <xf86drm.h>
|
||||
#include <libdrm/radeon_drm.h>
|
||||
|
||||
#include "3d_registers.h"
|
||||
#include "3d_registers_undocumented.h"
|
||||
|
||||
static uint32_t ib[16384];
|
||||
|
||||
#define TYPE_0_COUNT(c) (((c) & 0x3fff) << 16)
|
||||
#define TYPE_0_ONE_REG (1 << 15)
|
||||
#define TYPE_0_BASE_INDEX(i) (((i) & 0x1fff) << 0)
|
||||
|
||||
#define TYPE_3_COUNT(c) (((c) & 0x3fff) << 16)
|
||||
#define TYPE_3_OPCODE(o) (((o) & 0xff) << 8)
|
||||
|
||||
#define T0(address, count) \
|
||||
do { \
|
||||
ib[ix++] = TYPE_0_COUNT(count) | TYPE_0_BASE_INDEX(address >> 2); \
|
||||
} while (0);
|
||||
|
||||
#define T0_ONE_REG(address, count) \
|
||||
do { \
|
||||
ib[ix++] = TYPE_0_COUNT(count) | TYPE_0_ONE_REG | TYPE_0_BASE_INDEX(address >> 2); \
|
||||
} while (0);
|
||||
|
||||
#define T0V(address, value) \
|
||||
do { \
|
||||
ib[ix++] = TYPE_0_COUNT(0) | TYPE_0_BASE_INDEX(address >> 2); \
|
||||
ib[ix++] = value; \
|
||||
} while (0);
|
||||
|
||||
#define T3(opcode, count) \
|
||||
do { \
|
||||
ib[ix++] = (0b11 << 30) | TYPE_3_COUNT(count) | TYPE_3_OPCODE(opcode); \
|
||||
} while (0);
|
||||
|
||||
int indirect_buffer()
|
||||
{
|
||||
int ix = 0;
|
||||
|
||||
T0V(SC_SCISSOR0, 0x0);
|
||||
T0V(SC_SCISSOR1, ((1200 - 1) << 13) | ((1600 - 1) << 0));
|
||||
|
||||
T0V(RB3D_DSTCACHE_CTLSTAT, 0x0000000a);
|
||||
|
||||
T0V(ZB_ZCACHE_CTLSTAT, 0x00000003);
|
||||
|
||||
T0V(WAIT_UNTIL, 0x00020000);
|
||||
|
||||
T0V(GB_AA_CONFIG, 0x00000000);
|
||||
|
||||
T0V(RB3D_AARESOLVE_CTL, 0x00000000);
|
||||
|
||||
T0V(RB3D_CCTL, 0x00004000);
|
||||
|
||||
T0V(RB3D_COLOROFFSET0, 0x00000000);
|
||||
ib[ix++] = 0xc0001000;
|
||||
ib[ix++] = 0x0;
|
||||
|
||||
T0V(RB3D_COLORPITCH0, (6 << 21) | (1600 << 0));
|
||||
ib[ix++] = 0xc0001000;
|
||||
ib[ix++] = 0x0;
|
||||
|
||||
T0V(ZB_BW_CNTL, 0x00000000);
|
||||
T0V(ZB_DEPTHCLEARVALUE, 0x00000000);
|
||||
T0V(SC_HYPERZ_EN, 0x00000000);
|
||||
T0V(GB_Z_PEQ_CONFIG, 0x00000000);
|
||||
T0V(ZB_ZTOP, 0x00000001);
|
||||
T0V(FG_ALPHA_FUNC, 0x00000000);
|
||||
T0V(ZB_CNTL, 0x00000000);
|
||||
T0V(ZB_ZSTENCILCNTL, 0x00000000);
|
||||
T0V(ZB_STENCILREFMASK, 0x00000000);
|
||||
T0V(ZB_STENCILREFMASK_BF, 0x00000000);
|
||||
|
||||
T0V(FG_ALPHA_VALUE, 0x00000000);
|
||||
T0V(RB3D_ROPCNTL, 0x00000000);
|
||||
T0V(RB3D_BLENDCNTL, 0x00000000);
|
||||
T0V(RB3D_ABLENDCNTL, 0x00000000);
|
||||
T0V(RB3D_COLOR_CHANNEL_MASK, 0x0000000f);
|
||||
T0V(RB3D_DITHER_CTL, 0x00000000);
|
||||
T0V(RB3D_CONSTANT_COLOR_AR, 0x00000000);
|
||||
T0V(RB3D_CONSTANT_COLOR_GB, 0x00000000);
|
||||
|
||||
T0V(SC_CLIP_0_A, 0x00000000);
|
||||
T0V(SC_CLIP_0_B, 0xffffffff);
|
||||
|
||||
T0V(SC_SCREENDOOR, 0x00ffffff);
|
||||
T0V(GB_SELECT, 0x00000000);
|
||||
T0V(FG_FOG_BLEND, 0x00000000);
|
||||
T0V(GA_OFFSET, 0x00000000);
|
||||
T0V(SU_TEX_WRAP, 0x00000000);
|
||||
T0V(SU_DEPTH_SCALE, 0x4b7fffff);
|
||||
T0V(SU_DEPTH_OFFSET, 0x00000000);
|
||||
T0V(SC_EDGERULE, 0x2da49525);
|
||||
T0V(RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101);
|
||||
T0V(RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xfefefefe);
|
||||
T0V(GA_COLOR_CONTROL_PS3, 0x00000000);
|
||||
T0V(SU_TEX_WRAP_PS3, 0x00000000);
|
||||
T0V(VAP_VPORT_XSCALE, 0x44480000);
|
||||
T0V(VAP_VPORT_XOFFSET, 0x44480000);
|
||||
T0V(VAP_VPORT_YSCALE, 0xc4160000);
|
||||
T0V(VAP_VPORT_YOFFSET, 0x44160000);
|
||||
T0V(VAP_VPORT_ZSCALE, 0x3f000000);
|
||||
T0V(VAP_VPORT_ZOFFSET, 0x3f000000);
|
||||
T0V(VAP_VTE_CNTL, 0x0000043f);
|
||||
T0V(VAP_PVS_STATE_FLUSH_REG, 0x00000000);
|
||||
T0V(VAP_PVS_VTX_TIMEOUT_REG, 0x0000ffff);
|
||||
T0V(VAP_GB_VERT_CLIP_ADJ, 0x3f800000);
|
||||
T0V(VAP_GB_VERT_DISC_ADJ, 0x3f800000);
|
||||
T0V(VAP_GB_HORZ_CLIP_ADJ, 0x3f800000);
|
||||
T0V(VAP_GB_HORZ_DISC_ADJ, 0x3f800000);
|
||||
T0V(VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa);
|
||||
T0V(VAP_TEX_TO_COLOR_CNTL, 0x00000000);
|
||||
T0V(VAP_PROG_STREAM_CNTL_0, 0x00002002);
|
||||
T0V(VAP_PROG_STREAM_CNTL_EXT_0, 0x0000fa88);
|
||||
T0V(VAP_PVS_CODE_CNTL_0, 0x00000000);
|
||||
T0V(VAP_PVS_CODE_CNTL_1, 0x00000000);
|
||||
T0V(VAP_PVS_VECTOR_INDX_REG, 0x00000000);
|
||||
|
||||
T0_ONE_REG(VAP_PVS_VECTOR_DATA_REG_128, 3);
|
||||
ib[ix++] = 0x00f00203;
|
||||
ib[ix++] = 0x00d10001;
|
||||
ib[ix++] = 0x01248001;
|
||||
ib[ix++] = 0x01248001;
|
||||
|
||||
T0V(VAP_CNTL, 0x00b0055a);
|
||||
T0V(VAP_PVS_FLOW_CNTL_OPC, 0x00000000);
|
||||
|
||||
T0(VAP_PVS_FLOW_CNTL_ADDRS_LW_0, 31);
|
||||
for (int i = 0; i < 32; i++)
|
||||
ib[ix++] = 0x00000000;
|
||||
|
||||
T0(VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, 15);
|
||||
for (int i = 0; i < 16; i++)
|
||||
ib[ix++] = 0x00000000;
|
||||
|
||||
T0V(VAP_PVS_VECTOR_INDX_REG, 0x00000600);
|
||||
T0_ONE_REG(VAP_PVS_VECTOR_DATA_REG_128, 23);
|
||||
for (int i = 0; i < 24; i++)
|
||||
ib[ix++] = 0x00000000;
|
||||
|
||||
T0V(VAP_VTX_STATE_CNTL, 0x00005555);
|
||||
T0V(VAP_VSM_VTX_ASSM, 0x00000001);
|
||||
T0V(VAP_OUT_VTX_FMT_0, 0x00000001);
|
||||
T0V(VAP_OUT_VTX_FMT_1, 0x00000000);
|
||||
T0V(GB_ENABLE, 0x00000000);
|
||||
T0V(RS_IP_0, 0x30000000);
|
||||
T0V(RS_COUNT, 0x00040080);
|
||||
T0V(RS_INST_COUNT, 0x00000000);
|
||||
T0V(RS_INST_0, 0x00000000);
|
||||
T0V(VAP_CNTL_STATUS, 0x00000000);
|
||||
T0V(VAP_CLIP_CNTL, 0x0000c000);
|
||||
T0V(GA_POINT_SIZE, 0x00060006);
|
||||
T0V(GA_POINT_MINMAX, 0x00060006);
|
||||
T0V(GA_LINE_CNTL, 0x00020006);
|
||||
T0V(SU_POLY_OFFSET_ENABLE, 0x00000000);
|
||||
T0V(SU_CULL_MODE, 0x00000000);
|
||||
T0V(GA_LINE_STIPPLE_CONFIG, 0x00000000);
|
||||
T0V(GA_LINE_STIPPLE_VALUE, 0x00000000);
|
||||
T0V(GA_POLY_MODE, 0x00000000);
|
||||
T0V(GA_ROUND_MODE, 0x00000031);
|
||||
T0V(SC_CLIP_RULE, 0x0000ffff);
|
||||
T0V(GA_POINT_S0, 0x00000000);
|
||||
T0V(GA_POINT_T0, 0x3f800000);
|
||||
T0V(GA_POINT_S1, 0x3f800000);
|
||||
T0V(GA_POINT_T1, 0x00000000);
|
||||
T0V(US_OUT_FMT_0, 0x00001b00);
|
||||
T0V(US_OUT_FMT_1, 0x0000000f);
|
||||
T0V(US_OUT_FMT_2, 0x0000000f);
|
||||
T0V(US_OUT_FMT_3, 0x0000000f);
|
||||
T0V(GB_MSPOS0, 0x66666666);
|
||||
T0V(GB_MSPOS1, 0x06666666);
|
||||
T0V(US_CONFIG, 0x00000002);
|
||||
T0V(US_PIXSIZE, 0x00000001);
|
||||
T0V(US_FC_CTRL, 0x00000000);
|
||||
T0V(US_CODE_RANGE, 0x00000000);
|
||||
T0V(US_CODE_OFFSET, 0x00000000);
|
||||
T0V(US_CODE_ADDR, 0x00000000);
|
||||
|
||||
T0V(GA_US_VECTOR_INDEX, 0x00000000);
|
||||
|
||||
T0_ONE_REG(GA_US_VECTOR_DATA, 5);
|
||||
ib[ix++] = 0x00078005;
|
||||
ib[ix++] = 0x08020080;
|
||||
ib[ix++] = 0x08020080;
|
||||
ib[ix++] = 0x1c9b04d8;
|
||||
ib[ix++] = 0x1c810003;
|
||||
ib[ix++] = 0x00000005;
|
||||
|
||||
T0V(FG_DEPTH_SRC, 0x00000000);
|
||||
T0V(US_W_FMT, 0x00000000);
|
||||
T0V(VAP_PVS_CONST_CNTL, 0x00000000);
|
||||
T0V(TX_INVALTAGS, 0x00000000);
|
||||
T0V(TX_ENABLE, 0x00000000);
|
||||
T0V(VAP_INDEX_OFFSET, 0x00000000);
|
||||
T0V(GA_COLOR_CONTROL, 0x0003aaaa);
|
||||
T0V(VAP_VF_MAX_VTX_INDX, 0x00000002);
|
||||
T0V(VAP_VF_MIN_VTX_INDX, 0x00000000);
|
||||
T0V(VAP_VTX_SIZE, 0x00000003);
|
||||
|
||||
T3(0x35, 9);
|
||||
ib[ix++] = 0x00030034;
|
||||
ib[ix++] = 0x3f000000;
|
||||
ib[ix++] = 0xbf800000; //0xbf000000;
|
||||
ib[ix++] = 0x00000000;
|
||||
ib[ix++] = 0xbf800000; //0xbf000000
|
||||
ib[ix++] = 0xbf800000; //0xbf000000
|
||||
ib[ix++] = 0x00000000;
|
||||
ib[ix++] = 0x00000000;
|
||||
ib[ix++] = 0x3f000000;
|
||||
ib[ix++] = 0x00000000;
|
||||
|
||||
while ((ix % 8) != 0) {
|
||||
ib[ix++] = 0x80000000;
|
||||
}
|
||||
|
||||
return ix;
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
int ret;
|
||||
int fd = open("/dev/dri/card0", O_RDWR | O_CLOEXEC);
|
||||
|
||||
int colorbuffer_handle;
|
||||
int flush_handle;
|
||||
|
||||
// colorbuffer
|
||||
{
|
||||
struct drm_radeon_gem_create args = {
|
||||
.size = 1600 * 1200 * 4,
|
||||
.alignment = 4096,
|
||||
.handle = 0,
|
||||
.initial_domain = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.flags = 4
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE, &args, (sizeof (struct drm_radeon_gem_create)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_CREATE)");
|
||||
}
|
||||
assert(args.handle != 0);
|
||||
|
||||
colorbuffer_handle = args.handle;
|
||||
}
|
||||
|
||||
// flush
|
||||
{
|
||||
struct drm_radeon_gem_create args = {
|
||||
.size = 4096,
|
||||
.alignment = 4096,
|
||||
.handle = 0,
|
||||
.initial_domain = 2, // GTT
|
||||
.flags = 0
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE,
|
||||
&args, (sizeof (args)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_CREATE)");
|
||||
}
|
||||
assert(args.handle != 0);
|
||||
flush_handle = args.handle;
|
||||
}
|
||||
|
||||
|
||||
fprintf(stderr, "colorbuffer handle %d\n", colorbuffer_handle);
|
||||
|
||||
struct drm_radeon_cs_reloc relocs[] = {
|
||||
{
|
||||
.handle = colorbuffer_handle,
|
||||
.read_domains = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.write_domain = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.flags = 8,
|
||||
},
|
||||
{
|
||||
.handle = flush_handle,
|
||||
.read_domains = 2, // RADEON_GEM_DOMAIN_GTT
|
||||
.write_domain = 2, // RADEON_GEM_DOMAIN_GTT
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
uint32_t flags[2] = {
|
||||
5, // RADEON_CS_KEEP_TILING_FLAGS | RADEON_CS_END_OF_FRAME
|
||||
0, // RADEON_CS_RING_GFX
|
||||
};
|
||||
|
||||
int ib_dwords = indirect_buffer();
|
||||
//int ib_dwords = (sizeof (ib2)) / (sizeof (ib2[0]));
|
||||
|
||||
struct drm_radeon_cs_chunk chunks[3] = {
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_IB,
|
||||
.length_dw = ib_dwords,
|
||||
.chunk_data = (uint64_t)(uintptr_t)ib,
|
||||
},
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_RELOCS,
|
||||
.length_dw = (sizeof (relocs)) / (sizeof (uint32_t)),
|
||||
.chunk_data = (uint64_t)(uintptr_t)relocs,
|
||||
},
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_FLAGS,
|
||||
.length_dw = (sizeof (flags)) / (sizeof (uint32_t)),
|
||||
.chunk_data = (uint64_t)(uintptr_t)&flags,
|
||||
},
|
||||
};
|
||||
|
||||
uint64_t chunks_array[3] = {
|
||||
(uint64_t)(uintptr_t)&chunks[0],
|
||||
(uint64_t)(uintptr_t)&chunks[1],
|
||||
(uint64_t)(uintptr_t)&chunks[2],
|
||||
};
|
||||
|
||||
struct drm_radeon_cs cs = {
|
||||
.num_chunks = 3,
|
||||
.cs_id = 0,
|
||||
.chunks = (uint64_t)(uintptr_t)chunks_array,
|
||||
.gart_limit = 0,
|
||||
.vram_limit = 0,
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_CS, &cs, (sizeof (struct drm_radeon_cs)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_CS)");
|
||||
}
|
||||
|
||||
struct drm_radeon_gem_wait_idle args = {
|
||||
.handle = flush_handle
|
||||
};
|
||||
while (drmCommandWrite(fd, DRM_RADEON_GEM_WAIT_IDLE, &args, (sizeof (struct drm_radeon_gem_wait_idle))) == -EBUSY);
|
||||
|
||||
struct drm_radeon_gem_mmap mmap_args = {
|
||||
.handle = colorbuffer_handle,
|
||||
.offset = 0,
|
||||
.size = 1600 * 1200 * 4,
|
||||
};
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_MMAP, &mmap_args, (sizeof (struct drm_radeon_gem_mmap)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_MMAP)");
|
||||
}
|
||||
|
||||
void * ptr;
|
||||
ptr = mmap(0, mmap_args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
|
||||
fd, mmap_args.addr_ptr);
|
||||
|
||||
int out_fd = open("colorbuffer.data", O_RDWR|O_CREAT);
|
||||
assert(out_fd >= 0);
|
||||
ssize_t write_length = write(out_fd, ptr, mmap_args.size);
|
||||
assert(write_length == mmap_args.size);
|
||||
close(out_fd);
|
||||
|
||||
int mm_fd = open("/sys/kernel/debug/radeon_vram_mm", O_RDONLY);
|
||||
assert(mm_fd >= 0);
|
||||
char buf[4096];
|
||||
while (true) {
|
||||
ssize_t read_length = read(mm_fd, buf, 4096);
|
||||
assert(read_length >= 0);
|
||||
write(STDOUT_FILENO, buf, read_length);
|
||||
if (read_length < 4096) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
close(mm_fd);
|
||||
|
||||
munmap(ptr, mmap_args.size);
|
||||
|
||||
close(fd);
|
||||
}
|
||||
631
drm/single_color.c
Normal file
631
drm/single_color.c
Normal file
@ -0,0 +1,631 @@
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <sys/mman.h>
|
||||
|
||||
#include <xf86drm.h>
|
||||
#include <libdrm/radeon_drm.h>
|
||||
|
||||
#include "3d_registers.h"
|
||||
#include "3d_registers_undocumented.h"
|
||||
#include "3d_registers_bits.h"
|
||||
#include "command_processor.h"
|
||||
|
||||
union u32_f32 {
|
||||
uint32_t u32;
|
||||
float f32;
|
||||
};
|
||||
|
||||
static union u32_f32 ib[16384];
|
||||
|
||||
int indirect_buffer()
|
||||
{
|
||||
int ix = 0;
|
||||
|
||||
T0V(RB3D_DSTCACHE_CTLSTAT
|
||||
, RB3D_DSTCACHE_CTLSTAT__DC_FLUSH(0x2) // Flush dirty 3D data
|
||||
| RB3D_DSTCACHE_CTLSTAT__DC_FREE(0x2) // Free 3D tags
|
||||
);
|
||||
|
||||
T0V(ZB_ZCACHE_CTLSTAT
|
||||
, ZB_ZCACHE_CTLSTAT__ZC_FLUSH(1)
|
||||
| ZB_ZCACHE_CTLSTAT__ZC_FREE(1)
|
||||
);
|
||||
|
||||
T0V(WAIT_UNTIL, 0x00020000);
|
||||
|
||||
T0V(GB_AA_CONFIG, 0x00000000);
|
||||
|
||||
T0V(RB3D_AARESOLVE_CTL, 0x00000000);
|
||||
|
||||
T0V(RB3D_CCTL
|
||||
, RB3D_CCTL__INDEPENDENT_COLORFORMAT_ENABLE(1)
|
||||
);
|
||||
|
||||
T0V(RB3D_COLOROFFSET0, 0x00000000); // value replaced by kernel from relocs
|
||||
ib[ix++].u32 = 0xc0001000;
|
||||
ib[ix++].u32 = 0x0;
|
||||
|
||||
T0V(RB3D_COLORPITCH0
|
||||
, RB3D_COLORPITCH__COLORPITCH(1600 >> 1)
|
||||
| RB3D_COLORPITCH__COLORFORMAT(6) // ARGB8888
|
||||
);
|
||||
ib[ix++].u32 = 0xc0001000;
|
||||
ib[ix++].u32 = 0x0;
|
||||
|
||||
T0V(ZB_BW_CNTL, 0x00000000);
|
||||
T0V(ZB_DEPTHCLEARVALUE, 0x00000000);
|
||||
T0V(SC_HYPERZ_EN, 0x00000000);
|
||||
T0V(GB_Z_PEQ_CONFIG, 0x00000000);
|
||||
T0V(ZB_ZTOP
|
||||
, ZB_ZTOP__ZTOP(1)
|
||||
);
|
||||
T0V(FG_ALPHA_FUNC, 0x00000000);
|
||||
T0V(ZB_CNTL, 0x00000000);
|
||||
T0V(ZB_ZSTENCILCNTL, 0x00000000);
|
||||
T0V(ZB_STENCILREFMASK, 0x00000000);
|
||||
T0V(ZB_STENCILREFMASK_BF, 0x00000000);
|
||||
|
||||
T0V(FG_ALPHA_VALUE, 0x00000000);
|
||||
T0V(RB3D_ROPCNTL, 0x00000000);
|
||||
T0V(RB3D_BLENDCNTL, 0x00000000);
|
||||
T0V(RB3D_ABLENDCNTL, 0x00000000);
|
||||
T0V(RB3D_COLOR_CHANNEL_MASK
|
||||
, RB3D_COLOR_CHANNEL_MASK__BLUE_MASK(1)
|
||||
| RB3D_COLOR_CHANNEL_MASK__GREEN_MASK(1)
|
||||
| RB3D_COLOR_CHANNEL_MASK__RED_MASK(1)
|
||||
| RB3D_COLOR_CHANNEL_MASK__ALPHA_MASK(1)
|
||||
);
|
||||
T0V(RB3D_DITHER_CTL, 0x00000000);
|
||||
T0V(RB3D_CONSTANT_COLOR_AR, 0x00000000);
|
||||
T0V(RB3D_CONSTANT_COLOR_GB, 0x00000000);
|
||||
|
||||
T0V(SC_CLIP_0_A, 0x00000000);
|
||||
T0V(SC_CLIP_0_B, 0xffffffff);
|
||||
T0V(SC_SCREENDOOR, 0x00ffffff);
|
||||
|
||||
T0V(GB_SELECT, 0x00000000);
|
||||
T0V(FG_FOG_BLEND, 0x00000000);
|
||||
T0V(GA_OFFSET, 0x00000000);
|
||||
T0V(SU_TEX_WRAP, 0x00000000);
|
||||
T0Vf(SU_DEPTH_SCALE, 16777215.0f);
|
||||
T0V(SU_DEPTH_OFFSET, 0x00000000);
|
||||
T0V(SC_EDGERULE
|
||||
, SC_EDGERULE__ER_TRI(5) // L-in,R-out,HT-in,HB-in
|
||||
| SC_EDGERULE__ER_POINT(9) // L-out,R-in,HT-in,HB-out
|
||||
| SC_EDGERULE__ER_LINE_LR(5) // L-in,R-out,HT-in,HB-out
|
||||
| SC_EDGERULE__ER_LINE_RL(9) // L-out,R-in,HT-in,HB-out
|
||||
| SC_EDGERULE__ER_LINE_TB(26) // T-in,B-out,VL-out,VR-in
|
||||
| SC_EDGERULE__ER_LINE_BT(22) // T-out,B-in,VL-out,VR-in
|
||||
);
|
||||
T0V(RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
|
||||
, RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__BLUE(1)
|
||||
| RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__GREEN(1)
|
||||
| RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__RED(1)
|
||||
| RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__ALPHA(1)
|
||||
);
|
||||
T0V(RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
|
||||
, RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__BLUE(254)
|
||||
| RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__GREEN(254)
|
||||
| RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__RED(254)
|
||||
| RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__ALPHA(254)
|
||||
);
|
||||
T0V(GA_COLOR_CONTROL_PS3, 0x00000000);
|
||||
T0V(SU_TEX_WRAP_PS3, 0x00000000);
|
||||
T0V(VAP_PVS_STATE_FLUSH_REG, 0x00000000);
|
||||
T0V(VAP_PVS_VTX_TIMEOUT_REG
|
||||
, VAP_PVS_VTX_TIMEOUT_REG__CLK_COUNT(0xffff)
|
||||
);
|
||||
T0Vf(VAP_GB_VERT_CLIP_ADJ, 1.0f);
|
||||
T0Vf(VAP_GB_VERT_DISC_ADJ, 1.0f);
|
||||
T0Vf(VAP_GB_HORZ_CLIP_ADJ, 1.0f);
|
||||
T0Vf(VAP_GB_HORZ_DISC_ADJ, 1.0f);
|
||||
T0V(VAP_PSC_SGN_NORM_CNTL
|
||||
, VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_0(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_1(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_2(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_3(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_4(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_5(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_6(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_7(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_8(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_9(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_10(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_11(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_12(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_13(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_14(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_15(2)
|
||||
);
|
||||
T0V(VAP_TEX_TO_COLOR_CNTL, 0x00000000);
|
||||
|
||||
T0V(VAP_CNTL
|
||||
, VAP_CNTL__PVS_NUM_SLOTS(10)
|
||||
| VAP_CNTL__PVS_NUM_CNTLRS(5)
|
||||
| VAP_CNTL__PVS_NUM_FPUS(5)
|
||||
| VAP_CNTL__VAP_NO_RENDER(0)
|
||||
| VAP_CNTL__VF_MAX_VTX_NUM(12)
|
||||
| VAP_CNTL__DX_CLIP_SPACE_DEF(0)
|
||||
| VAP_CNTL__TCL_STATE_OPTIMIZATION(1)
|
||||
);
|
||||
T0V(VAP_PVS_FLOW_CNTL_OPC, 0x00000000);
|
||||
|
||||
T0(VAP_PVS_FLOW_CNTL_ADDRS_LW_0, 31);
|
||||
for (int i = 0; i < 32; i++)
|
||||
ib[ix++].u32 = 0x00000000;
|
||||
|
||||
T0(VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, 15);
|
||||
for (int i = 0; i < 16; i++)
|
||||
ib[ix++].u32 = 0x00000000;
|
||||
|
||||
T0V(VAP_PVS_VECTOR_INDX_REG, 0x00000600);
|
||||
T0_ONE_REG(VAP_PVS_VECTOR_DATA_REG_128, 23);
|
||||
for (int i = 0; i < 24; i++)
|
||||
ib[ix++].u32 = 0x00000000;
|
||||
|
||||
T0V(VAP_VTX_STATE_CNTL
|
||||
, VAP_VTX_STATE_CNTL__COLOR_0_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_1_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_2_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_3_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_4_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_5_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_6_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_7_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__UPDATE_USER_COLOR_0_ENA(0)
|
||||
);
|
||||
|
||||
T0V(GB_ENABLE, 0x00000000);
|
||||
T0V(VAP_CNTL_STATUS, 0x00000000);
|
||||
T0V(VAP_CLIP_CNTL
|
||||
, VAP_CLIP_CNTL__PS_UCP_MODE(3)
|
||||
);
|
||||
T0V(GA_POINT_SIZE
|
||||
, GA_POINT_SIZE__HEIGHT(6)
|
||||
| GA_POINT_SIZE__WIDTH(6)
|
||||
);
|
||||
T0V(GA_POINT_MINMAX
|
||||
, GA_POINT_MINMAX__MIN_SIZE(6)
|
||||
| GA_POINT_MINMAX__MAX_SIZE(6)
|
||||
);
|
||||
T0V(GA_LINE_CNTL
|
||||
, GA_LINE_CNTL__WIDTH(6)
|
||||
| GA_LINE_CNTL__END_TYPE(2)
|
||||
| GA_LINE_CNTL__SORT(0)
|
||||
);
|
||||
T0V(SU_POLY_OFFSET_ENABLE, 0x00000000);
|
||||
T0V(SU_CULL_MODE, 0x00000000);
|
||||
T0V(GA_LINE_STIPPLE_CONFIG, 0x00000000);
|
||||
T0V(GA_LINE_STIPPLE_VALUE, 0x00000000);
|
||||
T0V(GA_POLY_MODE, 0x00000000);
|
||||
T0V(GA_ROUND_MODE
|
||||
, GA_ROUND_MODE__GEOMETRY_ROUND(1)
|
||||
| GA_ROUND_MODE__COLOR_ROUND(0)
|
||||
| GA_ROUND_MODE__RGB_CLAMP(1)
|
||||
| GA_ROUND_MODE__ALPHA_CLAMP(1)
|
||||
| GA_ROUND_MODE__GEOMETRY_MASK(0)
|
||||
);
|
||||
T0V(SC_CLIP_RULE
|
||||
, SC_CLIP_RULE__CLIP_RULE(0xffff));
|
||||
T0Vf(GA_POINT_S0, 0.0f);
|
||||
T0Vf(GA_POINT_T0, 1.0f);
|
||||
T0Vf(GA_POINT_S1, 1.0f);
|
||||
T0Vf(GA_POINT_T1, 0.0f);
|
||||
T0V(US_OUT_FMT_0
|
||||
, US_OUT_FMT__OUT_FMT(0) // C4_8
|
||||
| US_OUT_FMT__C0_SEL(3) // Blue
|
||||
| US_OUT_FMT__C1_SEL(2) // Green
|
||||
| US_OUT_FMT__C2_SEL(1) // Red
|
||||
| US_OUT_FMT__C3_SEL(0) // Alpha
|
||||
| US_OUT_FMT__OUT_SIGN(0)
|
||||
);
|
||||
T0V(US_OUT_FMT_1
|
||||
, US_OUT_FMT__OUT_FMT(15) // render target is not used
|
||||
);
|
||||
T0V(US_OUT_FMT_2
|
||||
, US_OUT_FMT__OUT_FMT(15) // render target is not used
|
||||
);
|
||||
T0V(US_OUT_FMT_2
|
||||
, US_OUT_FMT__OUT_FMT(15) // render target is not used
|
||||
);
|
||||
T0V(GB_MSPOS0
|
||||
, GB_MSPOS0__MS_X0(6)
|
||||
| GB_MSPOS0__MS_Y0(6)
|
||||
| GB_MSPOS0__MS_X1(6)
|
||||
| GB_MSPOS0__MS_Y1(6)
|
||||
| GB_MSPOS0__MS_X2(6)
|
||||
| GB_MSPOS0__MS_Y2(6)
|
||||
| GB_MSPOS0__MSBD0_Y(6)
|
||||
| GB_MSPOS0__MSBD0_X(6)
|
||||
);
|
||||
T0V(GB_MSPOS1
|
||||
, GB_MSPOS1__MS_X3(6)
|
||||
| GB_MSPOS1__MS_Y3(6)
|
||||
| GB_MSPOS1__MS_X4(6)
|
||||
| GB_MSPOS1__MS_Y4(6)
|
||||
| GB_MSPOS1__MS_X5(6)
|
||||
| GB_MSPOS1__MS_Y5(6)
|
||||
| GB_MSPOS1__MSBD1(6)
|
||||
);
|
||||
T0V(US_CONFIG
|
||||
, US_CONFIG__ZERO_TIMES_ANYTHING_EQUALS_ZERO(1)
|
||||
);
|
||||
T0V(US_PIXSIZE
|
||||
, US_PIXSIZE__PIX_SIZE(1)
|
||||
);
|
||||
T0V(US_FC_CTRL, 0);
|
||||
|
||||
T0V(FG_DEPTH_SRC, 0x00000000);
|
||||
T0V(US_W_FMT, 0x00000000);
|
||||
T0V(VAP_PVS_CONST_CNTL, 0x00000000);
|
||||
T0V(TX_INVALTAGS, 0x00000000);
|
||||
T0V(TX_ENABLE, 0x00000000);
|
||||
T0V(VAP_INDEX_OFFSET, 0x00000000);
|
||||
T0V(GA_COLOR_CONTROL
|
||||
, GA_COLOR_CONTROL__RGB0_SHADING(2)
|
||||
| GA_COLOR_CONTROL__ALPHA0_SHADING(2)
|
||||
| GA_COLOR_CONTROL__RGB1_SHADING(2)
|
||||
| GA_COLOR_CONTROL__ALPHA1_SHADING(2)
|
||||
| GA_COLOR_CONTROL__RGB2_SHADING(2)
|
||||
| GA_COLOR_CONTROL__ALPHA2_SHADING(2)
|
||||
| GA_COLOR_CONTROL__RGB3_SHADING(2)
|
||||
| GA_COLOR_CONTROL__ALPHA3_SHADING(2)
|
||||
| GA_COLOR_CONTROL__PROVOKING_VERTEX(3)
|
||||
);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// SC
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0V(SC_SCISSOR0
|
||||
, SC_SCISSOR0__XS0(0)
|
||||
| SC_SCISSOR0__YS0(0)
|
||||
);
|
||||
T0V(SC_SCISSOR1
|
||||
, SC_SCISSOR1__XS1(1600 - 1)
|
||||
| SC_SCISSOR1__YS1(1200 - 1)
|
||||
);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// VAP
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0Vf(VAP_VPORT_XSCALE, 800.0f);
|
||||
T0Vf(VAP_VPORT_XOFFSET, 800.0f);
|
||||
T0Vf(VAP_VPORT_YSCALE, -600.0f);
|
||||
T0Vf(VAP_VPORT_YOFFSET, 600.0f);
|
||||
T0Vf(VAP_VPORT_ZSCALE, 0.5f);
|
||||
T0Vf(VAP_VPORT_ZOFFSET, 0.5f);
|
||||
|
||||
T0V(VAP_VTE_CNTL
|
||||
, VAP_VTE_CNTL__VPORT_X_SCALE_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_X_OFFSET_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_Y_SCALE_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_Y_OFFSET_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_Z_SCALE_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_Z_OFFSET_ENA(1)
|
||||
| VAP_VTE_CNTL__VTX_XY_FMT(0)
|
||||
| VAP_VTE_CNTL__VTX_Z_FMT(0)
|
||||
| VAP_VTE_CNTL__VTX_W0_FMT(1)
|
||||
| VAP_VTE_CNTL__SERIAL_PROC_ENA(0)
|
||||
);
|
||||
|
||||
T0V(VAP_VF_MAX_VTX_INDX
|
||||
, VAP_VF_MAX_VTX_INDX__MAX_INDX(2)
|
||||
);
|
||||
T0V(VAP_VF_MIN_VTX_INDX
|
||||
, VAP_VF_MIN_VTX_INDX__MIN_INDX(0)
|
||||
);
|
||||
T0V(VAP_VTX_SIZE
|
||||
, VAP_VTX_SIZE__DWORDS_PER_VTX(3)
|
||||
);
|
||||
|
||||
T0V(VAP_PROG_STREAM_CNTL_0
|
||||
, VAP_PROG_STREAM_CNTL__DATA_TYPE_0(2)
|
||||
| VAP_PROG_STREAM_CNTL__SKIP_DWORDS_0(0)
|
||||
| VAP_PROG_STREAM_CNTL__DST_VEC_LOC_0(0)
|
||||
| VAP_PROG_STREAM_CNTL__LAST_VEC_0(1)
|
||||
);
|
||||
T0V(VAP_PROG_STREAM_CNTL_EXT_0
|
||||
, VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_X_0(0)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Y_0(1)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Z_0(2)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_W_0(5)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__WRITE_ENA_0(15)
|
||||
);
|
||||
|
||||
T0V(VAP_VSM_VTX_ASSM
|
||||
, 0x00000001); // undocumented
|
||||
T0V(VAP_OUT_VTX_FMT_0
|
||||
, VAP_OUT_VTX_FMT_0__VTX_POS_PRESENT(1));
|
||||
T0V(VAP_OUT_VTX_FMT_1
|
||||
, 0x0);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// VAP_PVS
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0V(VAP_PVS_CODE_CNTL_0
|
||||
, VAP_PVS_CODE_CNTL_0__PVS_FIRST_INST(0)
|
||||
| VAP_PVS_CODE_CNTL_0__PVS_XYZW_VALID_INST(0)
|
||||
| VAP_PVS_CODE_CNTL_0__PVS_LAST_INST(0)
|
||||
);
|
||||
T0V(VAP_PVS_CODE_CNTL_1
|
||||
, VAP_PVS_CODE_CNTL_1__PVS_LAST_VTX_SRC_INST(0)
|
||||
);
|
||||
T0V(VAP_PVS_VECTOR_INDX_REG
|
||||
, VAP_PVS_VECTOR_INDX_REG__OCTWORD_OFFSET(0)
|
||||
);
|
||||
|
||||
const uint32_t vertex_shader[] = {
|
||||
0x00f00203,
|
||||
0x00d10001,
|
||||
0x01248001,
|
||||
0x01248001,
|
||||
};
|
||||
const int vertex_shader_length = (sizeof (vertex_shader)) / (sizeof (vertex_shader[0]));
|
||||
printf("vs length %d\n", vertex_shader_length);
|
||||
|
||||
T0_ONE_REG(VAP_PVS_VECTOR_DATA_REG_128, vertex_shader_length - 1);
|
||||
for (int i = 0; i < vertex_shader_length; i++) {
|
||||
ib[ix++].u32 = vertex_shader[i];
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// RS
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0V(RS_IP_0
|
||||
, RS_IP__TEX_PTR_S(0)
|
||||
| RS_IP__TEX_PTR_T(0)
|
||||
| RS_IP__TEX_PTR_R(0)
|
||||
| RS_IP__TEX_PTR_Q(0)
|
||||
| RS_IP__COL_PTR(0)
|
||||
| RS_IP__COL_FMT(6) // Zero components (0,0,0,1)
|
||||
| RS_IP__OFFSET_EN(0)
|
||||
);
|
||||
T0V(RS_COUNT
|
||||
, RS_COUNT__IT_COUNT(0)
|
||||
| RS_COUNT__IC_COUNT(1)
|
||||
| RS_COUNT__W_ADDR(0)
|
||||
| RS_COUNT__HIRES_EN(1)
|
||||
);
|
||||
T0V(RS_INST_COUNT, 0x00000000);
|
||||
T0V(RS_INST_0, 0x00000000);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// GA_US
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0V(US_CODE_RANGE
|
||||
, US_CODE_RANGE__CODE_ADDR(0)
|
||||
| US_CODE_RANGE__CODE_SIZE(0)
|
||||
);
|
||||
T0V(US_CODE_OFFSET
|
||||
, US_CODE_OFFSET__OFFSET_ADDR(0)
|
||||
);
|
||||
T0V(US_CODE_ADDR
|
||||
, US_CODE_ADDR__START_ADDR(0)
|
||||
| US_CODE_ADDR__END_ADDR(0)
|
||||
);
|
||||
|
||||
const uint32_t fragment_shader[] = {
|
||||
0x00078005,
|
||||
0x08020080,
|
||||
0x08020080,
|
||||
0x1c9b04d8,
|
||||
0x1c810003,
|
||||
0x00000005,
|
||||
};
|
||||
const int fragment_shader_length = (sizeof (fragment_shader)) / (sizeof (fragment_shader[0]));
|
||||
printf("fs length %d\n", fragment_shader_length);
|
||||
|
||||
T0V(GA_US_VECTOR_INDEX, 0x00000000);
|
||||
T0_ONE_REG(GA_US_VECTOR_DATA, fragment_shader_length - 1);
|
||||
for (int i = 0; i < fragment_shader_length; i++) {
|
||||
ib[ix++].u32 = fragment_shader[i];
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// 3D_DRAW
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
const float vertices[] = {
|
||||
0.5f, -0.5f, 0.0f, // bottom right
|
||||
-0.5f, -0.5f, 0.0f, // bottom left
|
||||
0.0f, 0.5f, 0.0f, // top
|
||||
};
|
||||
const int vertices_length = (sizeof (vertices)) / (sizeof (vertices[0]));
|
||||
printf("vtx length %d\n", vertices_length);
|
||||
T3(_3D_DRAW_IMMD_2, (1 + vertices_length) - 1);
|
||||
ib[ix++].u32
|
||||
= VAP_VF_CNTL__PRIM_TYPE(4)
|
||||
| VAP_VF_CNTL__PRIM_WALK(3)
|
||||
| VAP_VF_CNTL__INDEX_SIZE(0)
|
||||
| VAP_VF_CNTL__VTX_REUSE_DIS(0)
|
||||
| VAP_VF_CNTL__DUAL_INDEX_MODE(0)
|
||||
| VAP_VF_CNTL__USE_ALT_NUM_VERTS(0)
|
||||
| VAP_VF_CNTL__NUM_VERTICES(3)
|
||||
;
|
||||
for (int i = 0; i < vertices_length; i++) {
|
||||
ib[ix++].f32 = vertices[i];
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// padding
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
while ((ix % 8) != 0) {
|
||||
ib[ix++].u32 = 0x80000000;
|
||||
}
|
||||
|
||||
return ix;
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
int ret;
|
||||
int fd = open("/dev/dri/card0", O_RDWR | O_CLOEXEC);
|
||||
|
||||
const int colorbuffer_size = 1600 * 1200 * 4;
|
||||
int colorbuffer_handle;
|
||||
void * colorbuffer_ptr;
|
||||
int flush_handle;
|
||||
|
||||
// colorbuffer
|
||||
{
|
||||
struct drm_radeon_gem_create args = {
|
||||
.size = colorbuffer_size,
|
||||
.alignment = 4096,
|
||||
.handle = 0,
|
||||
.initial_domain = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.flags = 4
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE, &args, (sizeof (struct drm_radeon_gem_create)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_CREATE)");
|
||||
}
|
||||
assert(args.handle != 0);
|
||||
|
||||
colorbuffer_handle = args.handle;
|
||||
}
|
||||
|
||||
{
|
||||
struct drm_radeon_gem_mmap mmap_args = {
|
||||
.handle = colorbuffer_handle,
|
||||
.offset = 0,
|
||||
.size = colorbuffer_size,
|
||||
};
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_MMAP, &mmap_args, (sizeof (struct drm_radeon_gem_mmap)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_MMAP)");
|
||||
}
|
||||
|
||||
colorbuffer_ptr = mmap(0, mmap_args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
|
||||
fd, mmap_args.addr_ptr);
|
||||
}
|
||||
|
||||
{ // clear colorbuffer
|
||||
for (int i = 0; i < colorbuffer_size / 4; i++) {
|
||||
((uint32_t*)colorbuffer_ptr)[i] = 0;
|
||||
}
|
||||
asm volatile ("" ::: "memory");
|
||||
}
|
||||
|
||||
// flush
|
||||
{
|
||||
struct drm_radeon_gem_create args = {
|
||||
.size = 4096,
|
||||
.alignment = 4096,
|
||||
.handle = 0,
|
||||
.initial_domain = 2, // GTT
|
||||
.flags = 0
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE,
|
||||
&args, (sizeof (args)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_CREATE)");
|
||||
}
|
||||
assert(args.handle != 0);
|
||||
flush_handle = args.handle;
|
||||
}
|
||||
|
||||
|
||||
fprintf(stderr, "colorbuffer handle %d\n", colorbuffer_handle);
|
||||
|
||||
struct drm_radeon_cs_reloc relocs[] = {
|
||||
{
|
||||
.handle = colorbuffer_handle,
|
||||
.read_domains = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.write_domain = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.flags = 8,
|
||||
},
|
||||
{
|
||||
.handle = flush_handle,
|
||||
.read_domains = 2, // RADEON_GEM_DOMAIN_GTT
|
||||
.write_domain = 2, // RADEON_GEM_DOMAIN_GTT
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
uint32_t flags[2] = {
|
||||
5, // RADEON_CS_KEEP_TILING_FLAGS | RADEON_CS_END_OF_FRAME
|
||||
0, // RADEON_CS_RING_GFX
|
||||
};
|
||||
|
||||
int ib_dwords = indirect_buffer();
|
||||
//int ib_dwords = (sizeof (ib2)) / (sizeof (ib2[0]));
|
||||
|
||||
struct drm_radeon_cs_chunk chunks[3] = {
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_IB,
|
||||
.length_dw = ib_dwords,
|
||||
.chunk_data = (uint64_t)(uintptr_t)ib,
|
||||
},
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_RELOCS,
|
||||
.length_dw = (sizeof (relocs)) / (sizeof (uint32_t)),
|
||||
.chunk_data = (uint64_t)(uintptr_t)relocs,
|
||||
},
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_FLAGS,
|
||||
.length_dw = (sizeof (flags)) / (sizeof (uint32_t)),
|
||||
.chunk_data = (uint64_t)(uintptr_t)&flags,
|
||||
},
|
||||
};
|
||||
|
||||
uint64_t chunks_array[3] = {
|
||||
(uint64_t)(uintptr_t)&chunks[0],
|
||||
(uint64_t)(uintptr_t)&chunks[1],
|
||||
(uint64_t)(uintptr_t)&chunks[2],
|
||||
};
|
||||
|
||||
struct drm_radeon_cs cs = {
|
||||
.num_chunks = 3,
|
||||
.cs_id = 0,
|
||||
.chunks = (uint64_t)(uintptr_t)chunks_array,
|
||||
.gart_limit = 0,
|
||||
.vram_limit = 0,
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_CS, &cs, (sizeof (struct drm_radeon_cs)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_CS)");
|
||||
}
|
||||
|
||||
struct drm_radeon_gem_wait_idle args = {
|
||||
.handle = flush_handle
|
||||
};
|
||||
while (drmCommandWrite(fd, DRM_RADEON_GEM_WAIT_IDLE, &args, (sizeof (struct drm_radeon_gem_wait_idle))) == -EBUSY);
|
||||
|
||||
int out_fd = open("colorbuffer.data", O_RDWR|O_CREAT);
|
||||
assert(out_fd >= 0);
|
||||
ssize_t write_length = write(out_fd, colorbuffer_ptr, colorbuffer_size);
|
||||
assert(write_length == colorbuffer_size);
|
||||
close(out_fd);
|
||||
|
||||
int mm_fd = open("/sys/kernel/debug/radeon_vram_mm", O_RDONLY);
|
||||
assert(mm_fd >= 0);
|
||||
char buf[4096];
|
||||
while (true) {
|
||||
ssize_t read_length = read(mm_fd, buf, 4096);
|
||||
assert(read_length >= 0);
|
||||
write(STDOUT_FILENO, buf, read_length);
|
||||
if (read_length < 4096) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
close(mm_fd);
|
||||
|
||||
munmap(colorbuffer_ptr, colorbuffer_size);
|
||||
|
||||
close(fd);
|
||||
}
|
||||
663
drm/vertex_color.c
Normal file
663
drm/vertex_color.c
Normal file
@ -0,0 +1,663 @@
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <sys/mman.h>
|
||||
|
||||
#include <xf86drm.h>
|
||||
#include <libdrm/radeon_drm.h>
|
||||
|
||||
#include "3d_registers.h"
|
||||
#include "3d_registers_undocumented.h"
|
||||
#include "3d_registers_bits.h"
|
||||
#include "command_processor.h"
|
||||
|
||||
union u32_f32 {
|
||||
uint32_t u32;
|
||||
float f32;
|
||||
};
|
||||
|
||||
static union u32_f32 ib[16384];
|
||||
|
||||
int indirect_buffer()
|
||||
{
|
||||
int ix = 0;
|
||||
|
||||
T0V(RB3D_DSTCACHE_CTLSTAT
|
||||
, RB3D_DSTCACHE_CTLSTAT__DC_FLUSH(0x2) // Flush dirty 3D data
|
||||
| RB3D_DSTCACHE_CTLSTAT__DC_FREE(0x2) // Free 3D tags
|
||||
);
|
||||
|
||||
T0V(ZB_ZCACHE_CTLSTAT
|
||||
, ZB_ZCACHE_CTLSTAT__ZC_FLUSH(1)
|
||||
| ZB_ZCACHE_CTLSTAT__ZC_FREE(1)
|
||||
);
|
||||
|
||||
T0V(WAIT_UNTIL, 0x00020000);
|
||||
|
||||
T0V(GB_AA_CONFIG, 0x00000000);
|
||||
|
||||
T0V(RB3D_AARESOLVE_CTL, 0x00000000);
|
||||
|
||||
T0V(RB3D_CCTL
|
||||
, RB3D_CCTL__INDEPENDENT_COLORFORMAT_ENABLE(1)
|
||||
);
|
||||
|
||||
T0V(RB3D_COLOROFFSET0, 0x00000000); // value replaced by kernel from relocs
|
||||
ib[ix++].u32 = 0xc0001000;
|
||||
ib[ix++].u32 = 0x0;
|
||||
|
||||
T0V(RB3D_COLORPITCH0
|
||||
, RB3D_COLORPITCH__COLORPITCH(1600 >> 1)
|
||||
| RB3D_COLORPITCH__COLORFORMAT(6) // ARGB8888
|
||||
);
|
||||
ib[ix++].u32 = 0xc0001000;
|
||||
ib[ix++].u32 = 0x0;
|
||||
|
||||
T0V(ZB_BW_CNTL, 0x00000000);
|
||||
T0V(ZB_DEPTHCLEARVALUE, 0x00000000);
|
||||
T0V(SC_HYPERZ_EN, 0x00000000);
|
||||
T0V(GB_Z_PEQ_CONFIG, 0x00000000);
|
||||
T0V(ZB_ZTOP
|
||||
, ZB_ZTOP__ZTOP(1)
|
||||
);
|
||||
T0V(FG_ALPHA_FUNC, 0x00000000);
|
||||
T0V(ZB_CNTL, 0x00000000);
|
||||
T0V(ZB_ZSTENCILCNTL, 0x00000000);
|
||||
T0V(ZB_STENCILREFMASK, 0x00000000);
|
||||
T0V(ZB_STENCILREFMASK_BF, 0x00000000);
|
||||
|
||||
T0V(FG_ALPHA_VALUE, 0x00000000);
|
||||
T0V(RB3D_ROPCNTL, 0x00000000);
|
||||
T0V(RB3D_BLENDCNTL, 0x00000000);
|
||||
T0V(RB3D_ABLENDCNTL, 0x00000000);
|
||||
T0V(RB3D_COLOR_CHANNEL_MASK
|
||||
, RB3D_COLOR_CHANNEL_MASK__BLUE_MASK(1)
|
||||
| RB3D_COLOR_CHANNEL_MASK__GREEN_MASK(1)
|
||||
| RB3D_COLOR_CHANNEL_MASK__RED_MASK(1)
|
||||
| RB3D_COLOR_CHANNEL_MASK__ALPHA_MASK(1)
|
||||
);
|
||||
T0V(RB3D_DITHER_CTL, 0x00000000);
|
||||
T0V(RB3D_CONSTANT_COLOR_AR, 0x00000000);
|
||||
T0V(RB3D_CONSTANT_COLOR_GB, 0x00000000);
|
||||
|
||||
T0V(SC_CLIP_0_A, 0x00000000);
|
||||
T0V(SC_CLIP_0_B, 0xffffffff);
|
||||
T0V(SC_SCREENDOOR, 0x00ffffff);
|
||||
|
||||
T0V(GB_SELECT, 0x00000000);
|
||||
T0V(FG_FOG_BLEND, 0x00000000);
|
||||
T0V(GA_OFFSET, 0x00000000);
|
||||
T0V(SU_TEX_WRAP, 0x00000000);
|
||||
T0Vf(SU_DEPTH_SCALE, 16777215.0f);
|
||||
T0V(SU_DEPTH_OFFSET, 0x00000000);
|
||||
T0V(SC_EDGERULE
|
||||
, SC_EDGERULE__ER_TRI(5) // L-in,R-out,HT-in,HB-in
|
||||
| SC_EDGERULE__ER_POINT(9) // L-out,R-in,HT-in,HB-out
|
||||
| SC_EDGERULE__ER_LINE_LR(5) // L-in,R-out,HT-in,HB-out
|
||||
| SC_EDGERULE__ER_LINE_RL(9) // L-out,R-in,HT-in,HB-out
|
||||
| SC_EDGERULE__ER_LINE_TB(26) // T-in,B-out,VL-out,VR-in
|
||||
| SC_EDGERULE__ER_LINE_BT(22) // T-out,B-in,VL-out,VR-in
|
||||
);
|
||||
T0V(RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
|
||||
, RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__BLUE(1)
|
||||
| RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__GREEN(1)
|
||||
| RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__RED(1)
|
||||
| RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD__ALPHA(1)
|
||||
);
|
||||
T0V(RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
|
||||
, RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__BLUE(254)
|
||||
| RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__GREEN(254)
|
||||
| RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__RED(254)
|
||||
| RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD__ALPHA(254)
|
||||
);
|
||||
T0V(GA_COLOR_CONTROL_PS3, 0x00000000);
|
||||
T0V(SU_TEX_WRAP_PS3, 0x00000000);
|
||||
T0V(VAP_PVS_VTX_TIMEOUT_REG
|
||||
, VAP_PVS_VTX_TIMEOUT_REG__CLK_COUNT(0xffff)
|
||||
);
|
||||
T0Vf(VAP_GB_VERT_CLIP_ADJ, 1.0f);
|
||||
T0Vf(VAP_GB_VERT_DISC_ADJ, 1.0f);
|
||||
T0Vf(VAP_GB_HORZ_CLIP_ADJ, 1.0f);
|
||||
T0Vf(VAP_GB_HORZ_DISC_ADJ, 1.0f);
|
||||
T0V(VAP_PSC_SGN_NORM_CNTL
|
||||
, VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_0(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_1(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_2(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_3(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_4(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_5(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_6(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_7(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_8(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_9(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_10(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_11(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_12(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_13(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_14(2)
|
||||
| VAP_PSC_SGN_NORM_CNTL__SGN_NORM_METHOD_15(2)
|
||||
);
|
||||
T0V(VAP_TEX_TO_COLOR_CNTL, 0x00000000);
|
||||
|
||||
T0V(VAP_CNTL
|
||||
, VAP_CNTL__PVS_NUM_SLOTS(10)
|
||||
| VAP_CNTL__PVS_NUM_CNTLRS(5)
|
||||
| VAP_CNTL__PVS_NUM_FPUS(5)
|
||||
| VAP_CNTL__VAP_NO_RENDER(0)
|
||||
| VAP_CNTL__VF_MAX_VTX_NUM(12)
|
||||
| VAP_CNTL__DX_CLIP_SPACE_DEF(0)
|
||||
| VAP_CNTL__TCL_STATE_OPTIMIZATION(1)
|
||||
);
|
||||
T0V(VAP_PVS_FLOW_CNTL_OPC, 0x00000000);
|
||||
|
||||
T0(VAP_PVS_FLOW_CNTL_ADDRS_LW_0, 31);
|
||||
for (int i = 0; i < 32; i++)
|
||||
ib[ix++].u32 = 0x00000000;
|
||||
|
||||
T0(VAP_PVS_FLOW_CNTL_LOOP_INDEX_0, 15);
|
||||
for (int i = 0; i < 16; i++)
|
||||
ib[ix++].u32 = 0x00000000;
|
||||
|
||||
T0V(VAP_PVS_VECTOR_INDX_REG, 0x00000600);
|
||||
T0_ONE_REG(VAP_PVS_VECTOR_DATA_REG_128, 23);
|
||||
for (int i = 0; i < 24; i++)
|
||||
ib[ix++].u32 = 0x00000000;
|
||||
|
||||
T0V(VAP_VTX_STATE_CNTL
|
||||
, VAP_VTX_STATE_CNTL__COLOR_0_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_1_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_2_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_3_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_4_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_5_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_6_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__COLOR_7_ASSEMBLY_CNTL(1)
|
||||
| VAP_VTX_STATE_CNTL__UPDATE_USER_COLOR_0_ENA(0)
|
||||
);
|
||||
|
||||
T0V(GB_ENABLE, 0x00000000);
|
||||
T0V(VAP_CNTL_STATUS, 0x00000000);
|
||||
T0V(VAP_CLIP_CNTL
|
||||
, VAP_CLIP_CNTL__PS_UCP_MODE(3)
|
||||
);
|
||||
T0V(GA_POINT_SIZE
|
||||
, GA_POINT_SIZE__HEIGHT(6)
|
||||
| GA_POINT_SIZE__WIDTH(6)
|
||||
);
|
||||
T0V(GA_POINT_MINMAX
|
||||
, GA_POINT_MINMAX__MIN_SIZE(6)
|
||||
| GA_POINT_MINMAX__MAX_SIZE(6)
|
||||
);
|
||||
T0V(GA_LINE_CNTL
|
||||
, GA_LINE_CNTL__WIDTH(6)
|
||||
| GA_LINE_CNTL__END_TYPE(2)
|
||||
| GA_LINE_CNTL__SORT(0)
|
||||
);
|
||||
T0V(SU_POLY_OFFSET_ENABLE, 0x00000000);
|
||||
T0V(SU_CULL_MODE, 0x00000000);
|
||||
T0V(GA_LINE_STIPPLE_CONFIG, 0x00000000);
|
||||
T0V(GA_LINE_STIPPLE_VALUE, 0x00000000);
|
||||
T0V(GA_POLY_MODE, 0x00000000);
|
||||
T0V(GA_ROUND_MODE
|
||||
, GA_ROUND_MODE__GEOMETRY_ROUND(1)
|
||||
| GA_ROUND_MODE__COLOR_ROUND(0)
|
||||
| GA_ROUND_MODE__RGB_CLAMP(1)
|
||||
| GA_ROUND_MODE__ALPHA_CLAMP(1)
|
||||
| GA_ROUND_MODE__GEOMETRY_MASK(0)
|
||||
);
|
||||
T0V(SC_CLIP_RULE
|
||||
, SC_CLIP_RULE__CLIP_RULE(0xffff));
|
||||
T0Vf(GA_POINT_S0, 0.0f);
|
||||
T0Vf(GA_POINT_T0, 1.0f);
|
||||
T0Vf(GA_POINT_S1, 1.0f);
|
||||
T0Vf(GA_POINT_T1, 0.0f);
|
||||
T0V(US_OUT_FMT_0
|
||||
, US_OUT_FMT__OUT_FMT(0) // C4_8
|
||||
| US_OUT_FMT__C0_SEL(3) // Blue
|
||||
| US_OUT_FMT__C1_SEL(2) // Green
|
||||
| US_OUT_FMT__C2_SEL(1) // Red
|
||||
| US_OUT_FMT__C3_SEL(0) // Alpha
|
||||
| US_OUT_FMT__OUT_SIGN(0)
|
||||
);
|
||||
T0V(US_OUT_FMT_1
|
||||
, US_OUT_FMT__OUT_FMT(15) // render target is not used
|
||||
);
|
||||
T0V(US_OUT_FMT_2
|
||||
, US_OUT_FMT__OUT_FMT(15) // render target is not used
|
||||
);
|
||||
T0V(US_OUT_FMT_2
|
||||
, US_OUT_FMT__OUT_FMT(15) // render target is not used
|
||||
);
|
||||
T0V(GB_MSPOS0
|
||||
, GB_MSPOS0__MS_X0(6)
|
||||
| GB_MSPOS0__MS_Y0(6)
|
||||
| GB_MSPOS0__MS_X1(6)
|
||||
| GB_MSPOS0__MS_Y1(6)
|
||||
| GB_MSPOS0__MS_X2(6)
|
||||
| GB_MSPOS0__MS_Y2(6)
|
||||
| GB_MSPOS0__MSBD0_Y(6)
|
||||
| GB_MSPOS0__MSBD0_X(6)
|
||||
);
|
||||
T0V(GB_MSPOS1
|
||||
, GB_MSPOS1__MS_X3(6)
|
||||
| GB_MSPOS1__MS_Y3(6)
|
||||
| GB_MSPOS1__MS_X4(6)
|
||||
| GB_MSPOS1__MS_Y4(6)
|
||||
| GB_MSPOS1__MS_X5(6)
|
||||
| GB_MSPOS1__MS_Y5(6)
|
||||
| GB_MSPOS1__MSBD1(6)
|
||||
);
|
||||
T0V(US_CONFIG
|
||||
, US_CONFIG__ZERO_TIMES_ANYTHING_EQUALS_ZERO(1)
|
||||
);
|
||||
T0V(US_PIXSIZE
|
||||
, US_PIXSIZE__PIX_SIZE(1)
|
||||
);
|
||||
T0V(US_FC_CTRL, 0);
|
||||
|
||||
T0V(FG_DEPTH_SRC, 0x00000000);
|
||||
T0V(US_W_FMT, 0x00000000);
|
||||
T0V(VAP_PVS_CONST_CNTL, 0x00000000);
|
||||
T0V(TX_INVALTAGS, 0x00000000);
|
||||
T0V(TX_ENABLE, 0x00000000);
|
||||
T0V(VAP_INDEX_OFFSET, 0x00000000);
|
||||
T0V(GA_COLOR_CONTROL
|
||||
, GA_COLOR_CONTROL__RGB0_SHADING(2)
|
||||
| GA_COLOR_CONTROL__ALPHA0_SHADING(2)
|
||||
| GA_COLOR_CONTROL__RGB1_SHADING(2)
|
||||
| GA_COLOR_CONTROL__ALPHA1_SHADING(2)
|
||||
| GA_COLOR_CONTROL__RGB2_SHADING(2)
|
||||
| GA_COLOR_CONTROL__ALPHA2_SHADING(2)
|
||||
| GA_COLOR_CONTROL__RGB3_SHADING(2)
|
||||
| GA_COLOR_CONTROL__ALPHA3_SHADING(2)
|
||||
| GA_COLOR_CONTROL__PROVOKING_VERTEX(3)
|
||||
);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// SC
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0V(SC_SCISSOR0
|
||||
, SC_SCISSOR0__XS0(0)
|
||||
| SC_SCISSOR0__YS0(0)
|
||||
);
|
||||
T0V(SC_SCISSOR1
|
||||
, SC_SCISSOR1__XS1(1600 - 1)
|
||||
| SC_SCISSOR1__YS1(1200 - 1)
|
||||
);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// VAP
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0Vf(VAP_VPORT_XSCALE, 800.0f);
|
||||
T0Vf(VAP_VPORT_XOFFSET, 800.0f);
|
||||
T0Vf(VAP_VPORT_YSCALE, -600.0f);
|
||||
T0Vf(VAP_VPORT_YOFFSET, 600.0f);
|
||||
T0Vf(VAP_VPORT_ZSCALE, 0.5f);
|
||||
T0Vf(VAP_VPORT_ZOFFSET, 0.5f);
|
||||
|
||||
T0V(VAP_VTE_CNTL
|
||||
, VAP_VTE_CNTL__VPORT_X_SCALE_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_X_OFFSET_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_Y_SCALE_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_Y_OFFSET_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_Z_SCALE_ENA(1)
|
||||
| VAP_VTE_CNTL__VPORT_Z_OFFSET_ENA(1)
|
||||
| VAP_VTE_CNTL__VTX_XY_FMT(0)
|
||||
| VAP_VTE_CNTL__VTX_Z_FMT(0)
|
||||
| VAP_VTE_CNTL__VTX_W0_FMT(1)
|
||||
| VAP_VTE_CNTL__SERIAL_PROC_ENA(0)
|
||||
);
|
||||
|
||||
T0V(VAP_VF_MAX_VTX_INDX
|
||||
, VAP_VF_MAX_VTX_INDX__MAX_INDX(2)
|
||||
);
|
||||
T0V(VAP_VF_MIN_VTX_INDX
|
||||
, VAP_VF_MIN_VTX_INDX__MIN_INDX(0)
|
||||
);
|
||||
T0V(VAP_VTX_SIZE
|
||||
, VAP_VTX_SIZE__DWORDS_PER_VTX(6)
|
||||
);
|
||||
|
||||
T0V(VAP_PROG_STREAM_CNTL_0
|
||||
, VAP_PROG_STREAM_CNTL__DATA_TYPE_0(2)
|
||||
| VAP_PROG_STREAM_CNTL__SKIP_DWORDS_0(0)
|
||||
| VAP_PROG_STREAM_CNTL__DST_VEC_LOC_0(0)
|
||||
| VAP_PROG_STREAM_CNTL__LAST_VEC_0(0)
|
||||
| VAP_PROG_STREAM_CNTL__SIGNED_0(0)
|
||||
| VAP_PROG_STREAM_CNTL__NORMALIZE_0(0)
|
||||
| VAP_PROG_STREAM_CNTL__DATA_TYPE_1(2)
|
||||
| VAP_PROG_STREAM_CNTL__SKIP_DWORDS_1(0)
|
||||
| VAP_PROG_STREAM_CNTL__DST_VEC_LOC_1(1)
|
||||
| VAP_PROG_STREAM_CNTL__LAST_VEC_1(1)
|
||||
| VAP_PROG_STREAM_CNTL__SIGNED_1(0)
|
||||
| VAP_PROG_STREAM_CNTL__NORMALIZE_1(0)
|
||||
);
|
||||
T0V(VAP_PROG_STREAM_CNTL_EXT_0
|
||||
, VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_X_0(0)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Y_0(1)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Z_0(2)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_W_0(5)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__WRITE_ENA_0(15)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_X_1(0)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Y_1(1)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_Z_1(2)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__SWIZZLE_SELECT_W_1(5)
|
||||
| VAP_PROG_STREAM_CNTL_EXT__WRITE_ENA_1(15)
|
||||
);
|
||||
|
||||
T0V(VAP_VSM_VTX_ASSM, 0x00000401); // undocumented
|
||||
|
||||
T0V(VAP_OUT_VTX_FMT_0
|
||||
, VAP_OUT_VTX_FMT_0__VTX_POS_PRESENT(1));
|
||||
T0V(VAP_OUT_VTX_FMT_1
|
||||
, VAP_OUT_VTX_FMT_1__TEX_0_COMP_CNT(4)
|
||||
);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// VAP_PVS
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0V(VAP_PVS_CODE_CNTL_0
|
||||
, VAP_PVS_CODE_CNTL_0__PVS_FIRST_INST(0)
|
||||
| VAP_PVS_CODE_CNTL_0__PVS_XYZW_VALID_INST(1)
|
||||
| VAP_PVS_CODE_CNTL_0__PVS_LAST_INST(1)
|
||||
);
|
||||
T0V(VAP_PVS_CODE_CNTL_1
|
||||
, VAP_PVS_CODE_CNTL_1__PVS_LAST_VTX_SRC_INST(1)
|
||||
);
|
||||
|
||||
T0V(VAP_PVS_VECTOR_INDX_REG
|
||||
, VAP_PVS_VECTOR_INDX_REG__OCTWORD_OFFSET(0)
|
||||
);
|
||||
|
||||
const uint32_t vertex_shader[] = {
|
||||
0x00702203,
|
||||
0x01d10021,
|
||||
0x01248021,
|
||||
0x01248021,
|
||||
0x00f00203,
|
||||
0x01510001,
|
||||
0x01248001,
|
||||
0x01248001,
|
||||
};
|
||||
const int vertex_shader_length = (sizeof (vertex_shader)) / (sizeof (vertex_shader[0]));
|
||||
printf("vs length %d\n", vertex_shader_length);
|
||||
|
||||
T0_ONE_REG(VAP_PVS_VECTOR_DATA_REG_128, vertex_shader_length - 1);
|
||||
for (int i = 0; i < vertex_shader_length; i++) {
|
||||
ib[ix++].u32 = vertex_shader[i];
|
||||
}
|
||||
|
||||
T0V(VAP_PVS_STATE_FLUSH_REG, 0x00000000);
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// RS
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0V(RS_IP_0
|
||||
, RS_IP__TEX_PTR_S(0)
|
||||
| RS_IP__TEX_PTR_T(1)
|
||||
| RS_IP__TEX_PTR_R(2)
|
||||
| RS_IP__TEX_PTR_Q(3)
|
||||
| RS_IP__COL_PTR(0)
|
||||
| RS_IP__COL_FMT(0)
|
||||
| RS_IP__OFFSET_EN(0)
|
||||
);
|
||||
T0V(RS_COUNT
|
||||
, RS_COUNT__IT_COUNT(4)
|
||||
| RS_COUNT__IC_COUNT(0)
|
||||
| RS_COUNT__W_ADDR(0)
|
||||
| RS_COUNT__HIRES_EN(1)
|
||||
);
|
||||
T0V(RS_INST_0
|
||||
, RS_INST__TEX_ID(0)
|
||||
| RS_INST__TEX_CN(1)
|
||||
| RS_INST__TEX_ADDR(0)
|
||||
| RS_INST__COL_ID(0)
|
||||
| RS_INST__COL_CN(0)
|
||||
| RS_INST__COL_ADDR(0)
|
||||
| RS_INST__TEX_ADJ(0)
|
||||
| RS_INST__W_CN(0)
|
||||
);
|
||||
|
||||
T0V(RS_INST_COUNT, 0x00000000);
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// GA_US
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
T0V(US_CODE_RANGE
|
||||
, US_CODE_RANGE__CODE_ADDR(0)
|
||||
| US_CODE_RANGE__CODE_SIZE(0)
|
||||
);
|
||||
T0V(US_CODE_OFFSET
|
||||
, US_CODE_OFFSET__OFFSET_ADDR(0)
|
||||
);
|
||||
T0V(US_CODE_ADDR
|
||||
, US_CODE_ADDR__START_ADDR(0)
|
||||
| US_CODE_ADDR__END_ADDR(0)
|
||||
);
|
||||
|
||||
const uint32_t fragment_shader[] = {
|
||||
0x00078005,
|
||||
0x08020000,
|
||||
0x08020080,
|
||||
0x1c440220,
|
||||
0x1cc18003,
|
||||
0x00000005,
|
||||
};
|
||||
const int fragment_shader_length = (sizeof (fragment_shader)) / (sizeof (fragment_shader[0]));
|
||||
printf("fs length %d\n", fragment_shader_length);
|
||||
|
||||
T0V(GA_US_VECTOR_INDEX, 0x00000000);
|
||||
T0_ONE_REG(GA_US_VECTOR_DATA, fragment_shader_length - 1);
|
||||
for (int i = 0; i < fragment_shader_length; i++) {
|
||||
ib[ix++].u32 = fragment_shader[i];
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// 3D_DRAW
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
const float vertices[] = {
|
||||
// position // color
|
||||
0.5f, -0.5f, 0.0f, 1.0f, 0.0f, 0.0f, // bottom right
|
||||
-0.5f, -0.5f, 0.0f, 0.0f, 1.0f, 0.0f, // bottom left
|
||||
0.0f, 0.5f, 0.0f, 0.0f, 0.0f, 1.0f // top
|
||||
};
|
||||
const int vertices_length = (sizeof (vertices)) / (sizeof (vertices[0]));
|
||||
printf("vtx length %d\n", vertices_length);
|
||||
T3(_3D_DRAW_IMMD_2, (1 + vertices_length) - 1);
|
||||
ib[ix++].u32
|
||||
= VAP_VF_CNTL__PRIM_TYPE(4)
|
||||
| VAP_VF_CNTL__PRIM_WALK(3)
|
||||
| VAP_VF_CNTL__INDEX_SIZE(0)
|
||||
| VAP_VF_CNTL__VTX_REUSE_DIS(0)
|
||||
| VAP_VF_CNTL__DUAL_INDEX_MODE(0)
|
||||
| VAP_VF_CNTL__USE_ALT_NUM_VERTS(0)
|
||||
| VAP_VF_CNTL__NUM_VERTICES(3)
|
||||
;
|
||||
for (int i = 0; i < vertices_length; i++) {
|
||||
ib[ix++].f32 = vertices[i];
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// padding
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
while ((ix % 8) != 0) {
|
||||
ib[ix++].u32 = 0x80000000;
|
||||
}
|
||||
|
||||
return ix;
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
int ret;
|
||||
int fd = open("/dev/dri/card0", O_RDWR | O_CLOEXEC);
|
||||
|
||||
const int colorbuffer_size = 1600 * 1200 * 4;
|
||||
int colorbuffer_handle;
|
||||
void * colorbuffer_ptr;
|
||||
int flush_handle;
|
||||
|
||||
// colorbuffer
|
||||
{
|
||||
struct drm_radeon_gem_create args = {
|
||||
.size = colorbuffer_size,
|
||||
.alignment = 4096,
|
||||
.handle = 0,
|
||||
.initial_domain = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.flags = 4
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE, &args, (sizeof (struct drm_radeon_gem_create)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_CREATE)");
|
||||
}
|
||||
assert(args.handle != 0);
|
||||
|
||||
colorbuffer_handle = args.handle;
|
||||
}
|
||||
|
||||
{
|
||||
struct drm_radeon_gem_mmap mmap_args = {
|
||||
.handle = colorbuffer_handle,
|
||||
.offset = 0,
|
||||
.size = colorbuffer_size,
|
||||
};
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_MMAP, &mmap_args, (sizeof (struct drm_radeon_gem_mmap)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_MMAP)");
|
||||
}
|
||||
|
||||
colorbuffer_ptr = mmap(0, mmap_args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
|
||||
fd, mmap_args.addr_ptr);
|
||||
}
|
||||
|
||||
{ // clear colorbuffer
|
||||
for (int i = 0; i < colorbuffer_size / 4; i++) {
|
||||
((uint32_t*)colorbuffer_ptr)[i] = 0;
|
||||
}
|
||||
asm volatile ("" ::: "memory");
|
||||
}
|
||||
|
||||
// flush
|
||||
{
|
||||
struct drm_radeon_gem_create args = {
|
||||
.size = 4096,
|
||||
.alignment = 4096,
|
||||
.handle = 0,
|
||||
.initial_domain = 2, // GTT
|
||||
.flags = 0
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_GEM_CREATE,
|
||||
&args, (sizeof (args)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_GEM_CREATE)");
|
||||
}
|
||||
assert(args.handle != 0);
|
||||
flush_handle = args.handle;
|
||||
}
|
||||
|
||||
|
||||
fprintf(stderr, "colorbuffer handle %d\n", colorbuffer_handle);
|
||||
|
||||
struct drm_radeon_cs_reloc relocs[] = {
|
||||
{
|
||||
.handle = colorbuffer_handle,
|
||||
.read_domains = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.write_domain = 4, // RADEON_GEM_DOMAIN_VRAM
|
||||
.flags = 8,
|
||||
},
|
||||
{
|
||||
.handle = flush_handle,
|
||||
.read_domains = 2, // RADEON_GEM_DOMAIN_GTT
|
||||
.write_domain = 2, // RADEON_GEM_DOMAIN_GTT
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
uint32_t flags[2] = {
|
||||
5, // RADEON_CS_KEEP_TILING_FLAGS | RADEON_CS_END_OF_FRAME
|
||||
0, // RADEON_CS_RING_GFX
|
||||
};
|
||||
|
||||
int ib_dwords = indirect_buffer();
|
||||
//int ib_dwords = (sizeof (ib2)) / (sizeof (ib2[0]));
|
||||
|
||||
struct drm_radeon_cs_chunk chunks[3] = {
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_IB,
|
||||
.length_dw = ib_dwords,
|
||||
.chunk_data = (uint64_t)(uintptr_t)ib,
|
||||
},
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_RELOCS,
|
||||
.length_dw = (sizeof (relocs)) / (sizeof (uint32_t)),
|
||||
.chunk_data = (uint64_t)(uintptr_t)relocs,
|
||||
},
|
||||
{
|
||||
.chunk_id = RADEON_CHUNK_ID_FLAGS,
|
||||
.length_dw = (sizeof (flags)) / (sizeof (uint32_t)),
|
||||
.chunk_data = (uint64_t)(uintptr_t)&flags,
|
||||
},
|
||||
};
|
||||
|
||||
uint64_t chunks_array[3] = {
|
||||
(uint64_t)(uintptr_t)&chunks[0],
|
||||
(uint64_t)(uintptr_t)&chunks[1],
|
||||
(uint64_t)(uintptr_t)&chunks[2],
|
||||
};
|
||||
|
||||
struct drm_radeon_cs cs = {
|
||||
.num_chunks = 3,
|
||||
.cs_id = 0,
|
||||
.chunks = (uint64_t)(uintptr_t)chunks_array,
|
||||
.gart_limit = 0,
|
||||
.vram_limit = 0,
|
||||
};
|
||||
|
||||
ret = drmCommandWriteRead(fd, DRM_RADEON_CS, &cs, (sizeof (struct drm_radeon_cs)));
|
||||
if (ret != 0) {
|
||||
perror("drmCommandWriteRead(DRM_RADEON_CS)");
|
||||
}
|
||||
|
||||
struct drm_radeon_gem_wait_idle args = {
|
||||
.handle = flush_handle
|
||||
};
|
||||
while (drmCommandWrite(fd, DRM_RADEON_GEM_WAIT_IDLE, &args, (sizeof (struct drm_radeon_gem_wait_idle))) == -EBUSY);
|
||||
|
||||
int out_fd = open("colorbuffer.data", O_RDWR|O_CREAT);
|
||||
assert(out_fd >= 0);
|
||||
ssize_t write_length = write(out_fd, colorbuffer_ptr, colorbuffer_size);
|
||||
assert(write_length == colorbuffer_size);
|
||||
close(out_fd);
|
||||
|
||||
int mm_fd = open("/sys/kernel/debug/radeon_vram_mm", O_RDONLY);
|
||||
assert(mm_fd >= 0);
|
||||
char buf[4096];
|
||||
while (true) {
|
||||
ssize_t read_length = read(mm_fd, buf, 4096);
|
||||
assert(read_length >= 0);
|
||||
write(STDOUT_FILENO, buf, read_length);
|
||||
if (read_length < 4096) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
close(mm_fd);
|
||||
|
||||
munmap(colorbuffer_ptr, colorbuffer_size);
|
||||
|
||||
close(fd);
|
||||
}
|
||||
4
regs/bits/cp_csq2_stat.txt
Normal file
4
regs/bits/cp_csq2_stat.txt
Normal file
@ -0,0 +1,4 @@
|
||||
Field Name Bits Default Description
|
||||
CSQ_WPTR_INDIRECT 9:0 none Current Write Pointer into the Indirect Queue. Default = 0.
|
||||
CSQ_RPTR_INDIRECT2 19:10 none Current Read Pointer into the Indirect Queue. Default = 0.
|
||||
CSQ_WPTR_INDIRECT2 29:20 none Current Write Pointer into the Indirect Queue. Default = 0.
|
||||
4
regs/bits/cp_csq_addr.txt
Normal file
4
regs/bits/cp_csq_addr.txt
Normal file
@ -0,0 +1,4 @@
|
||||
Field Name Bits Default Description
|
||||
CSQ_ADDR 11:2 none Address into the Command Stream Queue which is to be
|
||||
read from. Used for debug, to read the contents of the
|
||||
Command Stream Queue.
|
||||
2
regs/bits/cp_csq_aper_indirect.txt
Normal file
2
regs/bits/cp_csq_aper_indirect.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
CP_CSQ_APER_INDIRECT 31:0 none IB1 Aperture
|
||||
2
regs/bits/cp_csq_aper_indirect2.txt
Normal file
2
regs/bits/cp_csq_aper_indirect2.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
CP_CSQ_APER_INDIRECT2 31:0 none IB2 Aperture
|
||||
2
regs/bits/cp_csq_aper_primary.txt
Normal file
2
regs/bits/cp_csq_aper_primary.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
CP_CSQ_APER_PRIMARY 31:0 none Primary Aperture
|
||||
7
regs/bits/cp_csq_avail.txt
Normal file
7
regs/bits/cp_csq_avail.txt
Normal file
@ -0,0 +1,7 @@
|
||||
Field Name Bits Default Description
|
||||
CSQ_CNT_PRIMARY 9:0 none Count of available dwords in the queue for the Primary
|
||||
Stream. Read Only.
|
||||
CSQ_CNT_INDIRECT 19:10 none Count of available dwords in the queue for the Indirect
|
||||
Stream. Read Only.
|
||||
CSQ_CNT_INDIRECT2 29:20 none Count of available dwords in the queue for the Indirect
|
||||
Stream. Read Only.
|
||||
16
regs/bits/cp_csq_cntl.txt
Normal file
16
regs/bits/cp_csq_cntl.txt
Normal file
@ -0,0 +1,16 @@
|
||||
Field Name Bits Default Description
|
||||
CSQ_MODE 31:28 0x0 Command Stream Queue Mode. Controls whether each
|
||||
command stream is enabled, and whether it is in push
|
||||
mode (Programmed I/O), or pull mode (Bus-Master).
|
||||
Encodings are chosen to be compatible with Rage128.
|
||||
POSSIBLE VALUES:
|
||||
00 - Primary Disabled, Indirect Disabled.
|
||||
01 - Primary PIO, Indirect Disabled.
|
||||
02 - Primary BM, Indirect Disabled.
|
||||
03 - Primary PIO, Indirect BM.
|
||||
04 - Primary BM, Indirect BM.
|
||||
05 - Primary PIO, Indirect BM.
|
||||
06 - Primary BM, Indirect BM.
|
||||
07 - Primary PIO, Indirect BM.
|
||||
08 - Primary BM, Indirect BM.
|
||||
15 - Primary PIO, Indirect PIO
|
||||
5
regs/bits/cp_csq_data.txt
Normal file
5
regs/bits/cp_csq_data.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
CSQ_DATA 31:0 none Data from the Command Stream Queue, from location
|
||||
pointed to by the CP_CSQ_ADDR register. Used for
|
||||
debug, to read the contents of the Command Stream
|
||||
Queue.
|
||||
34
regs/bits/cp_csq_mode.txt
Normal file
34
regs/bits/cp_csq_mode.txt
Normal file
@ -0,0 +1,34 @@
|
||||
Field Name Bits Default Description
|
||||
INDIRECT2_START 6:0 none Start location of Indirect Queue #2 in the command
|
||||
cache. This value also sets the size in double octwords of
|
||||
the Indirect Queue #1 cache that will reside in locations
|
||||
INDIRECT1_START to (INDIRECT2_START - 1). The
|
||||
Indirect Queue #2 will reside in locations
|
||||
INDIRECT2_START to 0x5f. The minimum size of the
|
||||
Indirect Queues must be at least twice the MAX_FETCH
|
||||
size as programmed in the CP_RB_CNTL register.
|
||||
INDIRECT1_START 14:8 none Start location of Indirect Queue #1 in the command
|
||||
cache. This value is also the size in double octwords of
|
||||
the Primary Queue cache that will reside in locations 0 to
|
||||
(INDIRECT1_START - 1). The minimum size of the
|
||||
Primary Queue cache must be at least twice the
|
||||
MAX_FETCH size as programmed in the
|
||||
CP_RB_CNTL register.
|
||||
CSQ_INDIRECT2_MODE 26 0x0 POSSIBLE VALUES:
|
||||
00 - PIO
|
||||
01 - BM
|
||||
CSQ_INDIRECT2_ENABLE 27 0x0 Enables Indirect Buffer #2. If this bit is set, the
|
||||
CP_CSQ_MODE register overrides the operation of the
|
||||
CSQ_MODE variable in the CP_CSQ_CNTL register.
|
||||
CSQ_INDIRECT1_MODE 28 0x0 POSSIBLE VALUES:
|
||||
00 - PIO
|
||||
01 - BM
|
||||
CSQ_INDIRECT1_ENABLE 29 0x0 Enables Indirect Buffer #1. If this bit is set, the
|
||||
CP_CSQ_MODE register overrides the operation of the
|
||||
CSQ_MODE variable in the CP_CSQ_CNTL register.
|
||||
CSQ_PRIMARY_MODE 30 0x0 POSSIBLE VALUES:
|
||||
00 - PIO
|
||||
01 - BM
|
||||
CSQ_PRIMARY_ENABLE 31 0x0 Enables Primary Buffer. If this bit is set, the
|
||||
CP_CSQ_MODE register overrides the operation of the
|
||||
CSQ_MODE variable in the CP_CSQ_CNTL register.
|
||||
4
regs/bits/cp_csq_stat.txt
Normal file
4
regs/bits/cp_csq_stat.txt
Normal file
@ -0,0 +1,4 @@
|
||||
Field Name Bits Default Description
|
||||
CSQ_RPTR_PRIMARY 9:0 none Current Read Pointer into the Primary Queue. Default = 0.
|
||||
CSQ_WPTR_PRIMARY 19:10 none Current Write Pointer into the Primary Queue. Default = 0.
|
||||
CSQ_RPTR_INDIRECT 29:20 none Current Read Pointer into the Indirect Queue. Default = 0.
|
||||
3
regs/bits/cp_gui_command.txt
Normal file
3
regs/bits/cp_gui_command.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
CP_GUI_COMMAND 31:0 none Command for PIO DMAs to the GUI DMA. Only
|
||||
DWORD access is allowed to this register.
|
||||
3
regs/bits/cp_gui_dst_addr.txt
Normal file
3
regs/bits/cp_gui_dst_addr.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
CP_GUI_DST_ADDR 31:0 none Destination address for PIO DMAs to the GUI DMA.
|
||||
Only DWORD access is allowed to this register.
|
||||
3
regs/bits/cp_gui_src_addr.txt
Normal file
3
regs/bits/cp_gui_src_addr.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
CP_GUI_SRC_ADDR 31:0 none Source address for PIO DMAs to the GUI DMA. Only
|
||||
DWORD access is allowed to this register.
|
||||
4
regs/bits/cp_ib2_base.txt
Normal file
4
regs/bits/cp_ib2_base.txt
Normal file
@ -0,0 +1,4 @@
|
||||
Field Name Bits Default Description
|
||||
IB2_BASE 31:2 none Indirect Buffer 2 Base. Address of the beginning of the
|
||||
indirect buffer. Only DWORD access is allowed to this
|
||||
register.
|
||||
5
regs/bits/cp_ib2_bufz.txt
Normal file
5
regs/bits/cp_ib2_bufz.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
IB2_BUFSZ 22:0 0x0 Indirect Buffer 2 Size. This size is expressed in dwords.
|
||||
This field is an initiator to begin fetching commands
|
||||
from the Indirect Buffer. Only DWORD access is
|
||||
allowed to this register. Default = 0
|
||||
4
regs/bits/cp_ib_base.txt
Normal file
4
regs/bits/cp_ib_base.txt
Normal file
@ -0,0 +1,4 @@
|
||||
Field Name Bits Default Description
|
||||
IB_BASE 31:2 none Indirect Buffer Base. Address of the beginning of the
|
||||
indirect buffer. Only DWORD access is allowed to this
|
||||
register.
|
||||
5
regs/bits/cp_ib_bufsz.txt
Normal file
5
regs/bits/cp_ib_bufsz.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
IB_BUFSZ 22:0 0x0 Indirect Buffer Size. This size is expressed in dwords.
|
||||
This field is an initiator to begin fetching commands
|
||||
from the Indirect Buffer. Only DWORD access is
|
||||
allowed to this register. Default = 0
|
||||
18
regs/bits/cp_me_cntl.txt
Normal file
18
regs/bits/cp_me_cntl.txt
Normal file
@ -0,0 +1,18 @@
|
||||
Field Name Bits Default Description
|
||||
ME_STAT 15:0 none Status of MicroEngine internal registers. This value
|
||||
depends on the current value of the ME_STATMUX
|
||||
field. Read Only.
|
||||
ME_STATMUX 20:16 0x0 Selects which status is to be returned on the ME_STAT
|
||||
field.
|
||||
ME_BUSY 29 none Busy indicator for the MicroEngine. Read Only.
|
||||
POSSIBLE VALUES:
|
||||
00 - MicroEngine not busy.
|
||||
01 - MicroEngine is active.
|
||||
ME_MODE 30 0x1 Run-Mode of MicroEngine.
|
||||
POSSIBLE VALUES:
|
||||
00 - Single-Step Mode.
|
||||
01 - Free-running Mode.
|
||||
ME_STEP 31 0x0 Step the MicroEngine by one instruction. Writing a `1` to
|
||||
this field causes the MicroEngine to step by one
|
||||
instruction, if and only if the ME_MODE bit is a `0`.
|
||||
Write Only.
|
||||
5
regs/bits/cp_me_ram_addr.txt
Normal file
5
regs/bits/cp_me_ram_addr.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
ME_RAM_ADDR 7:0 none MicroEngine RAM Address (Write Mode) Writing this
|
||||
register puts the RAM access circuitry into `Write Mode`,
|
||||
which allows the address to auto-increment as data is
|
||||
written into the RAM.
|
||||
3
regs/bits/cp_me_ram_datah.txt
Normal file
3
regs/bits/cp_me_ram_datah.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
ME_RAM_DATAH 7:0 none MicroEngine RAM Data High Used to load the
|
||||
MicroEngine RAM.
|
||||
3
regs/bits/cp_me_ram_datal.txt
Normal file
3
regs/bits/cp_me_ram_datal.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
ME_RAM_DATAL 31:0 none MicroEngine RAM Data Low Used to load the
|
||||
MicroEngine RAM.
|
||||
5
regs/bits/cp_me_ram_raddr.txt
Normal file
5
regs/bits/cp_me_ram_raddr.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
ME_RAM_RADDR 7:0 none MicroEngine RAM Address (Read Mode) Writing
|
||||
this register puts the RAM access circuitry into `Read
|
||||
Mode` , which allows the address to auto-increment
|
||||
as data is read from the RAM. Write Only.
|
||||
3
regs/bits/cp_rb_base.txt
Normal file
3
regs/bits/cp_rb_base.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
RB_BASE 31:2 none Ring Buffer Base. Address of the beginning of the ring
|
||||
buffer.
|
||||
41
regs/bits/cp_rb_cntl.txt
Normal file
41
regs/bits/cp_rb_cntl.txt
Normal file
@ -0,0 +1,41 @@
|
||||
Field Name Bits Default Description
|
||||
RB_BUFSZ 5:0 0x0 Ring Buffer Size. This size is expressed in log2 of the
|
||||
actual size. Values 0 and 1 are clamped to an 8 DWORD
|
||||
ring buffer. A value of 2 to 22 will give a ring buffer:
|
||||
2^(RB_BUFSZ+1). Values greater than 22 will clamp to
|
||||
22. Default = 0
|
||||
RB_BLKSZ 13:8 0x0 Ring Buffer Block Size. This defines the number of
|
||||
quadwords that the Command Processor will read
|
||||
between updates to the host`s copy of the Read Pointer.
|
||||
This size is expressed in log2 of the actual size (in 64-bit
|
||||
quadwords). For example, for a block of 1024
|
||||
quadwords, you would program this field to 10(decimal).
|
||||
Default = 0
|
||||
BUF_SWAP 17:16 0x0 Endian Swap Control for Ring Buffer and Indirect
|
||||
Buffer. Only affects the chip behavior if the buffer
|
||||
resides in system memory.
|
||||
POSSIBLE VALUES:
|
||||
00 - No swap
|
||||
01 - 16-bit swap: 0xAABBCCDD becomes 0xBBAADDCC
|
||||
02 - 32-bit swap: 0xAABBCCDD becomes 0xDDCCBBAA
|
||||
03 - Half-dword swap: 0xAABBCCDD becomes 0xCCDDAABB
|
||||
MAX_FETCH 19:18 0x0 Maximum Fetch Size for any read request that the CP
|
||||
makes to memory.
|
||||
POSSIBLE VALUES:
|
||||
00 - 1 double octword. (32 bytes)
|
||||
01 - 2 double octwords. (64 bytes)
|
||||
02 - 4 double octwords. (128 bytes)
|
||||
03 - 8 double octwords. (256 bytes).
|
||||
RB_NO_UPDATE 27 0x0 Ring Buffer No Write to Read Pointer. The purpose of this
|
||||
control bit is to have a fall-back position if the bus-
|
||||
mastered write to system memory doesn`t work, in which
|
||||
case the driver will have to read the Graphics
|
||||
Controller`s copy of the Read Pointer directly, with some
|
||||
performance penalty.
|
||||
POSSIBLE VALUES:
|
||||
00 - Write to Host`s copy of Read Pointer in system memory.
|
||||
01 - Do not write to Host`s copy of Read pointer.
|
||||
RB_RPTR_WR_ENA 31 0x0 Ring Buffer Read Pointer Write Transfer Enable. When
|
||||
set the contents of the CP_RB_RPTR_WR register is
|
||||
transferred to the active read pointer (CP_RB_RPTR)
|
||||
whenever the CP_RB_WPTR register is written.
|
||||
3
regs/bits/cp_rb_rptr.txt
Normal file
3
regs/bits/cp_rb_rptr.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
RB_RPTR 22:0 none Ring Buffer Read Pointer. This is an index (in dwords)
|
||||
of the current element being read from the ring buffer.
|
||||
6
regs/bits/cp_rb_rptr_addr.txt
Normal file
6
regs/bits/cp_rb_rptr_addr.txt
Normal file
@ -0,0 +1,6 @@
|
||||
Field Name Bits Default Description
|
||||
RB_RPTR_SWAP 1:0 0x0 Swap control of the reported read pointer address. See
|
||||
CP_RB_CNTL.BUF_SWAP for the encoding.
|
||||
RB_RPTR_ADDR 31:2 0x0 Ring Buffer Read Pointer Address. Address of the Host`s
|
||||
copy of the Read Pointer. CP_RB_RPTR (RO) Ring
|
||||
Buffer Read Pointer
|
||||
3
regs/bits/cp_rb_rptr_wr.txt
Normal file
3
regs/bits/cp_rb_rptr_wr.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
RB_RPTR_WR 22:0 0x0 Writable Ring Buffer Read Pointer. Writable for
|
||||
updating the RB_RPTR after an ACPI.
|
||||
4
regs/bits/cp_rb_wptr.txt
Normal file
4
regs/bits/cp_rb_wptr.txt
Normal file
@ -0,0 +1,4 @@
|
||||
Field Name Bits Default Description
|
||||
RB_WPTR 22:0 0x0 Ring Buffer Write Pointer. This is an index (in dwords)
|
||||
of the last known element to be written to the ring buffer
|
||||
(by the host).
|
||||
9
regs/bits/cp_rb_wptr_delay.txt
Normal file
9
regs/bits/cp_rb_wptr_delay.txt
Normal file
@ -0,0 +1,9 @@
|
||||
Field Name Bits Default Description
|
||||
PRE_WRITE_TIMER 27:0 0x0 Pre-Write Timer. The number of clocks that a write to
|
||||
the CP_RB_WPTR register will be delayed until actually
|
||||
taking effect. Default = 0
|
||||
PRE_WRITE_LIMIT 31:28 0x0 Pre-Write Limit. The number of times that the
|
||||
CP_RB_WPTR register can be written (while the
|
||||
PRE_WRITE_TIMER has not expired) before the
|
||||
CP_RB_WPTR register is forced to be updated with the
|
||||
most recently written value. Default = 0
|
||||
2
regs/bits/cp_resync_addr.txt
Normal file
2
regs/bits/cp_resync_addr.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
RESYNC_ADDR 2:0 0x0 Scratch Register Offset Address.
|
||||
3
regs/bits/cp_resync_data.txt
Normal file
3
regs/bits/cp_resync_data.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
RESYNC_DATA 31:0 none Data written to selected Scratch Register when a sync
|
||||
pulse pair is received from the CBA and CBB.
|
||||
16
regs/bits/cp_stat.txt
Normal file
16
regs/bits/cp_stat.txt
Normal file
@ -0,0 +1,16 @@
|
||||
Field Name Bits Default Description
|
||||
MRU_BUSY 0 none Memory Read Unit Busy.
|
||||
MWU_BUSY 1 none Memory Write Unit Busy.
|
||||
RSIU_BUSY 2 none Register Backbone Input Interface Busy.
|
||||
RCIU_BUSY 3 none RBBM Output Interface Busy.
|
||||
CSF_PRIMARY_BUSY 9 none Primary Command Stream Fetcher Busy.
|
||||
CSF_INDIRECT_BUSY 10 none Indirect #1 Command Stream Fetcher Busy.
|
||||
CSQ_PRIMARY_BUSY 11 none Data in Command Queue for Primary Stream.
|
||||
CSQ_INDIRECT_BUSY 12 none Data in Command Queue for Indirect #1 Stream.
|
||||
CSI_BUSY 13 none Command Stream Interpreter Busy.
|
||||
CSF_INDIRECT2_BUSY 14 none Indirect #2 Command Stream Fetcher Busy.
|
||||
CSQ_INDIRECT2_BUSY 15 none Data in Command Queue for Indirect #2 Stream.
|
||||
GUIDMA_BUSY 28 none GUI DMA Engine Busy.
|
||||
VIDDMA_BUSY 29 none VID DMA Engine Busy.
|
||||
CMDSTRM_BUSY 30 none Command Stream Busy.
|
||||
CP_BUSY 31 none CP Busy.
|
||||
11
regs/bits/cp_vid_addr_cntl.txt
Normal file
11
regs/bits/cp_vid_addr_cntl.txt
Normal file
@ -0,0 +1,11 @@
|
||||
Field Name Bits Default Description
|
||||
SCRATCH_ALT_VP_WR 0 0x0 0=Physical (Default), 1=Virtual
|
||||
SCRATCH_VP_WR 1 0x0 0=Physical (Default), 1=Virtual
|
||||
RPTR_VP_UPDATE 2 0x0 0=Physical (Default), 1=Virtual
|
||||
VIDDMA_VP_WR 3 0x0 0=Physical (Default), 1=Virtual
|
||||
VIDDMA_VP_RD 4 0x0 0=Physical (Default), 1=Virtual
|
||||
GUIDMA_VP_WR 5 0x0 0=Physical (Default), 1=Virtual
|
||||
GUIDMA_VP_RD 6 0x0 0=Physical (Default), 1=Virtual
|
||||
INDR2_VP_FETCH 7 0x0 0=Physical (Default), 1=Virtual
|
||||
INDR1_VP_FETCH 8 0x0 0=Physical (Default), 1=Virtual
|
||||
RING_VP_FETCH 9 0x0 0=Physical (Default), 1=Virtual
|
||||
3
regs/bits/cp_vid_command.txt
Normal file
3
regs/bits/cp_vid_command.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
CP_VID_COMMAND 31:0 none Command for PIO DMAs to the VID DMA. Only
|
||||
DWORD access is allowed to this register.
|
||||
3
regs/bits/cp_vid_dst_addr.txt
Normal file
3
regs/bits/cp_vid_dst_addr.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
CP_VID_DST_ADDR 31:0 none Destination address for PIO DMAs to the VID DMA.
|
||||
Only DWORD access is allowed to this register.
|
||||
3
regs/bits/cp_vid_src_addr.txt
Normal file
3
regs/bits/cp_vid_src_addr.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
CP_VID_SRC_ADDR 31:0 none Source address for PIO DMAs to the VID DMA. Only
|
||||
DWORD access is allowed to this register.
|
||||
47
regs/bits/fg_alpha_func.txt
Normal file
47
regs/bits/fg_alpha_func.txt
Normal file
@ -0,0 +1,47 @@
|
||||
Field Name Bits Default Description
|
||||
AF_VAL 7:0 0x0 Specifies the 8-bit alpha compare value when
|
||||
AF_EN_8BIT is enabled
|
||||
AF_FUNC 10:8 0x0 Specifies the alpha compare function.
|
||||
POSSIBLE VALUES:
|
||||
00 - AF_NEVER
|
||||
01 - AF_LESS
|
||||
02 - AF_EQUAL
|
||||
03 - AF_LE
|
||||
04 - AF_GREATER
|
||||
05 - AF_NOTEQUAL
|
||||
06 - AF_GE
|
||||
07 - AF_ALWAYS
|
||||
AF_EN 11 0x0 Enables/Disables alpha compare function.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable alpha function.
|
||||
01 - Enable alpha function.
|
||||
AF_EN_8BIT 12 0x0 Enable 8-bit alpha compare function.
|
||||
POSSIBLE VALUES:
|
||||
00 - Default 10-bit alpha compare.
|
||||
01 - Enable 8-bit alpha compare.
|
||||
AM_EN 16 0x0 Enables/Disables alpha-to-mask function.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable alpha to mask function.
|
||||
01 - Enable alpha to mask function.
|
||||
AM_CFG 17 0x0 Specfies number of sub-pixel samples for alpha-to-mask
|
||||
function.
|
||||
POSSIBLE VALUES:
|
||||
00 - 2/4 sub-pixel samples.
|
||||
01 - 3/6 sub-pixel samples.
|
||||
DITH_EN 20 0x0 Enables/Disables RGB Dithering (Not supported in
|
||||
R520)
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable Dithering
|
||||
01 - Enable Dithering.
|
||||
ALP_OFF_EN 24 0x0 Alpha offset enable/disable (Not supported in R520)
|
||||
POSSIBLE VALUES:
|
||||
00 - Disables alpha offset of 2 (default r300 & rv350 behavior)
|
||||
01 - Enables offset of 2 on alpha coming in from the US
|
||||
DISCARD_ZERO_MASK_QUAD 25 0x0 Enable/Disable discard zero mask coverage quad to ZB
|
||||
POSSIBLE VALUES:
|
||||
00 - No discard of zero coverage mask quads
|
||||
01 - Discard zero coverage mask quads
|
||||
FP16_ENABLE 28 0x0 Enables/Disables FP16 alpha function
|
||||
POSSIBLE VALUES:
|
||||
00 - Default 10-bit alpha compare and alpha-to-mask function
|
||||
01 - Enable FP16 alpha compare and alpha-to-mask function
|
||||
3
regs/bits/fg_alpha_value.txt
Normal file
3
regs/bits/fg_alpha_value.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
AF_VAL 15:0 0x0 Specifies the alpha compare value, 0.10 fixed or FP16
|
||||
format
|
||||
4
regs/bits/fg_depth_src.txt
Normal file
4
regs/bits/fg_depth_src.txt
Normal file
@ -0,0 +1,4 @@
|
||||
Field Name Bits Default Description
|
||||
DEPTH_SRC 0 0x0 POSSIBLE VALUES:
|
||||
00 - Depth comes from scan converter as plane equation.
|
||||
01 - Depth comes from shader as four discrete values.
|
||||
11
regs/bits/fg_fog_blend.txt
Normal file
11
regs/bits/fg_fog_blend.txt
Normal file
@ -0,0 +1,11 @@
|
||||
Field Name Bits Default Description
|
||||
ENABLE 0 0x0 Enable for fog blending
|
||||
POSSIBLE VALUES:
|
||||
00 - Disables fog (output matches input color).
|
||||
01 - Enables fog.
|
||||
FN 2:1 0x0 Fog generation function
|
||||
POSSIBLE VALUES:
|
||||
00 - Fog function is linear
|
||||
01 - Fog function is exponential
|
||||
02 - Fog function is exponential squared
|
||||
03 - Fog is derived from constant fog factor
|
||||
2
regs/bits/fg_fog_color_b.txt
Normal file
2
regs/bits/fg_fog_color_b.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
BLUE 9:0 0x0 Blue component of fog color; (0.10) fixed format
|
||||
2
regs/bits/fg_fog_color_g.txt
Normal file
2
regs/bits/fg_fog_color_g.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
GREEN 9:0 0x0 Green component of fog color; (0.10) fixed format.
|
||||
2
regs/bits/fg_fog_color_r.txt
Normal file
2
regs/bits/fg_fog_color_r.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
RED 9:0 0x0 Red component of fog color; (0.10) fixed format.
|
||||
2
regs/bits/fg_fog_factor.txt
Normal file
2
regs/bits/fg_fog_factor.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
FACTOR 9:0 0x0 Constant fog factor; fixed (0.10) format.
|
||||
48
regs/bits/ga_color_control.txt
Normal file
48
regs/bits/ga_color_control.txt
Normal file
@ -0,0 +1,48 @@
|
||||
Field Name Bits Default Description
|
||||
RGB0_SHADING 1:0 0x0 Specifies solid, flat or Gouraud shading.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
ALPHA0_SHADING 3:2 0x0 Specifies solid, flat or Gouraud shading.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
RGB1_SHADING 5:4 0x0 Specifies solid, flat or Gouraud shading.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
ALPHA1_SHADING 7:6 0x0 Specifies solid, flat or Gouraud shading.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
RGB2_SHADING 9:8 0x0 Specifies solid, flat or Gouraud shading.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
ALPHA2_SHADING 11:10 0x0 Specifies solid, flat or Gouraud shading.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
RGB3_SHADING 13:12 0x0 Specifies solid, flat or Gouraud shading.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
ALPHA3_SHADING 15:14 0x0 Specifies solid, flat or Gouraud shading.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
PROVOKING_VERTEX 17:16 0x0 Specifies, for flat shaded polygons, which vertex holds
|
||||
the polygon color.
|
||||
POSSIBLE VALUES:
|
||||
00 - Provoking is first vertex
|
||||
01 - Provoking is second vertex
|
||||
02 - Provoking is third vertex
|
||||
03 - Provoking is always last vertex
|
||||
95
regs/bits/ga_color_control_ps3.txt
Normal file
95
regs/bits/ga_color_control_ps3.txt
Normal file
@ -0,0 +1,95 @@
|
||||
Field Name Bits Default Description
|
||||
TEX0_SHADING_PS3 1:0 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX1_SHADING_PS3 3:2 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX2_SHADING_PS3 5:4 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX3_SHADING_PS3 7:6 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX4_SHADING_PS3 9:8 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX5_SHADING_PS3 11:10 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX6_SHADING_PS3 13:12 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX7_SHADING_PS3 15:14 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX8_SHADING_PS3 17:16 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX9_SHADING_PS3 19:18 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
TEX10_SHADING_PS3 21:20 0x0 Specifies undefined(0), flat(1) and Gouraud(2/def)
|
||||
shading for tex10 components.
|
||||
POSSIBLE VALUES:
|
||||
00 - Solid fill color
|
||||
01 - Flat shading
|
||||
02 - Gouraud shading
|
||||
COLOR0_TEX_OVERRIDE 25:22 0x0 Specifies if each color should come from a texture and
|
||||
which one.
|
||||
POSSIBLE VALUES:
|
||||
00 - No override
|
||||
01 - Stuff texture 0
|
||||
02 - Stuff texture 1
|
||||
03 - Stuff texture 2
|
||||
04 - Stuff texture 3
|
||||
05 - Stuff texture 4
|
||||
06 - Stuff texture 5
|
||||
07 - Stuff texture 6
|
||||
08 - Stuff texture 7
|
||||
09 - Stuff texture 8/C2
|
||||
10 - Stuff texture 9/C3
|
||||
COLOR1_TEX_OVERRIDE 29:26 0x0 Specifies if each color should come from a texture and
|
||||
which one.
|
||||
POSSIBLE VALUES:
|
||||
00 - No override
|
||||
01 - Stuff texture 0
|
||||
02 - Stuff texture 1
|
||||
03 - Stuff texture 2
|
||||
04 - Stuff texture 3
|
||||
05 - Stuff texture 4
|
||||
06 - Stuff texture 5
|
||||
07 - Stuff texture 6
|
||||
08 - Stuff texture 7
|
||||
09 - Stuff texture 8/C2
|
||||
10 - Stuff texture 9/C3
|
||||
17
regs/bits/ga_enhance.txt
Normal file
17
regs/bits/ga_enhance.txt
Normal file
@ -0,0 +1,17 @@
|
||||
Field Name Bits Default Description
|
||||
DEADLOCK_CNTL 0 0x0 TCL/GA Deadlock control.
|
||||
POSSIBLE VALUES:
|
||||
00 - No effect.
|
||||
01 - Prevents TCL interface from deadlocking on GA side.
|
||||
FASTSYNC_CNTL 1 0x1 Enables Fast register/primitive switching
|
||||
POSSIBLE VALUES:
|
||||
00 - No effect.
|
||||
01 - Enables high-performance register/primitive switching.
|
||||
REG_READWRITE 2 0x0 R520+: When set, GA supports simultaneous register
|
||||
reads & writes
|
||||
POSSIBLE VALUES:
|
||||
00 - No effect.
|
||||
01 - Enables GA support of simultaneous register reads and writes.
|
||||
REG_NOSTALL 3 0x0 POSSIBLE VALUES:
|
||||
00 - No effect.
|
||||
01 - Enables GA support of no-stall reads for register read back.
|
||||
7
regs/bits/ga_fifo_cntl.txt
Normal file
7
regs/bits/ga_fifo_cntl.txt
Normal file
@ -0,0 +1,7 @@
|
||||
Field Name Bits Default Description
|
||||
VERTEX_FIFO 2:0 0x0 Number of words remaining in input vertex fifo before
|
||||
asserting nearly full
|
||||
INDEX_FIFO 5:3 0x0 Number of words remaining in input primitive fifo
|
||||
before asserting nearly full
|
||||
REG_FIFO 13:6 0x0 Number of words remaining in input register fifo before
|
||||
asserting nearly full
|
||||
2
regs/bits/ga_fill_a.txt
Normal file
2
regs/bits/ga_fill_a.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
COLOR_ALPHA 31:0 0x0 FP20 format for alpha fill.
|
||||
2
regs/bits/ga_fill_b.txt
Normal file
2
regs/bits/ga_fill_b.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
COLOR_BLUE 31:0 0x0 FP20 format for blue fill.
|
||||
2
regs/bits/ga_fill_g.txt
Normal file
2
regs/bits/ga_fill_g.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
COLOR_GREEN 31:0 0x0 FP20 format for green fill.
|
||||
2
regs/bits/ga_fill_r.txt
Normal file
2
regs/bits/ga_fill_r.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
COLOR_RED 31:0 0x0 FP20 format for red fill.
|
||||
2
regs/bits/ga_fog_offset.txt
Normal file
2
regs/bits/ga_fog_offset.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
VALUE 31:0 0x0 32b SPFP scale value.
|
||||
2
regs/bits/ga_fog_scale.txt
Normal file
2
regs/bits/ga_fog_scale.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
VALUE 31:0 0x0 32b SPFP scale value.
|
||||
28
regs/bits/ga_idle.txt
Normal file
28
regs/bits/ga_idle.txt
Normal file
@ -0,0 +1,28 @@
|
||||
Field Name Bits Default Description
|
||||
PIPE3_Z_IDLE 0 0x0 Idle status of physical pipe 3 Z unit
|
||||
PIPE2_Z_IDLE 1 0x0 Idle status of physical pipe 2 Z unit
|
||||
PIPE3_CB_IDLE 2 0x0 Idle status of physical pipe 3 CB unit
|
||||
PIPE2_CB_IDLE 3 0x0 Idle status of physical pipe 2 CB unit
|
||||
PIPE3_FG_IDLE 4 0x0 Idle status of physical pipe 3 FG unit
|
||||
PIPE2_FG_IDLE 5 0x0 Idle status of physical pipe 2 FG unit
|
||||
PIPE3_US_IDLE 6 0x0 Idle status of physical pipe 3 US unit
|
||||
PIPE2_US_IDLE 7 0x0 Idle status of physical pipe 2 US unit
|
||||
PIPE3_SC_IDLE 8 0x0 Idle status of physical pipe 3 SC unit
|
||||
PIPE2_SC_IDLE 9 0x0 Idle status of physical pipe 2 SC unit
|
||||
PIPE3_RS_IDLE 10 0x0 Idle status of physical pipe 3 RS unit
|
||||
PIPE2_RS_IDLE 11 0x0 Idle status of physical pipe 2 RS unit
|
||||
PIPE1_Z_IDLE 12 0x0 Idle status of physical pipe 1 Z unit
|
||||
PIPE0_Z_IDLE 13 0x0 Idle status of physical pipe 0 Z unit
|
||||
PIPE1_CB_IDLE 14 0x0 Idle status of physical pipe 1 CB unit
|
||||
PIPE0_CB_IDLE 15 0x0 Idle status of physical pipe 0 CB unit
|
||||
PIPE1_FG_IDLE 16 0x0 Idle status of physical pipe 1 FG unit
|
||||
PIPE0_FG_IDLE 17 0x0 Idle status of physical pipe 0 FG unit
|
||||
PIPE1_US_IDLE 18 0x0 Idle status of physical pipe 1 US unit
|
||||
PIPE0_US_IDLE 19 0x0 Idle status of physical pipe 0 US unit
|
||||
PIPE1_SC_IDLE 20 0x0 Idle status of physical pipe 1 SC unit
|
||||
PIPE0_SC_IDLE 21 0x0 Idle status of physical pipe 0 SC unit
|
||||
PIPE1_RS_IDLE 22 0x0 Idle status of physical pipe 1 RS unit
|
||||
PIPE0_RS_IDLE 23 0x0 Idle status of physical pipe 0 RS unit
|
||||
SU_IDLE 24 0x0 Idle status of SU unit
|
||||
GA_IDLE 25 0x0 Idle status of GA unit
|
||||
GA_UNIT2_IDLE 26 0x0 Idle status of GA unit2
|
||||
14
regs/bits/ga_line_cntl.txt
Normal file
14
regs/bits/ga_line_cntl.txt
Normal file
@ -0,0 +1,14 @@
|
||||
Field Name Bits Default Description
|
||||
WIDTH 15:0 0x0 1/2 width of line, in subpixels (1/12 or 1/16 only, even in
|
||||
8b subprecision); (16.0) fixed format.
|
||||
END_TYPE 17:16 0x0 Specifies how ends of lines should be drawn.
|
||||
POSSIBLE VALUES:
|
||||
00 - Horizontal
|
||||
01 - Vertical
|
||||
02 - Square (horizontal or vertical depending upon slope)
|
||||
03 - Computed (perpendicular to slope)
|
||||
SORT 18 0x0 R520+: When enabled, all lines are sorted so that V0 is
|
||||
vertex with smallest X, or if X equal, smallest Y.
|
||||
POSSIBLE VALUES:
|
||||
00 - No sorting (default)
|
||||
01 - Sort on minX than MinY
|
||||
3
regs/bits/ga_line_s0.txt
Normal file
3
regs/bits/ga_line_s0.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
S0 31:0 0x0 S texture coordinate value generated for vertex 0 of an
|
||||
antialiased line; 32-bit IEEE float format. Typical 0.0.
|
||||
3
regs/bits/ga_line_s1.txt
Normal file
3
regs/bits/ga_line_s1.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
S1 31:0 0x0 S texture coordinate value generated for vertex 1 of an
|
||||
antialiased line; 32-bit IEEE float format. Typical 1.0.
|
||||
8
regs/bits/ga_line_stipple_config.txt
Normal file
8
regs/bits/ga_line_stipple_config.txt
Normal file
@ -0,0 +1,8 @@
|
||||
Field Name Bits Default Description
|
||||
LINE_RESET 1:0 0x0 Specify type of reset to use for stipple accumulation.
|
||||
POSSIBLE VALUES:
|
||||
00 - No reseting
|
||||
01 - Reset per line
|
||||
02 - Reset per packet
|
||||
STIPPLE_SCALE 31:2 0x0 Specifies, in truncated (30b) floating point, scale to apply
|
||||
to generated texture coordinates.
|
||||
5
regs/bits/ga_offset.txt
Normal file
5
regs/bits/ga_offset.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
X_OFFSET 15:0 0x0 Specifies X offset in S15 format (subpixels -- 1/12 or
|
||||
1/16, even in 8b subprecision).
|
||||
Y_OFFSET 31:16 0x0 Specifies Y offset in S15 format (subpixels -- 1/12 or
|
||||
1/16, even in 8b subprecision).
|
||||
5
regs/bits/ga_point_minmax.txt
Normal file
5
regs/bits/ga_point_minmax.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
MIN_SIZE 15:0 0x0 Minimum point & sprite radius (in subsamples) size to
|
||||
allow.
|
||||
MAX_SIZE 31:16 0x0 Maximum point & sprite radius (in subsamples) size to
|
||||
allow.
|
||||
3
regs/bits/ga_point_s0.txt
Normal file
3
regs/bits/ga_point_s0.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
S0 31:0 0x0 S texture coordinate of vertex 0 for point; 32-bit IEEE
|
||||
float format.
|
||||
3
regs/bits/ga_point_s1.txt
Normal file
3
regs/bits/ga_point_s1.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
S1 31:0 0x0 S texture coordinate of vertex 1 for point; 32-bit IEEE
|
||||
float format.
|
||||
5
regs/bits/ga_point_size.txt
Normal file
5
regs/bits/ga_point_size.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
HEIGHT 15:0 0x0 1/2 Height of point; fixed (16.0), subpixel format (1/12
|
||||
or 1/16, even if in 8b precision).
|
||||
WIDTH 31:16 0x0 1/2 Width of point; fixed (16.0), subpixel format (1/12 or
|
||||
1/16, even if in 8b precision)
|
||||
3
regs/bits/ga_point_t0.txt
Normal file
3
regs/bits/ga_point_t0.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
T0 31:0 0x0 T texture coordinate of vertex 0 for point; 32-bit IEEE
|
||||
float format.
|
||||
3
regs/bits/ga_point_t1.txt
Normal file
3
regs/bits/ga_point_t1.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
T1 31:0 0x0 T texture coordinate of vertex 1 for point; 32-bit IEEE
|
||||
float format.
|
||||
18
regs/bits/ga_poly_mode.txt
Normal file
18
regs/bits/ga_poly_mode.txt
Normal file
@ -0,0 +1,18 @@
|
||||
Field Name Bits Default Description
|
||||
POLY_MODE 1:0 0x0 Polygon mode enable.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable poly mode (render triangles).
|
||||
01 - Dual mode (send 2 sets of 3 polys with specified poly type).
|
||||
02 - Reserved
|
||||
FRONT_PTYPE 6:4 0x0 Specifies how to render front-facing polygons.
|
||||
POSSIBLE VALUES:
|
||||
00 - Draw points.
|
||||
01 - Draw lines.
|
||||
02 - Draw triangles.
|
||||
03 - Reserved 3 - 7.
|
||||
BACK_PTYPE 9:7 0x0 Specifies how to render back-facing polygons.
|
||||
POSSIBLE VALUES:
|
||||
00 - Draw points.
|
||||
01 - Draw lines.
|
||||
02 - Draw triangles.
|
||||
03 - Reserved 3 - 7.
|
||||
20
regs/bits/ga_round_mode.txt
Normal file
20
regs/bits/ga_round_mode.txt
Normal file
@ -0,0 +1,20 @@
|
||||
Field Name Bits Default Description
|
||||
GEOMETRY_ROUND 1:0 0x0 Trunc (0) or round to nearest (1) for geometry (XY).
|
||||
POSSIBLE VALUES:
|
||||
00 - Round to trunc
|
||||
01 - Round to nearest
|
||||
COLOR_ROUND 3:2 0x0 When set, FP32 to FP20 using round to nearest;
|
||||
otherwise trunc
|
||||
POSSIBLE VALUES:
|
||||
00 - Round to trunc
|
||||
01 - Round to nearest
|
||||
RGB_CLAMP 4 0x0 Specifies SPFP color clamp range of [0,1] or FP20 for RGB.
|
||||
POSSIBLE VALUES:
|
||||
00 - Clamp to [0,1.0] for RGB
|
||||
01 - RGB is FP20
|
||||
ALPHA_CLAMP 5 0x0 Specifies SPFP alpha clamp range of [0,1] or FP20.
|
||||
POSSIBLE VALUES:
|
||||
00 - Clamp to [0,1.0] for Alpha
|
||||
01 - Alpha is FP20
|
||||
GEOMETRY_MASK 9:6 0x0 4b negative polarity mask for subpixel precision.
|
||||
Inverted version gets ANDed with subpixel X, Y masks.
|
||||
3
regs/bits/ga_solid_ba.txt
Normal file
3
regs/bits/ga_solid_ba.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
COLOR_ALPHA 15:0 0x0 Component alpha value. (S3.12)
|
||||
COLOR_BLUE 31:16 0x0 Component blue value. (S3.12)
|
||||
3
regs/bits/ga_solid_rg.txt
Normal file
3
regs/bits/ga_solid_rg.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
COLOR_GREEN 15:0 0x0 Component green value (S3.12).
|
||||
COLOR_RED 31:16 0x0 Component red value (S3.12).
|
||||
3
regs/bits/ga_triangle_stipple.txt
Normal file
3
regs/bits/ga_triangle_stipple.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
X_SHIFT 3:0 0x0 Amount to shift x position before conversion to SPFP.
|
||||
Y_SHIFT 19:16 0x0 Amount to shift y position before conversion to SPFP.
|
||||
2
regs/bits/ga_us_vector_data.txt
Normal file
2
regs/bits/ga_us_vector_data.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
DATA 31:0 0x0 32 bit dword
|
||||
20
regs/bits/ga_us_vector_index.txt
Normal file
20
regs/bits/ga_us_vector_index.txt
Normal file
@ -0,0 +1,20 @@
|
||||
Field Name Bits Default Description
|
||||
INDEX 8:0 0x0 Instruction (TYPE == GA_US_VECTOR_INST) or
|
||||
constant (TYPE == GA_US_VECTOR_CONST)
|
||||
number at which to start loading. The GA will then
|
||||
expect n*6 (instructions) or n*4 (constants) writes to
|
||||
GA_US_VECTOR_DATA. The GA will self-increment
|
||||
until this register is written again. For instructions, the
|
||||
GA expects the dwords in the following order:
|
||||
US_CMN_INST, US_ALU_RGB_ADDR,
|
||||
US_ALU_ALPHA_ADDR, US_ALU_ALPHA,
|
||||
US_RGB_INST, US_ALPHA_INST, US_RGBA_INST.
|
||||
For constants, the GA expects the dwords in RGBA
|
||||
order.
|
||||
TYPE 16 0x0 Specifies if the GA should load instructions or constants.
|
||||
POSSIBLE VALUES:
|
||||
00 - Load instructions - INDEX is an instruction index
|
||||
01 - Load constants - INDEX is a constant index
|
||||
CLAMP 17 0x0 POSSIBLE VALUES:
|
||||
00 - No clamping of data - Default
|
||||
01 - Clamp to [-1.0,1.0] constant data
|
||||
12
regs/bits/gb_aa_config.txt
Normal file
12
regs/bits/gb_aa_config.txt
Normal file
@ -0,0 +1,12 @@
|
||||
Field Name Bits Default Description
|
||||
AA_ENABLE 0 0x0 Enables antialiasing.
|
||||
POSSIBLE VALUES:
|
||||
00 - Antialiasing disabled(def)
|
||||
01 - Antialiasing enabled
|
||||
NUM_AA_SUBSAMPLES 2:1 0x0 Specifies the number of subsamples to use while
|
||||
antialiasing.
|
||||
POSSIBLE VALUES:
|
||||
00 - 2 subsamples
|
||||
01 - 3 subsamples
|
||||
02 - 4 subsamples
|
||||
03 - 6 subsamples
|
||||
68
regs/bits/gb_enable.txt
Normal file
68
regs/bits/gb_enable.txt
Normal file
@ -0,0 +1,68 @@
|
||||
Field Name Bits Default Description
|
||||
POINT_STUFF_ENABLE 0 0x0 Specifies if points will have stuffed texture coordinates.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable point texture stuffing.
|
||||
01 - Enable point texture stuffing.
|
||||
LINE_STUFF_ENABLE 1 0x0 Specifies if lines will have stuffed texture coordinates.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable line texture stuffing.
|
||||
01 - Enable line texture stuffing.
|
||||
TRIANGLE_STUFF_ENABLE 2 0x0 Specifies if triangles will have stuffed texture
|
||||
coordinates.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable triangle texture stuffing.
|
||||
01 - Enable triangle texture stuffing.
|
||||
STENCIL_AUTO 5:4 0x0 Specifies if the auto dec/inc stencil mode should be
|
||||
enabled, and how.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable stencil auto inc/dec (def).
|
||||
01 - Enable stencil auto inc/dec based on triangle cw/ccw, force into dzy low bit.
|
||||
02 - Force 0 into dzy low bit.
|
||||
TEX0_SOURCE 17:16 0x0 Specifies the sources of the texture coordinates for each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX1_SOURCE 19:18 0x0 Specifies the sources of the texture coordinates for each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX2_SOURCE 21:20 0x0 Specifies the sources of the texture coordinates for each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX3_SOURCE 23:22 0x0 Specifies the sources of the texture coordinates for each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX4_SOURCE 25:24 0x0 Specifies the sources of the texture coordinates for each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX5_SOURCE 27:26 0x0 Specifies the sources of the texture coordinates for each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX6_SOURCE 29:28 0x0 Specifies the sources of the texture coordinates for each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX7_SOURCE 31:30 0x0 Specifies the sources of the texture coordinates for each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
58
regs/bits/gb_fifo_size.txt
Normal file
58
regs/bits/gb_fifo_size.txt
Normal file
@ -0,0 +1,58 @@
|
||||
Field Name Bits Default Description
|
||||
SC_IFIFO_SIZE 1:0 0x0 Size of scan converter input FIFO (XYZ)
|
||||
POSSIBLE VALUES:
|
||||
00 - 32 words
|
||||
01 - 64 words
|
||||
02 - 128 words
|
||||
03 - 256 words
|
||||
SC_TZFIFO_SIZE 3:2 0x0 Size of scan converter top-of-pipe Z FIFO
|
||||
POSSIBLE VALUES:
|
||||
00 - 16 words
|
||||
01 - 32 words
|
||||
02 - 64 words
|
||||
03 - 128 words
|
||||
SC_BFIFO_SIZE 5:4 0x0 Size of scan converter input FIFO (B)
|
||||
POSSIBLE VALUES:
|
||||
00 - 32 words
|
||||
01 - 64 words
|
||||
02 - 128 words
|
||||
03 - 256 words
|
||||
RS_TFIFO_SIZE 7:6 0x0 Size of ras input FIFO (Texture)
|
||||
POSSIBLE VALUES:
|
||||
00 - 64 words
|
||||
01 - 128 words
|
||||
02 - 256 words
|
||||
03 - 512 words
|
||||
RS_CFIFO_SIZE 9:8 0x0 Size of ras input FIFO (Color)
|
||||
POSSIBLE VALUES:
|
||||
00 - 64 words
|
||||
01 - 128 words
|
||||
02 - 256 words
|
||||
03 - 512 words
|
||||
US_RAM_SIZE 11:10 0x0 Size of us RAM
|
||||
POSSIBLE VALUES:
|
||||
00 - 64 words
|
||||
01 - 128 words
|
||||
02 - 256 words
|
||||
03 - 512 words
|
||||
US_OFIFO_SIZE 13:12 0x0 Size of us output FIFO (RGBA)
|
||||
POSSIBLE VALUES:
|
||||
00 - 16 words
|
||||
01 - 32 words
|
||||
02 - 64 words
|
||||
03 - 128 words
|
||||
US_WFIFO_SIZE 15:14 0x0 Size of us output FIFO (W)
|
||||
POSSIBLE VALUES:
|
||||
00 - 16 words
|
||||
01 - 32 words
|
||||
02 - 64 words
|
||||
03 - 128 words
|
||||
RS_HIGHWATER_COL 18:16 0x0 High water mark for RS colors` fifo -- NOT USED
|
||||
RS_HIGHWATER_TEX 21:19 0x0 High water mark for RS textures` fifo -- NOT USED
|
||||
US_OFIFO_HIGHWATER 23:22 0x0 High water mark for US output fifo
|
||||
POSSIBLE VALUES:
|
||||
00 - 0 words
|
||||
01 - 4 words
|
||||
02 - 8 words
|
||||
03 - 12 words
|
||||
US_CUBE_FIFO_HIGHWATER 28:24 0x0 High water mark for US cube map fifo
|
||||
5
regs/bits/gb_fifo_size1.txt
Normal file
5
regs/bits/gb_fifo_size1.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
SC_HIGHWATER_IFIFO 5:0 0x0 High water mark for SC input fifo
|
||||
SC_HIGHWATER_BFIFO 11:6 0x0 High water mark for SC input fifo (B)
|
||||
RS_HIGHWATER_COL 17:12 0x0 High water mark for RS colors` fifo
|
||||
RS_HIGHWATER_TEX 23:18 0x0 High water mark for RS textures` fifo
|
||||
19
regs/bits/gb_mspos0.txt
Normal file
19
regs/bits/gb_mspos0.txt
Normal file
@ -0,0 +1,19 @@
|
||||
Field Name Bits Default Description
|
||||
MS_X0 3:0 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 0
|
||||
MS_Y0 7:4 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 0
|
||||
MS_X1 11:8 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 1
|
||||
MS_Y1 15:12 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 1
|
||||
MS_X2 19:16 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 2
|
||||
MS_Y2 23:20 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 2
|
||||
MSBD0_Y 27:24 0x0 Specifies the minimum x and y distance (in subpixels)
|
||||
between the pixel edge and the multisamples. These
|
||||
values are used in the first (coarse) scan converter
|
||||
MSBD0_X 31:28 0x0 Specifies the minimum x and y distance (in subpixels)
|
||||
between the pixel edge and the multisamples. These
|
||||
values are used in the first (coarse) scan converter
|
||||
16
regs/bits/gb_mspos1.txt
Normal file
16
regs/bits/gb_mspos1.txt
Normal file
@ -0,0 +1,16 @@
|
||||
Field Name Bits Default Description
|
||||
MS_X3 3:0 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 3
|
||||
MS_Y3 7:4 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 3
|
||||
MS_X4 11:8 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 4
|
||||
MS_Y4 15:12 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 4
|
||||
MS_X5 19:16 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 5
|
||||
MS_Y5 23:20 0x0 Specifies the x and y position (in subpixels) of
|
||||
multisample 5
|
||||
MSBD1 27:24 0x0 Specifies the minimum distance (in subpixels) between
|
||||
the pixel edge and the multisamples. This value is used
|
||||
in the second (quad) scan converter
|
||||
19
regs/bits/gb_pipe_select.txt
Normal file
19
regs/bits/gb_pipe_select.txt
Normal file
@ -0,0 +1,19 @@
|
||||
Field Name Bits Default Description
|
||||
PIPE0_ID 1:0 0x0 Maps physical pipe 0 to logical pipe ID (def 0).
|
||||
PIPE1_ID 3:2 0x1 Maps physical pipe 1 to logical pipe ID (def 1).
|
||||
PIPE2_ID 5:4 0x2 Maps physical pipe 2 to logical pipe ID (def 2).
|
||||
PIPE3_ID 7:6 0x3 Maps physical pipe 3 to logical pipe ID (def 3).
|
||||
PIPE_MASK 11:8 0x0 4b mask, indicates which physical pipes are enabled (def
|
||||
none=0x0) -- B3=P3, B2=P2, B1=P1, B0=P0. -- 1:
|
||||
enabled, 0: disabled
|
||||
MAX_PIPE 13:12 0x3 2b, indicates, by the fuses, the max number of allowed
|
||||
pipes. 0 = 1 pipe ... 3 = 4 pipes -- Read Only
|
||||
BAD_PIPES 17:14 0xF 4b, indicates, by the fuses, the bad pipes: B3=P3, B2=P2,
|
||||
B1=P1, B0=P0 -- 1: bad, 0: good -- Read Only
|
||||
CONFIG_PIPES 18 0x0 If this bit is set when writing this register, the logical
|
||||
pipe ID values are assigned automatically based on the
|
||||
values that are read back in the MAX_PIPE and
|
||||
BAD_PIPES fields. This field is always read back as 0.
|
||||
POSSIBLE VALUES:
|
||||
00 - Do nothing
|
||||
01 - Force self-configuration
|
||||
25
regs/bits/gb_select.txt
Normal file
25
regs/bits/gb_select.txt
Normal file
@ -0,0 +1,25 @@
|
||||
Field Name Bits Default Description
|
||||
FOG_SELECT 2:0 0x0 Specifies source for outgoing (GA to SU) fog value.
|
||||
POSSIBLE VALUES:
|
||||
00 - Select C0A
|
||||
01 - Select C1A
|
||||
02 - Select C2A
|
||||
03 - Select C3A
|
||||
04 - Select 1/(1/W)
|
||||
05 - Select Z
|
||||
DEPTH_SELECT 3 0x0 Specifies source for outgoing (GA/SU & SU/RAS) depth
|
||||
value.
|
||||
POSSIBLE VALUES:
|
||||
00 - Select Z
|
||||
01 - Select 1/(1/W)
|
||||
W_SELECT 4 0x0 Specifies source for outgoing (1/W) value, used to
|
||||
disable perspective correct colors/textures.
|
||||
POSSIBLE VALUES:
|
||||
00 - Select (1/W)
|
||||
01 - Select 1.0
|
||||
FOG_STUFF_ENABLE 5 0x0 Controls enabling of fog stuffing into texture coordinate.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable fog texture stuffing
|
||||
01 - Enable fog texture stuffing
|
||||
FOG_STUFF_TEX 9:6 0x0 Controls which texture gets fog value
|
||||
FOG_STUFF_COMP 11:10 0x0 Controls which component of texture gets fog value
|
||||
77
regs/bits/gb_tile_config.txt
Normal file
77
regs/bits/gb_tile_config.txt
Normal file
@ -0,0 +1,77 @@
|
||||
Field Name Bits Default Description
|
||||
ENABLE 0 0x1 Enables tiling, otherwise all tiles receive all polygons.
|
||||
POSSIBLE VALUES:
|
||||
00 - Tiling disabled.
|
||||
01 - Tiling enabled (def).
|
||||
PIPE_COUNT 3:1 0x0 Specifies the number of active pipes and contexts (up to
|
||||
4 pipes, 1 ctx). When this field is written, it is
|
||||
automatically reduced by hardware so as not to use more
|
||||
pipes than the number indicated in
|
||||
GB_PIPE_SELECT.MAX_PIPES or the number of
|
||||
pipes left unmasked GB_PIPE_SELECT.BAD_PIPES.
|
||||
The potentially altered value is read back, rather than the
|
||||
original value written by software.
|
||||
POSSIBLE VALUES:
|
||||
00 - RV350 (1 pipe, 1 ctx)
|
||||
03 - R300 (2 pipes, 1 ctx)
|
||||
06 - R420-3P (3 pipes, 1 ctx)
|
||||
07 - R420 (4 pipes, 1 ctx)
|
||||
TILE_SIZE 5:4 0x1 Specifies width & height (square), in pixels (only 16, 32
|
||||
available).
|
||||
POSSIBLE VALUES:
|
||||
00 - 8 pixels.
|
||||
01 - 16 pixels.
|
||||
02 - 32 pixels.
|
||||
SUPER_SIZE 8:6 0x0 Specifies number of tiles and config in super chip
|
||||
configuration.
|
||||
POSSIBLE VALUES:
|
||||
00 - 1x1 tile (one 1x1).
|
||||
01 - 2 tiles (two 1x1 : ST-A,B).
|
||||
02 - 4 tiles (one 2x2).
|
||||
03 - 8 tiles (two 2x2 : ST-A,B).
|
||||
04 - 16 tiles (one 4x4).
|
||||
05 - 32 tiles (two 4x4 : ST-A,B).
|
||||
06 - 64 tiles (one 8x8).
|
||||
07 - 128 tiles (two 8x8 : ST-A,B).
|
||||
SUPER_X 11:9 0x0 X Location of chip within super tile.
|
||||
SUPER_Y 14:12 0x0 Y Location of chip within super tile.
|
||||
SUPER_TILE 15 0x0 Tile location of chip in a multi super tile config (Super
|
||||
size of 2,8,32 or 128).
|
||||
POSSIBLE VALUES:
|
||||
00 - ST-A tile.
|
||||
01 - ST-B tile.
|
||||
SUBPIXEL 16 0x0 Specifies the precision of subpixels wrt pixels (12 or 16).
|
||||
POSSIBLE VALUES:
|
||||
00 - Select 1/12 subpixel precision.
|
||||
01 - Select 1/16 subpixel precision.
|
||||
QUADS_PER_RAS 18:17 0x0 Specifies the number of quads to be sent to each
|
||||
rasterizer in turn when in RV300B or R300B mode
|
||||
POSSIBLE VALUES:
|
||||
00 - 4 Quads
|
||||
01 - 8 Quads
|
||||
02 - 16 Quads
|
||||
03 - 32 Quads
|
||||
BB_SCAN 19 0x0 Specifies whether to use an intercept or bounding box
|
||||
based calculation for the first (coarse) scan converter
|
||||
POSSIBLE VALUES:
|
||||
00 - Use intercept based scan converter
|
||||
01 - Use bounding box based scan converter
|
||||
ALT_SCAN_EN 20 0x0 Specifies whether to use an altenate scan pattern for the
|
||||
coarse scan converter
|
||||
POSSIBLE VALUES:
|
||||
00 - Use normal left-right scan
|
||||
01 - Use alternate left-right-left scan
|
||||
ALT_OFFSET 21 0x0 Not used -- should be 0
|
||||
POSSIBLE VALUES:
|
||||
00 - Not used
|
||||
01 - Not used
|
||||
SUBPRECISION 22 0x0 Set to 0
|
||||
ALT_TILING 23 0x0 Support for 3x2 tiling in 3P mode
|
||||
POSSIBLE VALUES:
|
||||
00 - Use default tiling in all tiling modes
|
||||
01 - Use alternative 3x2 tiling in 3P mode
|
||||
Z_EXTENDED 24 0x0 Support for extended setup Z range from [0,1] to [-2,2]
|
||||
with per pixel clamping
|
||||
POSSIBLE VALUES:
|
||||
00 - Use (24.1) Z format, with vertex clamp to [1.0,0.0]
|
||||
01 - Use (S25.1) format, with vertex clamp to [2.0,-2.0] and per pixel [1.0,0.0]
|
||||
5
regs/bits/gb_z_peq_config.txt
Normal file
5
regs/bits/gb_z_peq_config.txt
Normal file
@ -0,0 +1,5 @@
|
||||
Field Name Bits Default Description
|
||||
Z_PEQ_SIZE 0 0x0 Specifies the z plane equation size.
|
||||
POSSIBLE VALUES:
|
||||
00 - 4x4 z plane equations (point-sampled or aa)
|
||||
01 - 8x8 z plane equations (point-sampled only)
|
||||
6
regs/bits/ps3_enable.txt
Normal file
6
regs/bits/ps3_enable.txt
Normal file
@ -0,0 +1,6 @@
|
||||
Field Name Bits Default Description
|
||||
PS3_MODE 0 0x0 When reset (default), follows R300/PS2 mode; when set,
|
||||
allows for new ps3 mode.
|
||||
POSSIBLE VALUES:
|
||||
00 - Default PS2 mode
|
||||
01 - New PS3 mode
|
||||
61
regs/bits/ps3_tex_source.txt
Normal file
61
regs/bits/ps3_tex_source.txt
Normal file
@ -0,0 +1,61 @@
|
||||
Field Name Bits Default Description
|
||||
TEX0_SOURCE 1:0 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX1_SOURCE 3:2 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX2_SOURCE 5:4 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX3_SOURCE 7:6 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX4_SOURCE 9:8 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX5_SOURCE 11:10 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX6_SOURCE 13:12 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX7_SOURCE 15:14 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX8_SOURCE 17:16 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
TEX9_SOURCE 19:18 0x0 Specifies VAP source, or GA (ST) or GA (STR) stuffing
|
||||
for each texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Replicate VAP source texture coordinates (S,T,[R,Q]).
|
||||
01 - Stuff with source texture coordinates (S,T).
|
||||
02 - Stuff with source texture coordinates (S,T,R).
|
||||
87
regs/bits/ps3_vtx_fmt.txt
Normal file
87
regs/bits/ps3_vtx_fmt.txt
Normal file
@ -0,0 +1,87 @@
|
||||
Field Name Bits Default Description
|
||||
TEX_0_COMP_CNT 2:0 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_1_COMP_CNT 5:3 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_2_COMP_CNT 8:6 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_3_COMP_CNT 11:9 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_4_COMP_CNT 14:12 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_5_COMP_CNT 17:15 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_6_COMP_CNT 20:18 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_7_COMP_CNT 23:21 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_8_COMP_CNT 26:24 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_9_COMP_CNT 29:27 0x0 How many active components (0,1,2,3,4) are in each
|
||||
texture.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 1 component (VAP/GA), 2 component (GA/SU)
|
||||
02 - 2 component (VAP/GA), 2 component (GA/SU)
|
||||
03 - 3 component (VAP/GA), 3 component (GA/SU)
|
||||
04 - 4 component (VAP/GA), 4 component (GA/SU)
|
||||
TEX_10_COMP_CNT 31:30 0x0 How many active components (0,2,3,4) are in texture 10.
|
||||
POSSIBLE VALUES:
|
||||
00 - Not active
|
||||
01 - 2 component (GA/SU)
|
||||
02 - 3 component (GA/SU)
|
||||
03 - 4 component (GA/SU)
|
||||
18
regs/bits/rb3d_aaresolve_ctl.txt
Normal file
18
regs/bits/rb3d_aaresolve_ctl.txt
Normal file
@ -0,0 +1,18 @@
|
||||
Field Name Bits Default Description
|
||||
AARESOLVE_MODE 0 0x0 Specifies if the color buffer is in resolve mode. The
|
||||
cache must be empty before changing this register.
|
||||
POSSIBLE VALUES:
|
||||
00 - Normal operation.
|
||||
01 - Resolve operation.
|
||||
AARESOLVE_GAMMA 1 none Specifies the gamma and degamma to be applied to the
|
||||
samples before and after filtering, respectively.
|
||||
POSSIBLE VALUES:
|
||||
00 - 1.0
|
||||
01 - 2.2
|
||||
AARESOLVE_ALPHA 2 0x0 Controls whether alpha is averaged in the resolve. 0 =>
|
||||
the resolved alpha value is selected from the sample 0
|
||||
value. 1=> the resolved alpha value is a filtered (average)
|
||||
result of of the samples.
|
||||
POSSIBLE VALUES:
|
||||
00 - Resolved alpha value is taken from sample 0.
|
||||
01 - Resolved alpha value is the average of the samples. The average is not gamma corrected.
|
||||
2
regs/bits/rb3d_aaresolve_offset.txt
Normal file
2
regs/bits/rb3d_aaresolve_offset.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
AARESOLVE_OFFSET 31:5 none 256-bit aligned 3D resolve destination offset.
|
||||
2
regs/bits/rb3d_aaresolve_pitch.txt
Normal file
2
regs/bits/rb3d_aaresolve_pitch.txt
Normal file
@ -0,0 +1,2 @@
|
||||
Field Name Bits Default Description
|
||||
AARESOLVE_PITCH 13:1 none 3D destination pitch in multiples of 2-pixels.
|
||||
144
regs/bits/rb3d_ablendcntl.txt
Normal file
144
regs/bits/rb3d_ablendcntl.txt
Normal file
@ -0,0 +1,144 @@
|
||||
Field Name Bits Default Description
|
||||
COMB_FCN 14:12 none Combine Function , Allows modification of how the
|
||||
SRCBLEND and DESTBLEND are combined.
|
||||
POSSIBLE VALUES:
|
||||
00 - Add and Clamp
|
||||
01 - Add but no Clamp
|
||||
02 - Subtract Dst from Src, and Clamp
|
||||
03 - Subtract Dst from Src, and don`t Clamp
|
||||
04 - Minimum of Src, Dst (the src and dst blend functions are forced to D3D_ONE)
|
||||
05 - Maximum of Src, Dst (the src and dst blend functions are forced to D3D_ONE)
|
||||
06 - Subtract Src from Dst, and Clamp
|
||||
07 - Subtract Src from Dst, and don`t Clamp
|
||||
SRCBLEND 21:16 none Source Blend Function , Alpha blending function (SRC).
|
||||
POSSIBLE VALUES:
|
||||
00 - RESERVED
|
||||
01 - D3D_ZERO
|
||||
02 - D3D_ONE
|
||||
03 - D3D_SRCCOLOR
|
||||
04 - D3D_INVSRCCOLOR
|
||||
05 - D3D_SRCALPHA
|
||||
06 - D3D_INVSRCALPHA
|
||||
07 - D3D_DESTALPHA
|
||||
08 - D3D_INVDESTALPHA
|
||||
09 - D3D_DESTCOLOR
|
||||
10 - D3D_INVDESTCOLOR
|
||||
11 - D3D_SRCALPHASAT
|
||||
12 - D3D_BOTHSRCALPHA
|
||||
13 - D3D_BOTHINVSRCALPHA
|
||||
14 - RESERVED
|
||||
15 - RESERVED
|
||||
16 - RESERVED
|
||||
17 - RESERVED
|
||||
18 - RESERVED
|
||||
19 - RESERVED
|
||||
20 - RESERVED
|
||||
21 - RESERVED
|
||||
22 - RESERVED
|
||||
23 - RESERVED
|
||||
24 - RESERVED
|
||||
25 - RESERVED
|
||||
26 - RESERVED
|
||||
27 - RESERVED
|
||||
28 - RESERVED
|
||||
29 - RESERVED
|
||||
30 - RESERVED
|
||||
31 - RESERVED
|
||||
32 - GL_ZERO
|
||||
33 - GL_ONE
|
||||
34 - GL_SRC_COLOR
|
||||
35 - GL_ONE_MINUS_SRC_COLOR
|
||||
36 - GL_DST_COLOR
|
||||
37 - GL_ONE_MINUS_DST_COLOR
|
||||
38 - GL_SRC_ALPHA
|
||||
39 - GL_ONE_MINUS_SRC_ALPHA
|
||||
40 - GL_DST_ALPHA
|
||||
41 - GL_ONE_MINUS_DST_ALPHA
|
||||
42 - GL_SRC_ALPHA_SATURATE
|
||||
43 - GL_CONSTANT_COLOR
|
||||
44 - GL_ONE_MINUS_CONSTANT_COLOR
|
||||
45 - GL_CONSTANT_ALPHA
|
||||
46 - GL_ONE_MINUS_CONSTANT_ALPHA
|
||||
47 - RESERVED
|
||||
48 - RESERVED
|
||||
49 - RESERVED
|
||||
50 - RESERVED
|
||||
51 - RESERVED
|
||||
52 - RESERVED
|
||||
53 - RESERVED
|
||||
54 - RESERVED
|
||||
55 - RESERVED
|
||||
56 - RESERVED
|
||||
57 - RESERVED
|
||||
58 - RESERVED
|
||||
59 - RESERVED
|
||||
60 - RESERVED
|
||||
61 - RESERVED
|
||||
62 - RESERVED
|
||||
63 - RESERVED
|
||||
DESTBLEND 29:24 none Destination Blend Function , Alpha blending function (DST).
|
||||
POSSIBLE VALUES:
|
||||
00 - RESERVED
|
||||
01 - D3D_ZERO
|
||||
02 - D3D_ONE
|
||||
03 - D3D_SRCCOLOR
|
||||
04 - D3D_INVSRCCOLOR
|
||||
05 - D3D_SRCALPHA
|
||||
06 - D3D_INVSRCALPHA
|
||||
07 - D3D_DESTALPHA
|
||||
08 - D3D_INVDESTALPHA
|
||||
09 - D3D_DESTCOLOR
|
||||
10 - D3D_INVDESTCOLOR
|
||||
11 - RESERVED
|
||||
12 - RESERVED
|
||||
13 - RESERVED
|
||||
14 - RESERVED
|
||||
15 - RESERVED
|
||||
16 - RESERVED
|
||||
17 - RESERVED
|
||||
18 - RESERVED
|
||||
19 - RESERVED
|
||||
20 - RESERVED
|
||||
21 - RESERVED
|
||||
22 - RESERVED
|
||||
23 - RESERVED
|
||||
24 - RESERVED
|
||||
25 - RESERVED
|
||||
26 - RESERVED
|
||||
27 - RESERVED
|
||||
28 - RESERVED
|
||||
29 - RESERVED
|
||||
30 - RESERVED
|
||||
31 - RESERVED
|
||||
32 - GL_ZERO
|
||||
33 - GL_ONE
|
||||
34 - GL_SRC_COLOR
|
||||
35 - GL_ONE_MINUS_SRC_COLOR
|
||||
36 - GL_DST_COLOR
|
||||
37 - GL_ONE_MINUS_DST_COLOR
|
||||
38 - GL_SRC_ALPHA
|
||||
39 - GL_ONE_MINUS_SRC_ALPHA
|
||||
40 - GL_DST_ALPHA
|
||||
41 - GL_ONE_MINUS_DST_ALPHA
|
||||
42 - RESERVED
|
||||
43 - GL_CONSTANT_COLOR
|
||||
44 - GL_ONE_MINUS_CONSTANT_COLOR
|
||||
45 - GL_CONSTANT_ALPHA
|
||||
46 - GL_ONE_MINUS_CONSTANT_ALPHA
|
||||
47 - RESERVED
|
||||
48 - RESERVED
|
||||
49 - RESERVED
|
||||
50 - RESERVED
|
||||
51 - RESERVED
|
||||
52 - RESERVED
|
||||
53 - RESERVED
|
||||
54 - RESERVED
|
||||
55 - RESERVED
|
||||
56 - RESERVED
|
||||
57 - RESERVED
|
||||
58 - RESERVED
|
||||
59 - RESERVED
|
||||
60 - RESERVED
|
||||
61 - RESERVED
|
||||
62 - RESERVED
|
||||
63 - RESERVED
|
||||
179
regs/bits/rb3d_blendcntl.txt
Normal file
179
regs/bits/rb3d_blendcntl.txt
Normal file
@ -0,0 +1,179 @@
|
||||
Field Name Bits Default Description
|
||||
ALPHA_BLEND_ENABLE 0 0x0 Allow alpha blending with the destination.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable
|
||||
01 - Enable
|
||||
SEPARATE_ALPHA_ENABLE 1 0x0 Enables use of RB3D_ABLENDCNTL
|
||||
POSSIBLE VALUES:
|
||||
00 - Disabled (Use RB3D_BLENDCNTL)
|
||||
01 - Enabled (Use RB3D_ABLENDCNTL)
|
||||
READ_ENABLE 2 0x1 When blending is enabled, this enables memory reads.
|
||||
Memory reads will still occur when this is disabled if
|
||||
they are for reasons not related to blending.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable reads
|
||||
01 - Enable reads
|
||||
DISCARD_SRC_PIXELS 5:3 0x0 Discard pixels when blending is enabled based on the src
|
||||
color.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable
|
||||
01 - Discard pixels if src alpha <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
|
||||
02 - Discard pixels if src color <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
|
||||
03 - Discard pixels if src argb <= RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
|
||||
04 - Discard pixels if src alpha >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
|
||||
05 - Discard pixels if src color >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
|
||||
06 - Discard pixels if src argb >= RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
|
||||
07 - (reserved)
|
||||
COMB_FCN 14:12 none Combine Function , Allows modification of how the
|
||||
SRCBLEND and DESTBLEND are combined.
|
||||
POSSIBLE VALUES:
|
||||
00 - Add and Clamp
|
||||
01 - Add but no Clamp
|
||||
02 - Subtract Dst from Src, and Clamp
|
||||
03 - Subtract Dst from Src, and don`t Clamp
|
||||
04 - Minimum of Src, Dst (the src and dst blend functions are forced to D3D_ONE)
|
||||
05 - Maximum of Src, Dst (the src and dst blend functions are forced to D3D_ONE)
|
||||
06 - Subtract Src from Dst, and Clamp
|
||||
07 - Subtract Src from Dst, and don`t Clamp
|
||||
SRCBLEND 21:16 none Source Blend Function , Alpha blending function (SRC).
|
||||
POSSIBLE VALUES:
|
||||
00 - RESERVED
|
||||
01 - D3D_ZERO
|
||||
02 - D3D_ONE
|
||||
03 - D3D_SRCCOLOR
|
||||
04 - D3D_INVSRCCOLOR
|
||||
05 - D3D_SRCALPHA
|
||||
06 - D3D_INVSRCALPHA
|
||||
07 - D3D_DESTALPHA
|
||||
08 - D3D_INVDESTALPHA
|
||||
09 - D3D_DESTCOLOR
|
||||
10 - D3D_INVDESTCOLOR
|
||||
11 - D3D_SRCALPHASAT
|
||||
12 - D3D_BOTHSRCALPHA
|
||||
13 - D3D_BOTHINVSRCALPHA
|
||||
14 - RESERVED
|
||||
15 - RESERVED
|
||||
16 - RESERVED
|
||||
17 - RESERVED
|
||||
18 - RESERVED
|
||||
19 - RESERVED
|
||||
20 - RESERVED
|
||||
21 - RESERVED
|
||||
22 - RESERVED
|
||||
23 - RESERVED
|
||||
24 - RESERVED
|
||||
25 - RESERVED
|
||||
26 - RESERVED
|
||||
27 - RESERVED
|
||||
28 - RESERVED
|
||||
29 - RESERVED
|
||||
30 - RESERVED
|
||||
31 - RESERVED
|
||||
32 - GL_ZERO
|
||||
33 - GL_ONE
|
||||
34 - GL_SRC_COLOR
|
||||
35 - GL_ONE_MINUS_SRC_COLOR
|
||||
36 - GL_DST_COLOR
|
||||
37 - GL_ONE_MINUS_DST_COLOR
|
||||
38 - GL_SRC_ALPHA
|
||||
39 - GL_ONE_MINUS_SRC_ALPHA
|
||||
40 - GL_DST_ALPHA
|
||||
41 - GL_ONE_MINUS_DST_ALPHA
|
||||
42 - GL_SRC_ALPHA_SATURATE
|
||||
43 - GL_CONSTANT_COLOR
|
||||
44 - GL_ONE_MINUS_CONSTANT_COLOR
|
||||
45 - GL_CONSTANT_ALPHA
|
||||
46 - GL_ONE_MINUS_CONSTANT_ALPHA
|
||||
47 - RESERVED
|
||||
48 - RESERVED
|
||||
49 - RESERVED
|
||||
50 - RESERVED
|
||||
51 - RESERVED
|
||||
52 - RESERVED
|
||||
53 - RESERVED
|
||||
54 - RESERVED
|
||||
55 - RESERVED
|
||||
56 - RESERVED
|
||||
57 - RESERVED
|
||||
58 - RESERVED
|
||||
59 - RESERVED
|
||||
60 - RESERVED
|
||||
61 - RESERVED
|
||||
62 - RESERVED
|
||||
63 - RESERVED
|
||||
DESTBLEND 29:24 none Destination Blend Function , Alpha blending function (DST).
|
||||
POSSIBLE VALUES:
|
||||
00 - RESERVED
|
||||
01 - D3D_ZERO
|
||||
02 - D3D_ONE
|
||||
03 - D3D_SRCCOLOR
|
||||
04 - D3D_INVSRCCOLOR
|
||||
05 - D3D_SRCALPHA
|
||||
06 - D3D_INVSRCALPHA
|
||||
07 - D3D_DESTALPHA
|
||||
08 - D3D_INVDESTALPHA
|
||||
09 - D3D_DESTCOLOR
|
||||
10 - D3D_INVDESTCOLOR
|
||||
11 - RESERVED
|
||||
12 - RESERVED
|
||||
13 - RESERVED
|
||||
14 - RESERVED
|
||||
15 - RESERVED
|
||||
16 - RESERVED
|
||||
17 - RESERVED
|
||||
18 - RESERVED
|
||||
19 - RESERVED
|
||||
20 - RESERVED
|
||||
21 - RESERVED
|
||||
22 - RESERVED
|
||||
23 - RESERVED
|
||||
24 - RESERVED
|
||||
25 - RESERVED
|
||||
26 - RESERVED
|
||||
27 - RESERVED
|
||||
28 - RESERVED
|
||||
29 - RESERVED
|
||||
30 - RESERVED
|
||||
31 - RESERVED
|
||||
32 - GL_ZERO
|
||||
33 - GL_ONE
|
||||
34 - GL_SRC_COLOR
|
||||
35 - GL_ONE_MINUS_SRC_COLOR
|
||||
36 - GL_DST_COLOR
|
||||
37 - GL_ONE_MINUS_DST_COLOR
|
||||
38 - GL_SRC_ALPHA
|
||||
39 - GL_ONE_MINUS_SRC_ALPHA
|
||||
40 - GL_DST_ALPHA
|
||||
41 - GL_ONE_MINUS_DST_ALPHA
|
||||
42 - RESERVED
|
||||
43 - GL_CONSTANT_COLOR
|
||||
44 - GL_ONE_MINUS_CONSTANT_COLOR
|
||||
45 - GL_CONSTANT_ALPHA
|
||||
46 - GL_ONE_MINUS_CONSTANT_ALPHA
|
||||
47 - RESERVED
|
||||
48 - RESERVED
|
||||
49 - RESERVED
|
||||
50 - RESERVED
|
||||
51 - RESERVED
|
||||
52 - RESERVED
|
||||
53 - RESERVED
|
||||
54 - RESERVED
|
||||
55 - RESERVED
|
||||
56 - RESERVED
|
||||
57 - RESERVED
|
||||
58 - RESERVED
|
||||
59 - RESERVED
|
||||
60 - RESERVED
|
||||
61 - RESERVED
|
||||
62 - RESERVED
|
||||
63 - RESERVED
|
||||
SRC_ALPHA_0_NO_READ 30 0x0 Enables source alpha zero performance optimization to
|
||||
skip reads.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable source alpha zero performance optimization to skip reads
|
||||
01 - Enable source alpha zero performance optimization to skip reads
|
||||
SRC_ALPHA_1_NO_READ 31 0x0 Enables source alpha one performance optimization to
|
||||
skip reads.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable source alpha one performance optimization to skip reads
|
||||
01 - Enable source alpha one performance optimization to skip reads
|
||||
45
regs/bits/rb3d_cctl.txt
Normal file
45
regs/bits/rb3d_cctl.txt
Normal file
@ -0,0 +1,45 @@
|
||||
Field Name Bits Default Description
|
||||
NUM_MULTIWRITES 6:5 0x0 A quad is replicated and written to this
|
||||
many buffers.
|
||||
POSSIBLE VALUES:
|
||||
00 - 1 buffer. This is the only mode where the cb processes the end of packet command.
|
||||
01 - 2 buffers
|
||||
02 - 3 buffers
|
||||
03 - 4 buffers
|
||||
CLRCMP_FLIPE_ENABLE 7 0x0 Enables equivalent of rage128
|
||||
CMP_EQ_FLIP color compare mode.
|
||||
This is used to ensure 3D data does not
|
||||
get chromakeyed away by logic in the
|
||||
backend.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable color compare.
|
||||
01 - Enable color compare.
|
||||
AA_COMPRESSION_ENABLE 9 none Enables AA color compression. Cmask
|
||||
must also be enabled when aa
|
||||
compression is enabled. The cache must
|
||||
be empty before this is changed.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable AA compression
|
||||
01 - Enable AA compression
|
||||
CMASK_ENABLE 10 none Enables use of the cmask ram. The cache
|
||||
must be empty before this is changed.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable
|
||||
01 - Enable
|
||||
INDEPENDENT_COLOR_CHANNEL_MASK_ENABLE 12 0x0 Enables indepedent color channel masks
|
||||
for the MRTs. Disabling this feature will
|
||||
cause all the MRTs to use color channel
|
||||
mask 0.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable
|
||||
01 - Enable
|
||||
WRITE_COMPRESSION_DISABLE 13 none Disables write compression.
|
||||
POSSIBLE VALUES:
|
||||
00 - Enable write compression
|
||||
01 - Disable write compression
|
||||
INDEPENDENT_COLORFORMAT_ENABLE 14 0x0 Enables independent color format for the
|
||||
MRTs. Disabling this feature will cause
|
||||
all the MRTs to use color format 0.
|
||||
POSSIBLE VALUES:
|
||||
00 - Disable
|
||||
01 - Enable
|
||||
3
regs/bits/rb3d_clrcmp_clr.txt
Normal file
3
regs/bits/rb3d_clrcmp_clr.txt
Normal file
@ -0,0 +1,3 @@
|
||||
Field Name Bits Default Description
|
||||
CLRCMP_CLR 31:0 none Like RB2D_CLRCMP_CLR, but a separate register is
|
||||
provided to keep 2D and 3D state separate.
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user