drm/texture_cube_clear_zwrite_vertex_shader: fixed

drm/Makefile

@@ -9,6 +9,9 @@ LDFLAGS += $(shell pkg-config --libs libdrm) -lm
 %: %.c
 	$(CC) $(ARCH) $(CFLAGS) $(LDFLAGS) $(OPT) $< -o $@
 
+%.inc: %.asm
+	PYTHONPATH=../regs/ python -m assembler $< > $@
+
 clean:
 	find . -type f ! -name "*.*" -delete
 

drm/clear_nop.vs.asm

@@ -0,0 +1 @@
+out[0].xyzw = VE_ADD input[0].xyzw input[0].0000 input[0].0000

drm/cube_rotate.vs.asm

@@ -0,0 +1,65 @@
+; CONST[0] = {0.159155, 0.5, 6.283185, -3.141593}
+; CONST[1] = {theta1, theta2, 0.2, 0.5}
+
+; each instruction is only allowed to use a single unique `const` address
+;
+; instructions may use multiple `temp` addresses, so const[1] is moved to
+; temp[0]:
+;
+temp[0].xy   = VE_ADD  const[1].xy__ const[1].00__
+
+; ME_SIN and ME_COS are clamped to the range -π to +π prior to the sin/cos
+; calculation.
+;
+; This 3-instruction sequence linearly remaps the range [-∞,+∞] to [-π,+π]
+temp[0].xy   = VE_MAD   temp[0].xy__   const[0].xy__  const[0].yy__
+temp[0].xy   = VE_FRC   temp[0].xy__
+temp[0].xy   = VE_MAD   temp[0].xy__   const[0].zz__  const[0].ww__
+
+; sin and cos
+temp[3].x    = ME_SIN   temp[0].___x
+temp[3].y    = ME_COS   temp[0].___x
+temp[4].x    = ME_SIN   temp[0].___y
+temp[4].y    = ME_COS   temp[0].___y
+
+; temp[3] now contains:
+; temp[3] = {sin(theta1), cos(theta1), sin(theta2), cos(theta2)}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; first rotation: X-axis rotation:
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; y_ = (-z0 * st1)
+; z_ = ( z0 * ct1)
+temp[1].yz    = VE_MUL   input[0]._-zz_  temp[3]._xy_
+
+; x1 = (x0 *   1 +      0)
+; y1 = (y0 * ct1 + nz0st1)
+; z1 = (y0 * st1 +  z0ct1)
+temp[1].xyz   = VE_MAD   input[0].xyy_   temp[3].1yx_   temp[1].0yz_
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; second rotation: Y-axis rotation:
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; x_ = (-z1 * st2)
+; z_ = ( z1 * ct2)
+temp[2].xz    = VE_MUL   temp[1].-z_z_   temp[4].x_y_
+
+; x2 = (x1 * ct2 + nz1st2)
+; y2 = (y1 *   1 +      0)
+; z2 = (x1 * st2 +  z1ct2)
+temp[2].xyz   = VE_MAD   temp[1].xyx_    temp[4].y1x_   temp[2].x0z_
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; scale
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+temp[3].xyz   = VE_MAD   temp[2].xyz_    const[1].zzz_  const[1].00w_
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; output
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+out[0].xyzw   = VE_MUL   temp[3].xyzz    temp[3].11-z1
+out[1].xyzw   = VE_ADD   input[1].xyzw   input[1].0000

drm/cube_rotate.vs.inc

@@ -0,0 +1,15 @@
+0x00300003, 0x01f90022, 0x01fc8022, 0x01ffe022,
+0x00300004, 0x01f90000, 0x01f90002, 0x01f92002,
+0x00300006, 0x01f90000, 0x01ffe000, 0x01ffe000,
+0x00300004, 0x01f90000, 0x01fa4002, 0x01fb6002,
+0x00106050, 0x003fe000, 0x01ffe000, 0x01ffe000,
+0x00206051, 0x003fe000, 0x01ffe000, 0x01ffe000,
+0x00108050, 0x007fe000, 0x01ffe000, 0x01ffe000,
+0x00208051, 0x007fe000, 0x01ffe000, 0x01ffe000,
+0x00602002, 0x05d2e001, 0x01c8e060, 0x01ffe060,
+0x00702080, 0x01c90001, 0x01c1a060, 0x01d18020,
+0x00504002, 0x03d74020, 0x01cf0080, 0x01ffe080,
+0x00704080, 0x01c10020, 0x01c52080, 0x01d40040,
+0x00706004, 0x01d10040, 0x01d24022, 0x01dc8022,
+0x00f00202, 0x00910060, 0x0955a060, 0x01ffe060,
+0x00f02203, 0x00d10021, 0x01248021, 0x01ffe021,

drm/rotate.vs.asm

@@ -1,9 +1,9 @@
-; CONST[0] = {rotate, _, _, _}
+; CONST[0] = {0.159155, 0.5, 6.283185, -3.141593}
-; CONST[1] = {0.159155, 0.5, 6.283185, -3.141593}
+; CONST[1] = {rotate, _, _, _}
 
 ; each instruction is only allowed to use a single unique `const` address
 ;
-; instructions may use multiple `temp` addresses, so const[0] is moved to
+; instructions may use multiple `temp` addresses, so const[1] is moved to
 ; temp[0]:
 ;
 temp[0].x    = VE_ADD  const[1].x___  const[1].0___

regs/assembler/__main__.py

@@ -3,6 +3,7 @@ import sys
 from assembler.lexer import Lexer, LexerError
 from assembler.parser import Parser, ParserError
 from assembler.emitter import emit_instruction
+from assembler.validator import validate_instruction
 
 sample = b"""
 temp[0].xyzw = VE_ADD    const[1].xyzw     const[1].0000     const[1].0000
@@ -22,6 +23,7 @@ def frontend_inner(buf):
     tokens = list(lexer.lex_tokens())
     parser = Parser(tokens)
     for ins, start_end in parser.instructions():
+        ins = validate_instruction(ins)
         yield list(emit_instruction(ins)), start_end
 
 def print_error(filename, buf, e):

regs/assembler/emitter.py

@@ -1,4 +1,4 @@
-from assembler.keywords import ME, VE, KW
+from assembler.keywords import ME, VE, MVE, KW
 from assembler.parser import Instruction, DestinationOp, Source
 import pvs_dst
 import pvs_src
@@ -34,8 +34,10 @@ def dst_reg_type(kw):
         assert not "Invalid PVS_DST_REG", kw
 
 def emit_destination_op(dst_op: DestinationOp):
-    assert type(dst_op.opcode) in {ME, VE}
+    assert type(dst_op.opcode) in {ME, VE, MVE}
     math_inst = int(type(dst_op.opcode) is ME)
+    if dst_op.macro:
+        assert dst_op.opcode.value in {0, 1}
     value = (
           pvs_dst.OPCODE_gen(dst_op.opcode.value)
         | pvs_dst.MATH_INST_gen(math_inst)
@@ -45,6 +47,7 @@ def emit_destination_op(dst_op: DestinationOp):
         | pvs_dst.WE_Y_gen(we_y(dst_op.write_enable))
         | pvs_dst.WE_Z_gen(we_z(dst_op.write_enable))
         | pvs_dst.WE_W_gen(we_w(dst_op.write_enable))
+        | pvs_dst.MACRO_INST_gen(int(dst_op.macro))
     )
     yield value
 

regs/assembler/keywords.py

@@ -2,6 +2,12 @@ from dataclasses import dataclass
 from typing import Optional
 from enum import Enum, auto
 
+@dataclass
+class MVE:
+    name: str
+    synonym: Optional[str]
+    value: int
+
 @dataclass
 class VE:
     name: str
@@ -14,6 +20,11 @@ class ME:
     synonym: Optional[str]
     value: int
 
+macro_vector_operations = [
+    MVE(b"MACRO_OP_2CLK_MADD"       , None      , 0),
+    MVE(b"MACRO_OP_2CLK_M2X_ADD"    , None      , 1),
+]
+
 vector_operations = [
        # name                       synonym    value
     VE(b"VECTOR_NO_OP"              , b"VE_NOP" , 0),

regs/assembler/parser.py

@@ -25,6 +25,7 @@ class DestinationOp:
     offset: int
     write_enable: set[int]
     opcode: Union[VE, ME]
+    macro: bool
 
 @dataclass
 class SourceSwizzle:
@@ -172,7 +173,8 @@ class Parser:
         write_enable = parse_dest_write_enable(write_enable_token)
         self.consume(TT.equal, "expected equals")
         opcode = self.opcode()
-        return DestinationOp(destination_type, offset_value, write_enable, opcode)
+        macro = False
+        return DestinationOp(destination_type, offset_value, write_enable, opcode, macro)
 
     def source_type(self):
         token = self.consume(TT.keyword, "expected source type")

regs/assembler/validator.py

@@ -0,0 +1,25 @@
+from assembler.keywords import ME, VE, macro_vector_operations
+
+class ValidatorError(Exception):
+    pass
+
+def validate_instruction(ins):
+    addresses = len(set(
+        source.offset
+        for source in [ins.source0, ins.source1, ins.source2]
+        if source is not None
+    ))
+    if addresses > 2:
+        if type(ins.destination_op.opcode) is not VE:
+            raise ValidatorError("too many addresses for non-VE instruction", ins)
+        if ins.destination_op.opcode.name not in {b"VE_MULTIPLYX2_ADD", b"VE_MULTIPLY_ADD"}:
+            raise ValidatorError("too many addresses for VE non-multiply-add instruction", ins)
+        assert ins.destination_op.macro == False, ins
+        ins.destination_op.macro = True
+        if ins.destination_op.opcode.name == b"VE_MULTIPLY_ADD":
+            ins.destination_op.opcode = macro_vector_operations[0]
+        elif ins.destination_op.opcode.name == b"VE_MULTIPLYX2_ADD":
+            ins.destination_op.opcode = macro_vector_operations[1]
+        else:
+            assert False
+    return ins

regs/pvs_bits/pvs_opcode_and_destination_operand_bits.txt

@@ -1,3 +1,6 @@
+MACRO_OPCODE:
+MACRO_OP_2CLK_MADD    = 0
+MACRO_OP_2CLK_M2X_ADD = 1
 VECTOR_OPCODE:
 VECTOR_NO_OP              = 0
 VE_DOT_PRODUCT            = 1

regs/pvs_disassemble.py

@@ -88,7 +88,6 @@ def parse_dst_op(dst_op):
     addr_sel = pvs_dst.ADDR_SEL(dst_op)
 
     assert addr_mode == 0
-    assert macro_inst == 0
     assert pred_enable == 0
     assert pred_sense == 0
     assert dual_math_op == 0
@@ -102,7 +101,10 @@ def parse_dst_op(dst_op):
     parts.append(f"{reg_str}[{offset}].{we_swizzle}")
 
     if math_inst:
+        assert not macro_inst
         parts.append(op_substitutions(pvs_dst_bits.MATH_OPCODE[opcode]))
+    elif macro_inst:
+        parts.append(op_substitutions(pvs_dst_bits.MACRO_OPCODE[opcode]))
     else:
         parts.append(op_substitutions(pvs_dst_bits.VECTOR_OPCODE[opcode]))
 

shader_examples/mesa/texture_cube_vertex_shader.vs.txt

@@ -0,0 +1,128 @@
+0x00f00003,
+0x00d10022,
+0x01248022,
+0x01248022,
+0x00f02003,
+0x00d10022,
+0x01248022,
+0x01248022,
+0x00100004,
+0x01ff0002,
+0x01ff0020,
+0x01ff2000,
+0x00100006,
+0x01ff0000,
+0x01248000,
+0x01248000,
+0x00100004,
+0x01ff0000,
+0x01ff4022,
+0x01ff6022,
+0x00200050,
+0x00000000,
+0x01248000,
+0x01248000,
+0x00600002,
+0x01d1e001,
+0x01c9e000,
+0x01248000,
+0x00100051,
+0x00000000,
+0x01248000,
+0x01248000,
+0x00800004,
+0x00bfe001,
+0x003fe000,
+0x007fe000,
+0x00f02003,
+0x00d10022,
+0x01248022,
+0x01248022,
+0x00f04003,
+0x00d10002,
+0x01248002,
+0x01248002,
+0x00102004,
+0x01ff0042,
+0x01ff0040,
+0x01ff2020,
+0x00102006,
+0x01ff0020,
+0x01248020,
+0x01248020,
+0x00102004,
+0x01ff0020,
+0x01ff4022,
+0x01ff6022,
+0x00102050,
+0x00000020,
+0x01248020,
+0x01248020,
+0x00f04003,
+0x00d10022,
+0x01248022,
+0x01248022,
+0x00102004,
+0x01ff2042,
+0x01ff0020,
+0x01ff2040,
+0x00102006,
+0x01ff0020,
+0x01248020,
+0x01248020,
+0x00102004,
+0x01ff0020,
+0x01ff4022,
+0x01ff6022,
+0x00202051,
+0x00000020,
+0x01248020,
+0x01248020,
+0x00102050,
+0x00000020,
+0x01248020,
+0x01248020,
+0x00402002,
+0x01dfe000,
+0x01c7e020,
+0x01248020,
+0x00402004,
+0x01c7e001,
+0x01cfe020,
+0x09d7e020,
+0x00100004,
+0x01ff2001,
+0x01ff0000,
+0x03ff4000,
+0x00200002,
+0x01fbe000,
+0x01f9e020,
+0x01248020,
+0x00200004,
+0x01f8e001,
+0x01f8e020,
+0x01f9e000,
+0x00f04003,
+0x00d10022,
+0x01248022,
+0x01248022,
+0x00200004,
+0x01f9e000,
+0x01fae042,
+0x01f9e040,
+0x00400002,
+0x01cfe000,
+0x01cfe000,
+0x01248000,
+0x00500204,
+0x01ef4020,
+0x01e74042,
+0x09d78000,
+0x00302203,
+0x01f90021,
+0x01248021,
+0x01248021,
+0x00a00204,
+0x0178e000,
+0x013ae042,
+0x007ce000,