diff --git a/drm/shadertoy.c b/drm/shadertoy.c
index 0572446..b34b60c 100644
--- a/drm/shadertoy.c
+++ b/drm/shadertoy.c
@@ -452,7 +452,7 @@ int indirect_buffer()
   // fragment code
 
   const uint32_t fragment_shader[] = {
-    #include "shadertoy_sin.fs.inc"
+    #include "shadertoy_circle.fs.inc"
   };
   const int fragment_shader_length = (sizeof (fragment_shader)) / (sizeof (fragment_shader[0]));
   assert(fragment_shader_length % 6 == 0);
diff --git a/drm/shadertoy_circle.fs.asm b/drm/shadertoy_circle.fs.asm
index ebedc47..68324ac 100644
--- a/drm/shadertoy_circle.fs.asm
+++ b/drm/shadertoy_circle.fs.asm
@@ -1,23 +1,22 @@
-# CONST[0] = (-0.1, 0, 0, 0)
-
 # d = length(uv)
 src0.rgb = temp[0] :
   temp[0].r    = DP3 src0.rg0 src0.rg0 ;
 src0.rgb = temp[0] :
   temp[0].a    = RSQ |src0.r| ;
+NOP
 src0.a   = temp[0] :
   temp[0].a    = RCP src0.a ;
 
 # d = abs(d - 0.5) * 1 + -0.1
-src0.rgb = float(48), # 0.5
-src1.rgb = temp[0],   # d
-src2.rgb = const[0],  # -0.1
-srcp.rgb = sub :      # (src1.rgb - src0.rgb)
-  temp[0].r    = MAD |srcp.r00| src0.100 src2.r00 ;
+src0.a = float(48), # 0.5
+src1.a = temp[0],   # d
+src2.a = float(29), # 0.1015625
+srcp.a = sub :      # (src1.a - src0.a)
+  temp[0].a    = MAD |srcp.a| src0.1 -src2.a ;
 
 # d = (d >= 0.0) ? 1.0 : 0.0
 # out.rgba = vec4(d, 0, 0, 1)
 OUT TEX_SEM_WAIT
-src0.rgb = temp[0] :
+src0.a = temp[0] :
   out[0].a    = MAX src0.1 src0.1 ,
-  out[0].rgb  = CMP src0.100 src0.000 src0.r00 ;
+  out[0].rgb  = CMP src0.100 src0.000 src0.a00 ;
diff --git a/drm/shadertoy_circle.fs.inc b/drm/shadertoy_circle.fs.inc
index 05c8e71..7060587 100644
--- a/drm/shadertoy_circle.fs.inc
+++ b/drm/shadertoy_circle.fs.inc
@@ -12,17 +12,24 @@
 0x0004000b,
 0x00000000,
 
-0x00004000,
+0x00004200,
 0x08020080,
 0x08020000,
 0x00000000,
 0x0000c00a,
 0x00000000,
 
-0x00000800,
-0x500000b0,
+0x00004000,
 0x08020080,
-0x00931483,
+0x49d000b0,
 0x00000000,
-0x00482000,
+0x00c4f000,
+0x5c000000,
+
+0x00078005,
+0x08020080,
+0x08020000,
+0x00920498,
+0x00c18003,
+0x0048c008,
 
diff --git a/regs/assembler/fs/emitter.py b/regs/assembler/fs/emitter.py
index fa6d3ce..63c81c5 100644
--- a/regs/assembler/fs/emitter.py
+++ b/regs/assembler/fs/emitter.py
@@ -167,6 +167,7 @@ def emit_addr(code, addr):
 def emit_instruction(code, ins):
     US_CMN_INST.TYPE(code, ins.type.value)
     US_CMN_INST.TEX_SEM_WAIT(code, int(ins.tex_sem_wait))
+    US_CMN_INST.NOP(code, int(ins.nop))
 
     emit_addr(code, ins.addr)
     if ins.alpha_op is not None:
diff --git a/regs/assembler/fs/keywords.py b/regs/assembler/fs/keywords.py
index 42a4048..d47a4f4 100644
--- a/regs/assembler/fs/keywords.py
+++ b/regs/assembler/fs/keywords.py
@@ -39,6 +39,7 @@ class KW(Enum):
     NEG = auto()
 
     # modifiers
+    NOP = auto()
     TEX_SEM_WAIT = auto()
 
 _string_to_keyword = {
@@ -73,6 +74,7 @@ _string_to_keyword = {
     b"SUB": KW.SUB,
     b"ADD": KW.ADD,
     b"NEG": KW.NEG,
+    b"NOP": KW.NOP,
     b"TEX_SEM_WAIT": KW.TEX_SEM_WAIT,
 }
 _keyword_to_string = {v:k for k,v in _string_to_keyword.items()}
diff --git a/regs/assembler/fs/parser.py b/regs/assembler/fs/parser.py
index f1a9bd4..49a2745 100644
--- a/regs/assembler/fs/parser.py
+++ b/regs/assembler/fs/parser.py
@@ -42,6 +42,7 @@ class Operation:
 class Instruction:
     out: bool
     tex_sem_wait: bool
+    nop: bool
     let_expressions: list[LetExpression]
     operations: list[Operation]
 
@@ -165,6 +166,10 @@ class Parser(BaseParser):
         if self.match_keyword(KW.TEX_SEM_WAIT):
             self.advance()
             tex_sem_wait = True
+        nop = False
+        if self.match_keyword(KW.NOP):
+            self.advance()
+            nop = True
 
         let_expressions = []
         while not self.match(TT.colon):
@@ -185,6 +190,7 @@ class Parser(BaseParser):
         return Instruction(
             out,
             tex_sem_wait,
+            nop,
             let_expressions,
             operations,
         )
diff --git a/regs/assembler/fs/validator.py b/regs/assembler/fs/validator.py
index 3ac744a..cf8690e 100644
--- a/regs/assembler/fs/validator.py
+++ b/regs/assembler/fs/validator.py
@@ -149,6 +149,7 @@ class InstructionType(IntEnum):
 class Instruction:
     type: InstructionType
     tex_sem_wait: bool
+    nop: bool
     addr: Addr
     alpha_op: AlphaOperation
     rgb_op: RGBOperation
@@ -485,10 +486,12 @@ def validate_instruction(ins):
 
     instruction_type = InstructionType.OUT if ins.out else InstructionType.ALU
     tex_sem_wait = ins.tex_sem_wait
+    nop = ins.nop
 
     instruction = Instruction(
         instruction_type,
         tex_sem_wait,
+        nop,
         addr_rgb_alpha,
         None,
         None
diff --git a/regs/us_disassemble2.py b/regs/us_disassemble2.py
index b2d7344..6b43d22 100644
--- a/regs/us_disassemble2.py
+++ b/regs/us_disassemble2.py
@@ -224,8 +224,6 @@ def assert_zeros(code):
     assert write_inactive == 0
     last = US_CMN_INST.LAST(code)
     assert last == 0
-    nop = US_CMN_INST.NOP(code)
-    assert nop == 0
     alu_wait = US_CMN_INST.ALU_WAIT(code)
     assert alu_wait == 0
     alu_result_sel = US_CMN_INST.ALU_RESULT_SEL(code)
@@ -297,6 +295,7 @@ def disassemble_alu(code, is_output):
 
     type = US_CMN_INST.TYPE(code)
     tex_sem_wait = US_CMN_INST.TEX_SEM_WAIT(code)
+    nop = US_CMN_INST.NOP(code)
 
     _, a_op, _ = US_ALU_ALPHA_INST._ALPHA_OP(code)
     _, rgb_op, _ = US_ALU_RGBA_INST._RGB_OP(code)
@@ -312,6 +311,8 @@ def disassemble_alu(code, is_output):
         tags.append("OUT")
     if tex_sem_wait:
         tags.append("TEX_SEM_WAIT")
+    if nop:
+        tags.append("NOP")
     if tags:
         print(" ".join(tags))