regs/bits: fix all parse errors

regs/bits/cp_rb_cntl.txt

@@ -35,7 +35,7 @@ RB_NO_UPDATE          27     0x0     Ring Buffer No Write to Read Pointer. The p
                                      POSSIBLE VALUES:
                                      00 - Write to Host`s copy of Read Pointer in system memory.
                                      01 - Do not write to Host`s copy of Read pointer.
-RB_RPTR_WR_ENA        31     0bx0    Ring Buffer Read Pointer Write Transfer Enable. When
+RB_RPTR_WR_ENA        31     0x0     Ring Buffer Read Pointer Write Transfer Enable. When
                                      set the contents of the CP_RB_RPTR_WR register is
                                      transferred to the active read pointer (CP_RB_RPTR)
                                      whenever the CP_RB_WPTR register is written.

regs/bits/gb_tile_config.txt

@@ -14,8 +14,8 @@ PIPE_COUNT             3:1    0x0     Specifies the number of active pipes and c
                                       POSSIBLE VALUES:
                                       00 - RV350 (1 pipe, 1 ctx)
                                       03 - R300 (2 pipes, 1 ctx)
-                                      06 – R420-3P (3 pipes, 1 ctx)
+                                      06 - R420-3P (3 pipes, 1 ctx)
-                                      07 – R420 (4 pipes, 1 ctx)
+                                      07 - R420 (4 pipes, 1 ctx)
 TILE_SIZE              5:4    0x1     Specifies width & height (square), in pixels (only 16, 32
                                       available).
                                       POSSIBLE VALUES:

regs/bits/vap_prog_stream_cntl.txt

@@ -43,6 +43,6 @@ NORMALIZE_0            15     0x0     Determines whether the fixed to floating p
 DATA_TYPE_1            19:16  0x0     Similar to DATA_TYPE_0
 SKIP_DWORDS_1          23:20  0x0     See SKIP_DWORDS_0
 DST_VEC_LOC_1          28:24  0x0     See DST_VEC_LOC_0
-LAST_VEC_1             29  0x0        See LAST_VEC_0
+LAST_VEC_1             29     0x0     See LAST_VEC_0
-SIGNED_1               30  0x0        See SIGNED_0
+SIGNED_1               30     0x0     See SIGNED_0
-NORMALIZE_1            31  0x0        See NORMALIZE_0
+NORMALIZE_1            31     0x0     See NORMALIZE_0

regs/parse_bits.py

@@ -5,26 +5,42 @@ from dataclasses import dataclass
 from pprint import pprint
 from collections import OrderedDict
 
-def split_line_fields(line):
+def split_line_fields(line, fields):
-    fields = [0, 17, 24, 32]
     a = line[fields[0]:fields[1]]
     b = line[fields[1]:fields[2]]
     c = line[fields[2]:fields[3]]
     d = line[fields[3]:]
+    assert a[-1] == ' '
+    assert b[-1] == ' '
+    assert c[-1] == ' ' or len(line) < fields[3]
     return a, b, c, d
 
+def find_line_fields(line):
+    field_name_ix = line.index('Field Name')
+    bits_ix = line.index('Bits')
+    default_ix = line.index('Default')
+    description_ix = line.index('Description')
+    assert field_name_ix == 0
+    assert bits_ix > field_name_ix
+    assert default_ix > bits_ix
+    assert description_ix > default_ix
+    return field_name_ix, bits_ix, default_ix, description_ix
+
 def parse_file_fields(filename):
     with open(filename) as f:
         lines = f.read().split('\n')
     first, *rest = lines
-    a, b, c, d = split_line_fields(first)
+    fields = find_line_fields(first)
-    assert a == 'Field Name       ', a
+    a, b, c, d = split_line_fields(first, fields)
-    assert b == 'Bits   ', b
+    assert a.rstrip() == 'Field Name', a
-    assert c == 'Default ', c
+    assert b.rstrip() == 'Bits', b
+    assert c.rstrip() == 'Default', c
     assert d.rstrip() == 'Description', d
 
     for line in rest:
-        a, b, c, d = split_line_fields(line)
+        if not line.strip():
+            continue
+        a, b, c, d = split_line_fields(line, fields)
         yield a.strip(), b.strip(), c.strip(), d.strip()
 
 def parse_bits(s):
@@ -60,8 +76,6 @@ def aggregate(fields):
         nonlocal ix
         if ix + 1 >= len(fields):
             return
-        if not fields[ix+1][0] == '':
-            return
         if not fields[ix+1][3] == 'POSSIBLE VALUES:':
             return
         ix += 1
@@ -89,7 +103,7 @@ def aggregate(fields):
                 ix += 1
 
     def parse_possible_value_num(s):
-        num, description = s.split(' - ')
+        num, description = s.split(' - ', maxsplit=1)
         num = int(num, 10)
         if ": " in description:
             name, description = description.split(": ")
@@ -99,17 +113,21 @@ def aggregate(fields):
 
     while ix < len(fields):
         field_name, bits, default, description = fields[ix]
-        description_lines = [description]
+        if description == 'POSSIBLE VALUES:':
-        description_lines.extend(parse_description_lines())
+            description_lines = []
+            ix -= 1
+        else:
+            description_lines = [description]
+            description_lines.extend(parse_description_lines())
         possible_values = OrderedDict(
             map(parse_possible_value_num, parse_possible_values())
         )
 
-        assert default.startswith('0x'), default
+        assert default.startswith('0x') or default == 'none', default
         yield Descriptor(
             field_name = field_name,
             bits = parse_bits(bits),
-            default = int(default, 16),
+            default = 0 if default == 'none' else int(default, 16),
             description = ' '.join(description_lines),
             possible_values = possible_values
         )

regs/pvs_bits/pvs_dual_math_instruction.txt

@@ -1,4 +1,4 @@
-Field Name            Bit(s)   Description
+Field Name            Bits     Description
 PVS_SRC_REG_TYPE      1:0      Defines the Memory Select (Register Type) for the Source Operand. See Below.
 PVS_DST_OPCODE_MSB    2        Math Opcode MSB for Dual Math Inst.
 PVS_SRC_ABS_XYZW      3        If set, Take absolute value of both components of Dual Math input vector.