add regs
This commit is contained in:
commit
c2d61ee383
110
regs/parse_bits.py
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110
regs/parse_bits.py
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@ -0,0 +1,110 @@
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import sys
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from typing import Union
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import re
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from dataclasses import dataclass
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from pprint import pprint
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def split_line_fields(line):
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fields = [0, 17, 24, 32]
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a = line[fields[0]:fields[1]]
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b = line[fields[1]:fields[2]]
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c = line[fields[2]:fields[3]]
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d = line[fields[3]:]
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return a, b, c, d
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def parse_file_fields(filename):
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with open(filename) as f:
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lines = f.read().split('\n')
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first, *rest = lines
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a, b, c, d = split_line_fields(first)
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assert a == 'Field Name ', a
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assert b == 'Bits ', b
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assert c == 'Default ', c
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assert d.rstrip() == 'Description', d
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for line in rest:
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a, b, c, d = split_line_fields(line)
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yield a.strip(), b.strip(), c.strip(), d.strip()
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def parse_bits(s):
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if ':' in s:
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a, b = s.split(':')
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h = int(a, 10)
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l = int(b, 10)
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assert h > l
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return h, l
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else:
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b = int(s, 10)
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return b
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@dataclass
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class Descriptor:
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field_name: str
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bits: Union[int, tuple[int, int]]
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default: int
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description: str
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possible_values: list[tuple[int, str]]
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def aggregate(fields):
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ix = 0
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descriptor = None
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def next_nonempty():
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nonlocal ix
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while ix < len(fields) and not ''.join(fields[ix]):
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ix += 1
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def parse_possible_values():
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nonlocal ix
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if ix + 1 >= len(fields):
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return
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if not fields[ix+1][0] == '':
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return
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if not fields[ix+1][3] == 'POSSIBLE VALUES:':
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return
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ix += 1
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while ix + 1 < len(fields) and fields[ix+1][0] == '' and fields[ix+1][3] != '':
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field_name, bits, default, description = fields[ix+1]
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assert not field_name, field_name
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assert not bits, bits
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assert not default, default
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assert re.match('^[0-9]{2} - ', description), repr(description)
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yield description
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ix += 1
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def parse_description_lines():
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nonlocal ix
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while ix + 1 < len(fields) and fields[ix+1][0] == '':
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field_name, bits, default, description = fields[ix+1]
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assert not field_name, field_name
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assert not bits, bits
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assert not default, default
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assert not re.match('^[0-9]{2} - ', description), description
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if description == 'POSSIBLE VALUES:':
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break
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else:
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yield description
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ix += 1
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while ix < len(fields):
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field_name, bits, default, description = fields[ix]
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description_lines = [description]
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description_lines.extend(parse_description_lines())
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possible_values = list(parse_possible_values())
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assert default.startswith('0x'), default
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yield Descriptor(
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field_name = field_name,
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bits = parse_bits(bits),
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default = int(default, 16),
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description = ' '.join(description_lines),
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possible_values = possible_values
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)
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ix += 1
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next_nonempty()
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l = list(parse_file_fields(sys.argv[1]))
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for descriptor in aggregate(l):
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pprint(descriptor, width=200)
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21
regs/pvs_dual_math_instruction.txt
Normal file
21
regs/pvs_dual_math_instruction.txt
Normal file
@ -0,0 +1,21 @@
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Field Name Bit(s) Description
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PVS_SRC_REG_TYPE 1:0 Defines the Memory Select (Register Type) for the Source Operand. See Below.
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PVS_DST_OPCODE_MSB 2 Math Opcode MSB for Dual Math Inst.
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PVS_SRC_ABS_XYZW 3 If set, Take absolute value of both components of Dual Math input vector.
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PVS_SRC_ADDR_MODE_0 4 Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE as follows:
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0 = Absolute addressing
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1 = Relative addressing using A0 register
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2 = Relative addressing using I0 register (loop index)
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PVS_SRC_OFFSET 12:5 Vector Offset into selected memory (Register Type)
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PVS_SRC_SWIZZLE_X 15:13 X-Component Swizzle Select. See Below
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PVS_SRC_SWIZZLE_Y 18:16 Y-Component Swizzle Select. See Below
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DUAL_MATH_DST_OFFSET 20:19 Selects Dest Address ATRM 0-3 for Math Inst.
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PVS_DST_OPCODE 24:21 Math Opcode for Dual Math Inst.
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PVS_SRC_MODIFIER_X 25 If set, Negate X Component of input vector.
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PVS_SRC_MODIFIER_Y 26 If set, Negate Y Component of input vector.
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PVS_DST_WE_SEL 28:27 Encoded Write Enable for Dual Math Op Inst (0 = X, 1 = Y, 2 = Z, 3 = W)
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PVS_SRC_ADDR_SEL 30:29 When PVS_SRC_ADDR_MODE is set, this selects which component of the 4-component address register to use.
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PVS_SRC_ADDR_MODE_1 31 Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE as follows:
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0 = Absolute addressing
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1 = Relative addressing using A0 register
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2 = Relative addressing using I0 register (loop index)
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18
regs/pvs_opcode_and_destination_operand.txt
Normal file
18
regs/pvs_opcode_and_destination_operand.txt
Normal file
@ -0,0 +1,18 @@
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Field Name Bits Description
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PVS_DST_OPCODE 5:0 Selects the Operation which is to be performed.
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PVS_DST_MATH_INST 6 Specifies a Math Engine Operation
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PVS_DST_MACRO_INST 7 Specifies a Macro Operation
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PVS_DST_REG_TYPE 11:8 Defines the Memory Select (Register Type) for the Dest Operand.
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PVS_DST_ADDR_MODE_1 12 Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE
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PVS_DST_OFFSET 20 Vector Offset into the Selected Memory
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PVS_DST_WE_X 21 Write Enable for X Component
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PVS_DST_WE_Y 22 Write Enable for Y Component
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PVS_DST_WE_Z 23 Write Enable for Z Component
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PVS_DST_WE_W 24 Write Enable for W Component
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PVS_DST_VE_SAT 19:13 Vector engine operation is saturate clamped between 0 and 1 (all components)
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PVS_DST_ME_SAT 25 Math engine operation is saturate clamped between 0 and 1 (all components)
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PVS_DST_PRED_ENABLE 26 Operation is predicated – Operation writes if predicate bit matches predicate sense.
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PVS_DST_PRED_SENSE 27 Operation predication sense – If set, operation writes if predicate bit is set. If reset, operation writes if predicate bit is reset.
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PVS_DST_DUAL_MATH_OP 28 Set to describe a dual-math op.
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PVS_DST_ADDR_SEL 30:29 When PVS_DST_ADDR_MODE is set, this selects which component of the 4-component address register to use.
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PVS_DST_ADDR_MODE_0 31 Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE
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60
regs/pvs_opcode_and_destination_operand_bits.txt
Normal file
60
regs/pvs_opcode_and_destination_operand_bits.txt
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@ -0,0 +1,60 @@
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VECTOR_OPCODE:
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VECTOR_NO_OP = 0
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VE_DOT_PRODUCT = 1
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VE_MULTIPLY = 2
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VE_ADD = 3
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VE_MULTIPLY_ADD = 4
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VE_DISTANCE_VECTOR = 5
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VE_FRACTION = 6
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VE_MAXIMUM = 7
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VE_MINIMUM = 8
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VE_SET_GREATER_THAN_EQUAL = 9
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VE_SET_LESS_THAN = 10
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VE_MULTIPLYX2_ADD = 11
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VE_MULTIPLY_CLAMP = 12
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VE_FLT2FIX_DX = 13
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VE_FLT2FIX_DX_RND = 14
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VE_PRED_SET_EQ_PUSH = 15
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VE_PRED_SET_GT_PUSH = 16
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VE_PRED_SET_GTE_PUSH = 17
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VE_PRED_SET_NEQ_PUSH = 18
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VE_COND_WRITE_EQ = 19
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VE_COND_WRITE_GT = 20
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VE_COND_WRITE_GTE = 21
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VE_COND_WRITE_NEQ = 22
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VE_COND_MUX_EQ = 23
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VE_COND_MUX_GT = 24
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VE_COND_MUX_GTE = 25
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VE_SET_GREATER_THAN = 26
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VE_SET_EQUAL = 27
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VE_SET_NOT_EQUAL = 28
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MATH_OPCODE:
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MATH_NO_OP = 0
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ME_EXP_BASE2_DX = 1
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ME_LOG_BASE2_DX = 2
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ME_EXP_BASEE_FF = 3
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ME_LIGHT_COEFF_DX = 4
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ME_POWER_FUNC_FF = 5
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ME_RECIP_DX = 6
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ME_RECIP_FF = 7
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ME_RECIP_SQRT_DX = 8
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ME_RECIP_SQRT_FF = 9
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ME_MULTIPLY = 10
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ME_EXP_BASE2_FULL_DX = 11
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ME_LOG_BASE2_FULL_DX = 12
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ME_POWER_FUNC_FF_CLAMP_B = 13
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ME_POWER_FUNC_FF_CLAMP_B1 = 14
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ME_POWER_FUNC_FF_CLAMP_01 = 15
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ME_SIN = 16
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ME_COS = 17
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ME_LOG_BASE2_IEEE = 18
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ME_RECIP_IEEE = 19
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ME_RECIP_SQRT_IEEE = 20
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ME_PRED_SET_EQ = 21
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ME_PRED_SET_GT = 22
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ME_PRED_SET_GTE = 23
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ME_PRED_SET_NEQ = 24
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ME_PRED_SET_CLR = 25
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ME_PRED_SET_INV = 26
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ME_PRED_SET_POP = 27
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ME_PRED_SET_RESTORE = 28
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16
regs/pvs_source_operand.txt
Normal file
16
regs/pvs_source_operand.txt
Normal file
@ -0,0 +1,16 @@
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Field Name Bit(s) Description
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PVS_SRC_REG_TYPE 1:0 Defines the Memory Select (Register Type) for the Source Operand. See Below.
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SPARE_0 2
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PVS_SRC_ABS_XYZW 3 If set, Take absolute value of all 4 components of input vector.
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PVS_SRC_ADDR_MODE_0 4 Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE
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PVS_SRC_OFFSET 12:5 Vector Offset into selected memory (Register Type)
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PVS_SRC_SWIZZLE_X 15:13 X-Component Swizzle Select. See Below
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PVS_SRC_SWIZZLE_Y 18:16 Y-Component Swizzle Select. See Below
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PVS_SRC_SWIZZLE_Z 21:19 Z-Component Swizzle Select. See Below
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PVS_SRC_SWIZZLE_W 24:22 W-Component Swizzle Select. See Below
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PVS_SRC_MODIFIER_X 25 If set, Negate X Component of input vector.
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PVS_SRC_MODIFIER_Y 26 If set, Negate Y Component of input vector.
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PVS_SRC_MODIFIER_Z 27 If set, Negate Z Component of input vector.
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PVS_SRC_MODIFIER_W 28 If set, Negate W Component of input vector.
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PVS_SRC_ADDR_SEL 30:29 When PVS_SRC_ADDR_MODE is set, this selects which component of the 4-component address register to use.
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PVS_SRC_ADDR_MODE_1 31 Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE
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16
regs/pvs_source_operand_bits.txt
Normal file
16
regs/pvs_source_operand_bits.txt
Normal file
@ -0,0 +1,16 @@
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PVS_SRC_OFFSET:
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PVS_SRC_REG_TEMPORARY = 0 Intermediate storage
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PVS_SRC_REG_INPUT = 1 Input Vertex Storage
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PVS_SRC_REG_CONSTANT = 2 Constant State Storage
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PVS_SRC_REG_ALT_TEMPORARY = 3 Alternate Intermediate Storage
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PVS_SRC_ADDR_SEL:
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PVS_SRC_SELECT_X = 0 Select X Component
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PVS_SRC_SELECT_Y = 1 Select Y Component
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PVS_SRC_SELECT_Z = 2 Select Z Component
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PVS_SRC_SELECT_W = 3 Select W Component
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PVS_SRC_SELECT_FORCE_0 = 4 Force Component to 0.0
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PVS_SRC_SELECT_FORCE_1 = 5 Force Component to 1.0
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PVS_SRC_ADDR_MODE:
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Absolute addressing = 0
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Relative addressing using A0 register = 1
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Relative addressing using I0 register = 2
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70
regs/us_alu_alpha_addr.txt
Normal file
70
regs/us_alu_alpha_addr.txt
Normal file
@ -0,0 +1,70 @@
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Field Name Bits Default Description
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ADDR0 7:0 0x0 Specifies the identity of source operands a0, a1, and a2.
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If the const field is set, this number ranges from 0 to 255
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and specifies a location within the constant register bank.
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Otherwise: If the most significant bit is cleared, this field
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specifies a location within the current pixel stack frame
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(ranging from 0 to 127). If the most significant bit is set,
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then the lower 7 bits specify an inline unsigned floating-
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point constant with 4 bit exponent (bias 7) and 3 bit
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mantissa, including denormals but excluding
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infinite/NaN.
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ADDR0_CONST 8 0x0 Specifies whether the associated address is a constant
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register address or a temporary address / inline constant.
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POSSIBLE VALUES:
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00 - TEMPORARY: Address temporary register or inline constant value.
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01 - CONSTANT: Address constant register.
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ADDR0_REL 9 0x0 Specifies whether the loop register is added to the value
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of the associated address before it is used. This
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implements relative addressing.
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POSSIBLE VALUES:
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00 - NONE: Do not modify source address.
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01 - RELATIVE: Add aL before lookup.
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ADDR1 17:10 0x0 Specifies the identity of source operands a0, a1, and a2.
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If the const field is set, this number ranges from 0 to 255
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and specifies a location within the constant register bank.
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Otherwise: If the most significant bit is cleared, this field
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specifies a location within the current pixel stack frame
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(ranging from 0 to 127). If the most significant bit is set,
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then the lower 7 bits specify an inline unsigned floating-
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point constant with 4 bit exponent (bias 7) and 3 bit
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mantissa, including denormals but excluding
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infinite/NaN.
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ADDR1_CONST 18 0x0 Specifies whether the associated address is a constant
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register address or a temporary address / inline constant.
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POSSIBLE VALUES:
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00 - TEMPORARY: Address temporary register or inline constant value.
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01 - CONSTANT: Address constant register.
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ADDR1_REL 19 0x0 Specifies whether the loop register is added to the value
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of the associated address before it is used. This
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implements relative addressing.
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POSSIBLE VALUES:
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00 - NONE: Do not modify source address.
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01 - RELATIVE: Add aL before lookup.
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ADDR2 27:20 0x0 Specifies the identity of source operands a0, a1, and a2.
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If the const field is set, this number ranges from 0 to 255
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and specifies a location within the constant register bank.
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Otherwise: If the most significant bit is cleared, this field
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specifies a location within the current pixel stack frame
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(ranging from 0 to 127). If the most significant bit is set,
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then the lower 7 bits specify an inline unsigned floating-
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point constant with 4 bit exponent (bias 7) and 3 bit
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mantissa, including denormals but excluding
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infinite/NaN.
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ADDR2_CONST 28 0x0 Specifies whether the associated address is a constant
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register address or a temporary address / inline constant.
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POSSIBLE VALUES:
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00 - TEMPORARY: Address temporary register or inline constant value.
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01 - CONSTANT: Address constant register.
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ADDR2_REL 29 0x0 Specifies whether the loop register is added to the value
|
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of the associated address before it is used. This
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implements relative addressing.
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POSSIBLE VALUES:
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00 - NONE: Do not modify source address.
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01 - RELATIVE: Add aL before lookup.
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SRCP_OP 31:30 0x0 Specifies how the pre-subtract value (SRCP) is computed.
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POSSIBLE VALUES:
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00 - 1.0-2.0*A0
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01 - A1-A0
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02 - A1+A0
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03 - 1.0-A0
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95
regs/us_alu_alpha_inst.txt
Normal file
95
regs/us_alu_alpha_inst.txt
Normal file
@ -0,0 +1,95 @@
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Field Name Bits Default Description
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ALPHA_OP 3:0 0x0 Specifies the opcode for this instruction.
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POSSIBLE VALUES:
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00 - OP_MAD: Result = A*B + C
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01 - OP_DP: Result = dot product from RGB ALU
|
||||
02 - OP_MIN: Result = min(A,B)
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03 - OP_MAX: Result = max(A,B)
|
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04 - reserved
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05 - OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B
|
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06 - OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B
|
||||
07 - OP_FRC: Result = A-floor(A)
|
||||
08 - OP_EX2: Result = 2^^A
|
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09 - OP_LN2: Result = log2(A)
|
||||
10 - OP_RCP: Result = 1/A
|
||||
11 - OP_RSQ: Result = 1/sqrt(A)
|
||||
12 - OP_SIN: Result = sin(A*2pi)
|
||||
13 - OP_COS: Result = cos(A*2pi)
|
||||
14 - OP_MDH: Result = A*B + C; A is always topleft.src0, C is always topright.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.
|
||||
15 - OP_MDV: Result = A*B + C; A is always topleft.src0, C is always bottomleft.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.
|
||||
ALPHA_ADDRD 10:4 0x0 Specifies the address of the pixel stack frame register to
|
||||
which the Alpha result of this instruction is to be written.
|
||||
ALPHA_ADDRD_REL 11 0x0 Specifies whether the loop register is added to the value
|
||||
of ALPHA_ADDRD before it is used. This implements
|
||||
relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify destination address.
|
||||
01 - RELATIVE: Add aL to address before write.
|
||||
ALPHA_SEL_A 13:12 0x0 Specifies the operands for Alpha inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - src0
|
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01 - src1
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02 - src2
|
||||
03 - srcp
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||||
ALPHA_SWIZ_A 16:14 0x0 Specifies the channel sources for Alpha inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
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||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
ALPHA_MOD_A 18:17 0x0 Specifies the input modifiers for Alpha inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - NOP: Do not modify input
|
||||
01 - NEG: Negate input
|
||||
02 - ABS: Take absolute value of input
|
||||
03 - NAB: Take negative absolute value of input
|
||||
ALPHA_SEL_B 20:19 0x0 Specifies the operands for Alpha inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - src0
|
||||
01 - src1
|
||||
02 - src2
|
||||
03 - srcp
|
||||
ALPHA_SWIZ_B 23:21 0x0 Specifies the channel sources for Alpha inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
ALPHA_MOD_B 25:24 0x0 Specifies the input modifiers for Alpha inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - NOP: Do not modify input
|
||||
01 - NEG: Negate input
|
||||
02 - ABS: Take absolute value of input
|
||||
03 - NAB: Take negative absolute value of input
|
||||
OMOD 28:26 0x0 Specifies the output modifier for this instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Result * 1
|
||||
01 - Result * 2
|
||||
02 - Result * 4
|
||||
03 - Result * 8
|
||||
04 - Result / 2
|
||||
05 - Result / 4
|
||||
06 - Result / 8
|
||||
07 - Disable output modifier and clamping (result is copied exactly; only valid for MIN/MAX/CMP/CND)
|
||||
TARGET 30:29 0x0 This specifies which (cached) frame buffer target to write
|
||||
to. For non-output ALU instructions, this specifies how
|
||||
to compare the results against zero when setting the
|
||||
predicate bits.
|
||||
POSSIBLE VALUES:
|
||||
00 - A: Output to render target A. Predicate == (ALU)
|
||||
01 - B: Output to render target B. Predicate < (ALU)
|
||||
02 - C: Output to render target C. Predicate >= (ALU)
|
||||
03 - D: Output to render target D. Predicate != (ALU)
|
||||
W_OMASK 31 0x0 Specifies whether or not to write the Alpha component of
|
||||
the result of this instuction to the depth output fifo.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not write output to w.
|
||||
01 - A: Write the alpha channel only to w.
|
||||
71
regs/us_alu_rgb_addr.txt
Normal file
71
regs/us_alu_rgb_addr.txt
Normal file
@ -0,0 +1,71 @@
|
||||
Field Name Bits Default Description
|
||||
ADDR0 7:0 0x0 Specifies the identity of source operands rgb0, rgb1, and
|
||||
rgb2. If the const field is set, this number ranges from 0
|
||||
to 255 and specifies a location within the constant
|
||||
register bank. Otherwise: If the most significant bit is
|
||||
cleared, this field specifies a location within the current
|
||||
pixel stack frame (ranging from 0 to 127). If the most
|
||||
significant bit is set, then the lower 7 bits specify an
|
||||
inline unsigned floating-point constant with 4 bit
|
||||
exponent (bias 7) and 3 bit mantissa, including
|
||||
denormals but excluding infinite/NaN.
|
||||
ADDR0_CONST 8 0x0 Specifies whether the associated address is a constant
|
||||
register address or a temporary address / inline constant.
|
||||
POSSIBLE VALUES:
|
||||
00 - TEMPORARY: Address temporary register or inline constant value.
|
||||
01 - CONSTANT: Address constant register.
|
||||
ADDR0_REL 9 0x0 Specifies whether the loop register is added to the value
|
||||
of the associated address before it is used. This
|
||||
implements relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify source address.
|
||||
01 - RELATIVE: Add aL before lookup.
|
||||
ADDR1 17:10 0x0 Specifies the identity of source operands rgb0, rgb1, and
|
||||
rgb2. If the const field is set, this number ranges from 0
|
||||
to 255 and specifies a location within the constant
|
||||
register bank. Otherwise: If the most significant bit is
|
||||
cleared, this field specifies a location within the current
|
||||
pixel stack frame (ranging from 0 to 127). If the most
|
||||
significant bit is set, then the lower 7 bits specify an
|
||||
inline unsigned floating-point constant with 4 bit
|
||||
exponent (bias 7) and 3 bit mantissa, including
|
||||
denormals but excluding infinite/NaN.
|
||||
ADDR1_CONST 18 0x0 Specifies whether the associated address is a constant
|
||||
register address or a temporary address / inline constant.
|
||||
POSSIBLE VALUES:
|
||||
00 - TEMPORARY: Address temporary register or inline constant value.
|
||||
01 - CONSTANT: Address constant register.
|
||||
ADDR1_REL 19 0x0 Specifies whether the loop register is added to the value
|
||||
of the associated address before it is used. This
|
||||
implements relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify source address.
|
||||
01 - RELATIVE: Add aL before lookup.
|
||||
ADDR2 27:20 0x0 Specifies the identity of source operands rgb0, rgb1, and
|
||||
rgb2. If the const field is set, this number ranges from 0
|
||||
to 255 and specifies a location within the constant
|
||||
register bank. Otherwise: If the most significant bit is
|
||||
cleared, this field specifies a location within the current
|
||||
pixel stack frame (ranging from 0 to 127). If the most
|
||||
significant bit is set, then the lower 7 bits specify an
|
||||
inline unsigned floating-point constant with 4 bit
|
||||
exponent (bias 7) and 3 bit mantissa, including
|
||||
denormals but excluding infinite/NaN.
|
||||
ADDR2_CONST 28 0x0 Specifies whether the associated address is a constant
|
||||
register address or a temporary address / inline constant.
|
||||
POSSIBLE VALUES:
|
||||
00 - TEMPORARY: Address temporary register or inline constant value.
|
||||
01 - CONSTANT: Address constant register.
|
||||
ADDR2_REL 29 0x0 Specifies whether the loop register is added to the value
|
||||
of the associated address before it is used. This
|
||||
implements relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify source address.
|
||||
01 - RELATIVE: Add aL before lookup.
|
||||
SRCP_OP 31:30 0x0 Specifies how the pre-subtract value (SRCP) is
|
||||
computed.
|
||||
POSSIBLE VALUES:
|
||||
00 - 1.0-2.0*RGB0
|
||||
01 - RGB1-RGB0
|
||||
02 - RGB1+RGB0
|
||||
03 - 1.0-RGB0
|
||||
108
regs/us_alu_rgb_inst.txt
Normal file
108
regs/us_alu_rgb_inst.txt
Normal file
@ -0,0 +1,108 @@
|
||||
Field Name Bits Default Description
|
||||
RGB_SEL_A 1:0 0x0 Specifies the operands for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - src0
|
||||
01 - src1
|
||||
02 - src2
|
||||
03 - srcp
|
||||
RED_SWIZ_A 4:2 0x0 Specifies, per channel, the sources for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
GREEN_SWIZ_A 7:5 0x0 Specifies, per channel, the sources for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
BLUE_SWIZ_A 10:8 0x0 Specifies, per channel, the sources for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
RGB_MOD_A 12:11 0x0 Specifies the input modifiers for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - NOP: Do not modify input
|
||||
01 - NEG: Negate input
|
||||
02 - ABS: Take absolute value of input
|
||||
03 - NAB: Take negative absolute value of input
|
||||
RGB_SEL_B 14:13 0x0 Specifies the operands for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - src0
|
||||
01 - src1
|
||||
02 - src2
|
||||
03 - srcp
|
||||
RED_SWIZ_B 17:15 0x0 Specifies, per channel, the sources for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
GREEN_SWIZ_B 20:18 0x0 Specifies, per channel, the sources for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
BLUE_SWIZ_B 23:21 0x0 Specifies, per channel, the sources for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
RGB_MOD_B 25:24 0x0 Specifies the input modifiers for RGB inputs A and B.
|
||||
POSSIBLE VALUES:
|
||||
00 - NOP: Do not modify input
|
||||
01 - NEG: Negate input
|
||||
02 - ABS: Take absolute value of input
|
||||
03 - NAB: Take negative absolute value of input
|
||||
OMOD 28:26 0x0 Specifies the output modifier for this instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Result * 1
|
||||
01 - Result * 2
|
||||
02 - Result * 4
|
||||
03 - Result * 8
|
||||
04 - Result / 2
|
||||
05 - Result / 4
|
||||
06 - Result / 8
|
||||
07 - Disable output modifier and clamping (result is copied exactly; only valid for MIN/MAX/CMP/CND)
|
||||
TARGET 30:29 0x0 This specifies which (cached) frame buffer target to write
|
||||
to. For non-output ALU instructions, this specifies how
|
||||
to compare the results against zero when setting the
|
||||
predicate bits.
|
||||
POSSIBLE VALUES:
|
||||
00 - A: Output to render target A. Predicate == (ALU)
|
||||
01 - B: Output to render target B. Predicate < (ALU)
|
||||
02 - C: Output to render target C. Predicate >= (ALU)
|
||||
03 - D: Output to render target D. Predicate != (ALU)
|
||||
ALU_WMASK 31 0x0 Specifies whether to update the current ALU result.
|
||||
POSSIBLE VALUES:
|
||||
00 - Do not modify the current ALU result.
|
||||
01 - Modify the current ALU result based on the settings of ALU_RESULT_SEL and ALU_RESULT_OP.
|
||||
92
regs/us_alu_rgba_inst.txt
Normal file
92
regs/us_alu_rgba_inst.txt
Normal file
@ -0,0 +1,92 @@
|
||||
Field Name Bits Default Description
|
||||
RGB_OP 3:0 0x0 Specifies the opcode for this instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - OP_MAD: Result = A*B + C
|
||||
01 - OP_DP3: Result = A.r*B.r + A.g*B.g + A.b*B.b
|
||||
02 - OP_DP4: Result = A.r*B.r + A.g*B.g + A.b*B.b + A.a*B.a
|
||||
03 - OP_D2A: Result = A.r*B.r + A.g*B.g + C.b
|
||||
04 - OP_MIN: Result = min(A,B)
|
||||
05 - OP_MAX: Result = max(A,B)
|
||||
06 - reserved
|
||||
07 - OP_CND: Result = cnd(A,B,C) = (C>0.5)?A:B
|
||||
08 - OP_CMP: Result = cmp(A,B,C) = (C>=0.0)?A:B
|
||||
09 - OP_FRC: Result = A-floor(A)
|
||||
10 - OP_SOP: Result = ex2,ln2,rcp,rsq,sin,cos from Alpha ALU
|
||||
11 - OP_MDH: Result = A*B + C; A is always topleft.src0, C is always topright.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.
|
||||
12 - OP_MDV: Result = A*B + C; A is always topleft.src0, C is always bottomleft.src0 (source select and swizzles ignored). Input modifiers are respected for all inputs.
|
||||
RGB_ADDRD 10:4 0x0 Specifies the address of the pixel stack frame register to
|
||||
which the RGB result of this instruction is to be written.
|
||||
RGB_ADDRD_REL110x0Specifies whether the loop register is added to the value
|
||||
of RGB_ADDRD before it is used. This implements
|
||||
relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify destination address.
|
||||
01 - RELATIVE: Add aL to address before write.
|
||||
RGB_SEL_C 13:12 0x0 Specifies the operands for RGB and Alpha input C.
|
||||
POSSIBLE VALUES:
|
||||
00 - src0
|
||||
01 - src1
|
||||
02 - src2
|
||||
03 - srcp
|
||||
RED_SWIZ_C 16:14 0x0 Specifies, per channel, the sources for RGB and Alpha
|
||||
input C.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
GREEN_SWIZ_C 19:17 0x0 Specifies, per channel, the sources for RGB and Alpha
|
||||
input C.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
BLUE_SWIZ_C 22:20 0x0 Specifies, per channel, the sources for RGB and Alpha
|
||||
input C.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
RGB_MOD_C 24:23 0x0 Specifies the input modifiers for RGB and Alpha input C.
|
||||
POSSIBLE VALUES:
|
||||
00 - NOP: Do not modify input
|
||||
01 - NEG: Negate input
|
||||
02 - ABS: Take absolute value of input
|
||||
03 - NAB: Take negative absolute value of input
|
||||
ALPHA_SEL_C 26:25 0x0 Specifies the operands for RGB and Alpha input C.
|
||||
POSSIBLE VALUES:
|
||||
00 - src0
|
||||
01 - src1
|
||||
02 - src2
|
||||
03 - srcp
|
||||
ALPHA_SWIZ_C 29:27 0x0 Specifies, per channel, the sources for RGB and Alpha
|
||||
input C.
|
||||
POSSIBLE VALUES:
|
||||
00 - Red
|
||||
01 - Green
|
||||
02 - Blue
|
||||
03 - Alpha
|
||||
04 - Zero
|
||||
05 - Half
|
||||
06 - One
|
||||
07 - Unused
|
||||
ALPHA_MOD_C 31:30 0x0 Specifies the input modifiers for RGB and Alpha input C.
|
||||
POSSIBLE VALUES:
|
||||
00 - NOP: Do not modify input
|
||||
01 - NEG: Negate input
|
||||
02 - ABS: Take absolute value of input
|
||||
03 - NAB: Take negative absolute value of input
|
||||
128
regs/us_cmn_inst_bits.txt
Normal file
128
regs/us_cmn_inst_bits.txt
Normal file
@ -0,0 +1,128 @@
|
||||
Field Name Bits Default Description
|
||||
TYPE 1:0 0x0 Specifies the type of instruction. Note that output instructions
|
||||
write to render targets.
|
||||
POSSIBLE VALUES:
|
||||
00 - US_INST_TYPE_ALU: This instruction is an ALU instruction.
|
||||
01 - US_INST_TYPE_OUT: This instruction is an output instruction.
|
||||
02 - US_INST_TYPE_FC: This instruction is a flow control instruction.
|
||||
03 - US_INST_TYPE_TEX: This instruction is a texture instruction.
|
||||
TEX_SEM_WAIT 2 0x0 Specifies whether to wait for the texture semaphore.
|
||||
POSSIBLE VALUES:
|
||||
00 - This instruction may issue immediately.
|
||||
01 - This instruction will not issue until the texture semaphore is available.
|
||||
RGB_PRED_SEL 5:3 0x0 Specifies whether the instruction uses predication. For
|
||||
ALU/TEX/Output this specifies predication for the RGB
|
||||
channels only. For FC this specifies the predicate for the
|
||||
entire instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - US_PRED_SEL_NONE: No predication
|
||||
01 - US_PRED_SEL_RGBA: Independent Channel Predication
|
||||
02 - US_PRED_SEL_RRRR: R-Replicate Predication
|
||||
03 - US_PRED_SEL_GGGG: G-Replicate Predication
|
||||
04 - US_PRED_SEL_BBBB: B-Replicate Predication
|
||||
05 - US_PRED_SEL_AAAA: A-Replicate Predication
|
||||
RGB_PRED_INV 6 0x0 Specifies whether the predicate should be inverted. For
|
||||
ALU/TEX/Output this specifies predication for the RGB
|
||||
channels only. For FC this specifies the predicate for the
|
||||
entire instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Normal predication
|
||||
01 - Invert the value of the predicate
|
||||
WRITE_INACTIVE 7 0x0 Specifies which pixels to write to.
|
||||
POSSIBLE VALUES:
|
||||
00 - Only write to channels of active pixels
|
||||
01 - Write to channels of all pixels, including inactive pixels
|
||||
LAST 8 0x0 Specifies whether this is the last instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Do not terminate the shader after executing this instruction (unless this instruction is at END_ADDR).
|
||||
01 - All active pixels are willing to terminate after executing this instruction. There is no guarantee that the shader will actually terminate here. This feature is provided as a performance optimization for tests where pixels can conditionally terminate early.
|
||||
NOP 9 0x0 Specifies whether to insert a NOP instruction after this.
|
||||
This would get specified in order to meet dependency
|
||||
requirements for the pre-subtract inputs, and dependency
|
||||
requirements for src0 of an MDH/MDV instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Do not insert NOP instruction after this one.
|
||||
01 - Insert a NOP instruction after this one.
|
||||
ALU_WAIT 10 0x0 Specifies whether to wait for pending ALU instructions
|
||||
to complete before issuing this instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Do not wait for pending ALU instructions to complete before issuing the current instruction.
|
||||
01 - Wait for pending ALU instructions to complete before issuing the current instruction.
|
||||
RGB_WMASK 13:11 0x0 Specifies which components of the result of the RGB
|
||||
instruction are written to the pixel stack frame.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not write any output.
|
||||
01 - R: Write the red channel only.
|
||||
02 - G: Write the green channel only.
|
||||
03 - RG: Write the red and green channels.
|
||||
04 - B: Write the blue channel only.
|
||||
05 - RB: Write the red and blue channels.
|
||||
06 - GB: Write the green and blue channels.
|
||||
07 - RGB: Write the red, green, and blue channels.
|
||||
ALPHA_WMASK 14 0x0 Specifies whether the result of the Alpha instruction is
|
||||
written to the pixel stack frame.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not write register.
|
||||
01 - A: Write the alpha channel only.
|
||||
RGB_OMASK 17:15 0x0 Specifies which components of the result of the RGB
|
||||
instruction are written to the output fifo if this is an
|
||||
output instruction, and which predicate bits should be
|
||||
modified if this is an ALU instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not write any output.
|
||||
01 - R: Write the red channel only.
|
||||
02 - G: Write the green channel only.
|
||||
03 - RG: Write the red and green channels.
|
||||
04 - B: Write the blue channel only.
|
||||
05 - RB: Write the red and blue channels.
|
||||
06 - GB: Write the green and blue channels.
|
||||
07 - RGB: Write the red, green, and blue channels.
|
||||
ALPHA_OMASK 18 0x0 Specifies whether the result of the Alpha instruction is
|
||||
written to the output fifo if this is an output instruction,
|
||||
and whether the Alpha predicate bit should be modified
|
||||
if this is an ALU instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not write output.
|
||||
01 - A: Write the alpha channel only.
|
||||
RGB_CLAMP 19 0x0 Specifies RGB and Alpha clamp mode for this
|
||||
instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Do not clamp output.
|
||||
01 - Clamp output to the range [0,1].
|
||||
ALPHA_CLAMP 20 0x0 Specifies RGB and Alpha clamp mode for this
|
||||
instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Do not clamp output.
|
||||
01 - Clamp output to the range [0,1].
|
||||
ALU_RESULT_SEL 21 0x0 Specifies which component of the result of this
|
||||
instruction should be used as the `ALU result` by a
|
||||
subsequent flow control instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - RED: Use red as ALU result for FC.
|
||||
01 - ALPHA: Use alpha as ALU result for FC.
|
||||
ALPHA_PRED_INV 22 0x0 Specifies whether the predicate should be inverted. For
|
||||
ALU/TEX/Output this specifies predication for the alpha
|
||||
channel only. This field has no effect on FC instructions.
|
||||
POSSIBLE VALUES:
|
||||
00 - Normal predication
|
||||
01 - Invert the value of the predicate
|
||||
ALU_RESULT_OP 24:23 0x0 Specifies how to compare the ALU result against zero
|
||||
for the `alu_result` bit in a subsequent flow control
|
||||
instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Equal to
|
||||
01 - Less than
|
||||
02 - Greater than or equal to
|
||||
03 - Not equal
|
||||
ALPHA_PRED_SEL 27:25 0x0 Specifies whether the instruction uses predication. For
|
||||
ALU/TEX/Output this specifies predication for the alpha
|
||||
channel only. This field has no effect on FC instructions.
|
||||
POSSIBLE VALUES:
|
||||
00 - US_PRED_SEL_NONE: No predication
|
||||
01 - US_PRED_SEL_RGBA: A predication (identical to US_PRED_SEL_AAAA)
|
||||
02 - US_PRED_SEL_RRRR: R Predication
|
||||
03 - US_PRED_SEL_GGGG: G Predication
|
||||
04 - US_PRED_SEL_BBBB: B Predication
|
||||
05 - US_PRED_SEL_AAAA: A Predication
|
||||
STAT_WE 31:28 0x0 Specifies which components (R,G,B,A) contribute to the
|
||||
stat count
|
||||
8
regs/us_fc_addr.txt
Normal file
8
regs/us_fc_addr.txt
Normal file
@ -0,0 +1,8 @@
|
||||
Field Name Bits Default Description
|
||||
BOOL_ADDR 4:0 0x0 The address of the static boolean register to use in the jump function.
|
||||
INT_ADDR 12:8 0x0 The address of the static integer register to use for loop/rep and endloop/endrep.
|
||||
JUMP_ADDR 24:16 0x0 The address to jump to if the jump function evaluates to true.
|
||||
JUMP_GLOBAL 31 0x0 Specifies whether to interpret JUMP_ADDR as a global address.
|
||||
POSSIBLE VALUES:
|
||||
00 - Add the shader program offset in US_CODE_OFFSET.OFFSET_ADDR when calculating the destination address of a jump
|
||||
01 - Don`t use the shader program offset when calculating the destination address jump
|
||||
51
regs/us_fc_inst.txt
Normal file
51
regs/us_fc_inst.txt
Normal file
@ -0,0 +1,51 @@
|
||||
Field Name Bits Default Description
|
||||
OP 2:0 0x0 Specifies the type of flow control instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - US_FC_OP_JUMP: (if, endif, call, etc)
|
||||
01 - US_FC_OP_LOOP: same as jump except always take the jump if the static counter is 0. If we don`t take the jump, push initial loop counter and loop register (aL) values onto the loop stack.
|
||||
02 - US_FC_OP_ENDLOOP: same as jump but decrement the loop counter and increment the loop register (aL), and don`t take the jump if the loop counter becomes zero.
|
||||
03 - US_FC_OP_REP: same as loop but don`t push the loop register aL.
|
||||
04 - US_FC_OP_ENDREP: same as endloop but don`t update/pop the loop register aL.
|
||||
05 - US_FC_OP_BREAKLOOP: same as jump but pops the loop stacks if a pixel stops being active.
|
||||
06 - US_FC_OP_BREAKREP: same as breakloop but don`t pop the loop register if it jumps.
|
||||
07 - US_FC_OP_CONTINUE: used to disable pixels that are ready to jump to the ENDLOOP/ENDREP instruction.
|
||||
B_ELSE 4 0x0 Specifies whether to perform an else operation on the
|
||||
active and branch-inactive pixels before executing the
|
||||
instruction.
|
||||
POSSIBLE VALUES:
|
||||
00 - Don`t alter the branch state before executing the instruction.
|
||||
01 - Perform an else operation on the branch state before executing the instruction; pixels in the active state are moved to the branch inactive state with zero counter, and vice versa.
|
||||
JUMP_ANY 5 0x0 If set, jump if any active pixels want to take the jump
|
||||
(otherwise the instruction jumps only if all active pixels
|
||||
want to).
|
||||
POSSIBLE VALUES:
|
||||
00 - Jump if ALL active pixels want to take the jump (for if and else). If no pixels are active, jump.
|
||||
01 - Jump if ANY active pixels want to take the jump (for call, loop/rep and endrep/endloop). If no pixels are active, do not jump.
|
||||
A_OP 7:6 0x0 The address stack operation to perform if we take the jump.
|
||||
POSSIBLE VALUES:
|
||||
00 - US_FC_A_OP_NONE: Don`t change the address stack
|
||||
01 - US_FC_A_OP_POP: If we jump, pop the address stack and use that value for the jump target
|
||||
02 - US_FC_A_OP_PUSH: If we jump, push the current address onto the address stack
|
||||
JUMP_FUNC 15:8 0x0 A 2x2x2 table of boolean values indicating whether to
|
||||
take the jump. The table index is indexed by {ALU
|
||||
Compare Result, Predication Result, Boolean Value
|
||||
(from the static boolean address in
|
||||
US_FC_ADDR.BOOL)}. To determine whether to jump,
|
||||
look at bit ((alu_result<<2) | (predicate<<1) | bool).
|
||||
B_POP_CNT 20:16 0x0 The amount to decrement the branch counter by if
|
||||
US_FC_B_OP_DECR operation is performed.
|
||||
B_OP0 25:24 0x0 The branch state operation to perform if we don`t take
|
||||
the jump.
|
||||
POSSIBLE VALUES:
|
||||
00 - US_FC_B_OP_NONE: If we don`t jump, don`t alter the branch counter for any pixel.
|
||||
01 - US_FC_B_OP_DECR: If we don`t jump, decrement branch counter by B_POP_CNT for inactive ixels. Activate pixels with negative counters.
|
||||
02 - US_FC_B_OP_INCR: If we don`t jump, increment branch counter by 1 for inactive pixels. Deactivate pixels that decided to jump and set their counter to zero.
|
||||
B_OP1 27:26 0x0 The branch state operation to perform if we do take the jump.
|
||||
POSSIBLE VALUES:
|
||||
00 - US_FC_B_OP_NONE: If we do jump, don`t alter the branch counter for any pixel.
|
||||
01 - US_FC_B_OP_DECR: If we do jump, decrement branch counter by B_POP_CNT for inactive pixels. Activate pixels with negative counters.
|
||||
02 - US_FC_B_OP_INCR: If we do jump, increment branch counter by 1 for inactive pixels. Deactivate pixels that decided not to jump and set their counter to zero.
|
||||
IGNORE_UNCOVERED 28 0x0 If set, uncovered pixels will not participate in flow control decisions.
|
||||
POSSIBLE VALUES:
|
||||
00 - Include uncovered pixels in jump decisions
|
||||
01 - Ignore uncovered pixels in making jump decisions
|
||||
73
regs/us_tex_addr.txt
Normal file
73
regs/us_tex_addr.txt
Normal file
@ -0,0 +1,73 @@
|
||||
Field Name Bits Default Description
|
||||
SRC_ADDR 6:0 0x0 Specifies the location (within the shader pixel stack
|
||||
frame) of the texture address for this instruction
|
||||
SRC_ADDR_REL 7 0x0 Specifies whether the loop register is added to the value
|
||||
of the associated address before it is used. This
|
||||
implements relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify source address
|
||||
01 - RELATIVE: Add aL before lookup.
|
||||
SRC_S_SWIZ 9:8 0x0 Specify which colour channel of src_addr to use for S
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as S coordinate
|
||||
01 - Use G channel as S coordinate
|
||||
02 - Use B channel as S coordinate
|
||||
03 - Use A channel as S coordinate
|
||||
SRC_T_SWIZ 11:10 0x0 Specify which colour channel of src_addr to use for T
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as T coordinate
|
||||
01 - Use G channel as T coordinate
|
||||
02 - Use B channel as T coordinate
|
||||
03 - Use A channel as T coordinate
|
||||
SRC_R_SWIZ 13:12 0x0 Specify which colour channel of src_addr to use for R
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as R coordinate
|
||||
01 - Use G channel as R coordinate
|
||||
02 - Use B channel as R coordinate
|
||||
03 - Use A channel as R coordinate
|
||||
SRC_Q_SWIZ 15:14 0x0 Specify which colour channel of src_addr to use for Q
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as Q coordinate
|
||||
01 - Use G channel as Q coordinate
|
||||
02 - Use B channel as Q coordinate
|
||||
03 - Use A channel as Q coordinate
|
||||
DST_ADDR 22:16 0x0 Specifies the location (within the shader pixel stack
|
||||
frame) of the returned texture data for this instruction
|
||||
DST_ADDR_REL 23 0x0 Specifies whether the loop register is added to the value
|
||||
of the associated address before it is used. This
|
||||
implements relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify destination address
|
||||
01 - RELATIVE: Add aL before lookup.
|
||||
DST_R_SWIZ 25:24 0x0 Specify which colour channel of the returned texture data
|
||||
to write to the red channel of dst_addr
|
||||
POSSIBLE VALUES:
|
||||
00 - Write R channel to R channel
|
||||
01 - Write G channel to R channel
|
||||
02 - Write B channel to R channel
|
||||
03 - Write A channel to R channel
|
||||
DST_G_SWIZ 27:26 0x0 Specify which colour channel of the returned texture data
|
||||
to write to the green channel of dst_addr
|
||||
POSSIBLE VALUES:
|
||||
00 - Write R channel to G channel
|
||||
01 - Write G channel to G channel
|
||||
02 - Write B channel to G channel
|
||||
03 - Write A channel to G channel
|
||||
DST_B_SWIZ 29:28 0x0 Specify which colour channel of the returned texture data
|
||||
to write to the blue channel of dst_addr
|
||||
POSSIBLE VALUES:
|
||||
00 - Write R channel to B channel
|
||||
01 - Write G channel to B channel
|
||||
02 - Write B channel to B channel
|
||||
03 - Write A channel to B channel
|
||||
DST_A_SWIZ 31:30 0x0 Specify which colour channel of the returned texture data
|
||||
to write to the alpha channel of dst_addr
|
||||
POSSIBLE VALUES:
|
||||
00 - Write R channel to A channel
|
||||
01 - Write G channel to A channel
|
||||
02 - Write B channel to A channel
|
||||
03 - Write A channel to A channel
|
||||
73
regs/us_tex_addr_dxdy.txt
Normal file
73
regs/us_tex_addr_dxdy.txt
Normal file
@ -0,0 +1,73 @@
|
||||
Field Name Bits Default Description
|
||||
DX_ADDR 6:0 0x0 Specifies the location (within the shader pixel stack
|
||||
frame) of the DX value for this instruction
|
||||
DX_ADDR_REL 7 0x0 Specifies whether the loop register is added to the value
|
||||
of the associated address before it is used. This
|
||||
implements relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify source address
|
||||
01 - RELATIVE: Add aL before lookup.
|
||||
DX_S_SWIZ 9:8 0x0 Specify which colour channel of dx_addr to use for S
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as S coordinate
|
||||
01 - Use G channel as S coordinate
|
||||
02 - Use B channel as S coordinate
|
||||
03 - Use A channel as S coordinate
|
||||
DX_T_SWIZ 11:10 0x0 Specify which colour channel of dx_addr to use for T
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as T coordinate
|
||||
01 - Use G channel as T coordinate
|
||||
02 - Use B channel as T coordinate
|
||||
03 - Use A channel as T coordinate
|
||||
DX_R_SWIZ 13:12 0x0 Specify which colour channel of dx_addr to use for R
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as R coordinate
|
||||
01 - Use G channel as R coordinate
|
||||
02 - Use B channel as R coordinate
|
||||
03 - Use A channel as R coordinate
|
||||
DX_Q_SWIZ 15:14 0x0 Specify which colour channel of dx_addr to use for Q
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as Q coordinate
|
||||
01 - Use G channel as Q coordinate
|
||||
02 - Use B channel as Q coordinate
|
||||
03 - Use A channel as Q coordinate
|
||||
DY_ADDR 22:16 0x0 Specifies the location (within the shader pixel stack
|
||||
frame) of the DY value for this instruction
|
||||
DY_ADDR_REL 23 0x0 Specifies whether the loop register is added to the value
|
||||
of the associated address before it is used. This
|
||||
implements relative addressing.
|
||||
POSSIBLE VALUES:
|
||||
00 - NONE: Do not modify source address
|
||||
01 - RELATIVE: Add aL before lookup.
|
||||
DY_S_SWIZ 25:24 0x0 Specify which colour channel of dy_addr to use for S
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as S coordinate
|
||||
01 - Use G channel as S coordinate
|
||||
02 - Use B channel as S coordinate
|
||||
03 - Use A channel as S coordinate
|
||||
DY_T_SWIZ 27:26 0x0 Specify which colour channel of dy_addr to use for T
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as T coordinate
|
||||
01 - Use G channel as T coordinate
|
||||
02 - Use B channel as T coordinate
|
||||
03 - Use A channel as T coordinate
|
||||
DY_R_SWIZ 29:28 0x0 Specify which colour channel of dy_addr to use for R
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as R coordinate
|
||||
01 - Use G channel as R coordinate
|
||||
02 - Use B channel as R coordinate
|
||||
03 - Use A channel as R coordinate
|
||||
DY_Q_SWIZ 31:30 0x0 Specify which colour channel of dy_addr to use for Q
|
||||
coordinate
|
||||
POSSIBLE VALUES:
|
||||
00 - Use R channel as Q coordinate
|
||||
01 - Use G channel as Q coordinate
|
||||
02 - Use B channel as Q coordinate
|
||||
03 - Use A channel as Q coordinate
|
||||
26
regs/us_tex_inst.txt
Normal file
26
regs/us_tex_inst.txt
Normal file
@ -0,0 +1,26 @@
|
||||
Field Name Bits Default Description
|
||||
TEX_ID 19:16 0x0 Specifies the id of the texture map used for this instruction
|
||||
INST 24:22 0x0 Specifies the operation taking place for this instruction
|
||||
POSSIBLE VALUES:
|
||||
00 - NOP: Do nothing
|
||||
01 - LD: Do Texture Lookup (S,T,R)
|
||||
02 - TEXKILL: Kill pixel if any component is < 0
|
||||
03 - PROJ: Do projected texture lookup (S/Q,T/Q,R/Q)
|
||||
04 - LODBIAS: Do texture lookup with lod bias
|
||||
05 - LOD: Do texture lookup with explicit lod
|
||||
06 - DXDY: Do texture lookup with lod calculated from DX and DY
|
||||
TEX_SEM_ACQUIRE 25 0x0 Whether to hold the texture semaphore until the data is
|
||||
written to the temporary register.
|
||||
POSSIBLE VALUES:
|
||||
00 - Don`t hold the texture semaphore
|
||||
01 - Hold the texture semaphore until the data is written to the temporary register.
|
||||
IGNORE_UNCOVERED 26 0x0 If set, US will not request data for pixels which are
|
||||
uncovered. Clear this bit for indirect texture lookups.
|
||||
POSSIBLE VALUES:
|
||||
00 - Fetch texels for uncovered pixels
|
||||
01 - Don`t fetch texels for uncovered pixels
|
||||
UNSCALED 27 0x0 Whether to scale texture coordinates when sending them
|
||||
to the texture unit.
|
||||
POSSIBLE VALUES:
|
||||
00 - Scale the S, T, R texture coordinates from [0.0,1.0] to the dimensions of the target texture
|
||||
01 - Use the unscaled S, T, R texture coordates.
|
||||
Loading…
x
Reference in New Issue
Block a user