diff --git a/drm/3d_registers_undocumented.h b/drm/3d_registers_undocumented.h index bfebc9f..6437c49 100644 --- a/drm/3d_registers_undocumented.h +++ b/drm/3d_registers_undocumented.h @@ -1,2 +1,157 @@ -#define RADEON_WAIT_UNTIL 0x1720 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_HEIGHT_WIDTH 0x143c +#define DP_GUI_MASTER_CNTL 0x146c +#define BRUSH_Y_X 0x1474 +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DP_BRUSH_FRGD_CLR 0x147c +#define BRUSH_DATA0 0x1480 +#define BRUSH_DATA1 0x1484 +#define DST_WIDTH_HEIGHT 0x1598 +#define CLR_CMP_CNTL 0x15c0 +#define CLR_CMP_CLR_SRC 0x15c4 +#define CLR_CMP_CLR_DST 0x15c8 +#define CLR_CMP_MSK 0x15cc +#define DP_SRC_FRGD_CLR 0x15d8 +#define DP_SRC_BKGD_CLR 0x15dc +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define DST_LINE_PATCOUNT 0x1608 +#define DP_CNTL 0x16c0 +#define DP_WRITE_MSK 0x16cc +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 +#define SC_TOP_LEFT 0x16ec +#define SC_BOTTOM_RIGHT 0x16f0 +#define SRC_SC_BOTTOM_RIGHT 0x16f4 +#define DSTCACHE_CTLSTAT 0x1714 +#define WAIT_UNTIL 0x1720 +#define RBBM_GUICNTL 0x172c #define VAP_VSM_VTX_ASSM 0x2184 +#define VAP_VTX_STATE_IND_REG_0 0x2188 +#define VAP_VTX_STATE_IND_REG_1 0x218c +#define VAP_VTX_STATE_IND_REG_2 0x2190 +#define VAP_VTX_STATE_IND_REG_3 0x2194 +#define VAP_VTX_STATE_IND_REG_4 0x2198 +#define VAP_VTX_STATE_IND_REG_5 0x219c +#define VAP_VTX_STATE_IND_REG_6 0x21a0 +#define VAP_VTX_STATE_IND_REG_7 0x21a4 +#define VAP_VTX_STATE_IND_REG_8 0x21a8 +#define VAP_VTX_STATE_IND_REG_9 0x21ac +#define VAP_VTX_STATE_IND_REG_10 0x21b0 +#define VAP_VTX_STATE_IND_REG_11 0x21b4 +#define VAP_VTX_STATE_IND_REG_12 0x21b8 +#define VAP_VTX_STATE_IND_REG_13 0x21bc +#define VAP_VTX_STATE_IND_REG_14 0x21c0 +#define VAP_VTX_STATE_IND_REG_15 0x21c4 +#define RB2D_DSTCACHE_CTLSTAT 0x342c +#define GB_VAP_RASTER_VTX_FMT_0 0x4000 +#define GB_VAP_RASTER_VTX_FMT_1 0x4004 +#define US_ALU_CONST_R_8 0x4c80 +#define US_ALU_CONST_G_8 0x4c84 +#define US_ALU_CONST_B_8 0x4c88 +#define US_ALU_CONST_A_8 0x4c8c +#define US_ALU_CONST_R_9 0x4c90 +#define US_ALU_CONST_G_9 0x4c94 +#define US_ALU_CONST_B_9 0x4c98 +#define US_ALU_CONST_A_9 0x4c9c +#define US_ALU_CONST_R_10 0x4ca0 +#define US_ALU_CONST_G_10 0x4ca4 +#define US_ALU_CONST_B_10 0x4ca8 +#define US_ALU_CONST_A_10 0x4cac +#define US_ALU_CONST_R_11 0x4cb0 +#define US_ALU_CONST_G_11 0x4cb4 +#define US_ALU_CONST_B_11 0x4cb8 +#define US_ALU_CONST_A_11 0x4cbc +#define US_ALU_CONST_R_12 0x4cc0 +#define US_ALU_CONST_G_12 0x4cc4 +#define US_ALU_CONST_B_12 0x4cc8 +#define US_ALU_CONST_A_12 0x4ccc +#define US_ALU_CONST_R_13 0x4cd0 +#define US_ALU_CONST_G_13 0x4cd4 +#define US_ALU_CONST_B_13 0x4cd8 +#define US_ALU_CONST_A_13 0x4cdc +#define US_ALU_CONST_R_14 0x4ce0 +#define US_ALU_CONST_G_14 0x4ce4 +#define US_ALU_CONST_B_14 0x4ce8 +#define US_ALU_CONST_A_14 0x4cec +#define US_ALU_CONST_R_15 0x4cf0 +#define US_ALU_CONST_G_15 0x4cf4 +#define US_ALU_CONST_B_15 0x4cf8 +#define US_ALU_CONST_A_15 0x4cfc +#define US_ALU_CONST_R_16 0x4d00 +#define US_ALU_CONST_G_16 0x4d04 +#define US_ALU_CONST_B_16 0x4d08 +#define US_ALU_CONST_A_16 0x4d0c +#define US_ALU_CONST_R_17 0x4d10 +#define US_ALU_CONST_G_17 0x4d14 +#define US_ALU_CONST_B_17 0x4d18 +#define US_ALU_CONST_A_17 0x4d1c +#define US_ALU_CONST_R_18 0x4d20 +#define US_ALU_CONST_G_18 0x4d24 +#define US_ALU_CONST_B_18 0x4d28 +#define US_ALU_CONST_A_18 0x4d2c +#define US_ALU_CONST_R_19 0x4d30 +#define US_ALU_CONST_G_19 0x4d34 +#define US_ALU_CONST_B_19 0x4d38 +#define US_ALU_CONST_A_19 0x4d3c +#define US_ALU_CONST_R_20 0x4d40 +#define US_ALU_CONST_G_20 0x4d44 +#define US_ALU_CONST_B_20 0x4d48 +#define US_ALU_CONST_A_20 0x4d4c +#define US_ALU_CONST_R_21 0x4d50 +#define US_ALU_CONST_G_21 0x4d54 +#define US_ALU_CONST_B_21 0x4d58 +#define US_ALU_CONST_A_21 0x4d5c +#define US_ALU_CONST_R_22 0x4d60 +#define US_ALU_CONST_G_22 0x4d64 +#define US_ALU_CONST_B_22 0x4d68 +#define US_ALU_CONST_A_22 0x4d6c +#define US_ALU_CONST_R_23 0x4d70 +#define US_ALU_CONST_G_23 0x4d74 +#define US_ALU_CONST_B_23 0x4d78 +#define US_ALU_CONST_A_23 0x4d7c +#define US_ALU_CONST_R_24 0x4d80 +#define US_ALU_CONST_G_24 0x4d84 +#define US_ALU_CONST_B_24 0x4d88 +#define US_ALU_CONST_A_24 0x4d8c +#define US_ALU_CONST_R_25 0x4d90 +#define US_ALU_CONST_G_25 0x4d94 +#define US_ALU_CONST_B_25 0x4d98 +#define US_ALU_CONST_A_25 0x4d9c +#define US_ALU_CONST_R_26 0x4da0 +#define US_ALU_CONST_G_26 0x4da4 +#define US_ALU_CONST_B_26 0x4da8 +#define US_ALU_CONST_A_26 0x4dac +#define US_ALU_CONST_R_27 0x4db0 +#define US_ALU_CONST_G_27 0x4db4 +#define US_ALU_CONST_B_27 0x4db8 +#define US_ALU_CONST_A_27 0x4dbc +#define US_ALU_CONST_R_28 0x4dc0 +#define US_ALU_CONST_G_28 0x4dc4 +#define US_ALU_CONST_B_28 0x4dc8 +#define US_ALU_CONST_A_28 0x4dcc +#define US_ALU_CONST_R_29 0x4dd0 +#define US_ALU_CONST_G_29 0x4dd4 +#define US_ALU_CONST_B_29 0x4dd8 +#define US_ALU_CONST_A_29 0x4ddc +#define US_ALU_CONST_R_30 0x4de0 +#define US_ALU_CONST_G_30 0x4de4 +#define US_ALU_CONST_B_30 0x4de8 +#define US_ALU_CONST_A_30 0x4dec +#define US_ALU_CONST_R_31 0x4df0 +#define US_ALU_CONST_G_31 0x4df4 +#define US_ALU_CONST_B_31 0x4df8 +#define US_ALU_CONST_A_31 0x4dfc +#define RB3D_DEBUG_CTL 0x4e48 +#define RB3D_CMASK_OFFSET0 0x4e54 +#define RB3D_CMASK_OFFSET1 0x4e58 +#define RB3D_CMASK_OFFSET2 0x4e5c +#define RB3D_CMASK_OFFSET3 0x4e60 +#define RB3D_CMASK_PITCH0 0x4e64 +#define RB3D_CMASK_PITCH1 0x4e68 +#define RB3D_CMASK_PITCH2 0x4e6c +#define RB3D_CMASK_PITCH3 0x4e70 +#define RB3D_CMASK_WRINDEX 0x4e74 +#define RB3D_CMASK_DWORD 0x4e78 +#define RB3D_CMASK_RDINDEX 0x4e7c diff --git a/drm/main.c b/drm/main.c index 4c455f0..065f944 100644 --- a/drm/main.c +++ b/drm/main.c @@ -55,15 +55,15 @@ int indirect_buffer() T0V(ZB_ZCACHE_CTLSTAT, 0x00000003); - T0V(RADEON_WAIT_UNTIL, 00020000); + T0V(WAIT_UNTIL, 0x00020000); T0V(GB_AA_CONFIG, 0x00000000); - T0V(RB3D_AARESOLVE_CTL, 00000000); + T0V(RB3D_AARESOLVE_CTL, 0x00000000); - T0V(RB3D_CCTL, 00004000); + T0V(RB3D_CCTL, 0x00004000); - T0V(RB3D_COLOROFFSET0, 00000000); + T0V(RB3D_COLOROFFSET0, 0x00000000); ib[ix++] = 0xc0001000; ib[ix++] = 0x0; diff --git a/regs/parse_packets.py b/regs/parse_packets.py index 29d7a2e..b827a0b 100644 --- a/regs/parse_packets.py +++ b/regs/parse_packets.py @@ -8,7 +8,7 @@ with open(sys.argv[1]) as f: ] undocumented_registers = { - 0x1720: "RADEON_WAIT_UNTIL", + 0x1720: "WAIT_UNTIL", 0x2184: "VAP_VSM_VTX_ASSM", }