From 94e9c0403da495d3ead108ad154a5fb51a6a6313 Mon Sep 17 00:00:00 2001 From: Zack Buhman Date: Mon, 13 Oct 2025 14:54:55 -0500 Subject: [PATCH] regs/bits: fix all parse errors --- regs/bits/cp_rb_cntl.txt | 2 +- regs/bits/gb_tile_config.txt | 4 +- regs/bits/vap_prog_stream_cntl.txt | 6 +-- regs/parse_bits.py | 46 +++++++++++++------ .../pvs_dual_math_instruction.txt | 2 +- .../pvs_opcode_and_destination_operand.txt | 0 ...vs_opcode_and_destination_operand_bits.txt | 0 .../{bits => pvs_bits}/pvs_source_operand.txt | 0 .../pvs_source_operand_bits.txt | 0 9 files changed, 39 insertions(+), 21 deletions(-) rename regs/{bits => pvs_bits}/pvs_dual_math_instruction.txt (96%) rename regs/{bits => pvs_bits}/pvs_opcode_and_destination_operand.txt (100%) rename regs/{bits => pvs_bits}/pvs_opcode_and_destination_operand_bits.txt (100%) rename regs/{bits => pvs_bits}/pvs_source_operand.txt (100%) rename regs/{bits => pvs_bits}/pvs_source_operand_bits.txt (100%) diff --git a/regs/bits/cp_rb_cntl.txt b/regs/bits/cp_rb_cntl.txt index 392ad0e..0ec8e11 100644 --- a/regs/bits/cp_rb_cntl.txt +++ b/regs/bits/cp_rb_cntl.txt @@ -35,7 +35,7 @@ RB_NO_UPDATE 27 0x0 Ring Buffer No Write to Read Pointer. The p POSSIBLE VALUES: 00 - Write to Host`s copy of Read Pointer in system memory. 01 - Do not write to Host`s copy of Read pointer. -RB_RPTR_WR_ENA 31 0bx0 Ring Buffer Read Pointer Write Transfer Enable. When +RB_RPTR_WR_ENA 31 0x0 Ring Buffer Read Pointer Write Transfer Enable. When set the contents of the CP_RB_RPTR_WR register is transferred to the active read pointer (CP_RB_RPTR) whenever the CP_RB_WPTR register is written. diff --git a/regs/bits/gb_tile_config.txt b/regs/bits/gb_tile_config.txt index 6e6c5fd..1a2ea04 100644 --- a/regs/bits/gb_tile_config.txt +++ b/regs/bits/gb_tile_config.txt @@ -14,8 +14,8 @@ PIPE_COUNT 3:1 0x0 Specifies the number of active pipes and c POSSIBLE VALUES: 00 - RV350 (1 pipe, 1 ctx) 03 - R300 (2 pipes, 1 ctx) - 06 – R420-3P (3 pipes, 1 ctx) - 07 – R420 (4 pipes, 1 ctx) + 06 - R420-3P (3 pipes, 1 ctx) + 07 - R420 (4 pipes, 1 ctx) TILE_SIZE 5:4 0x1 Specifies width & height (square), in pixels (only 16, 32 available). POSSIBLE VALUES: diff --git a/regs/bits/vap_prog_stream_cntl.txt b/regs/bits/vap_prog_stream_cntl.txt index 87f1dbb..4607654 100644 --- a/regs/bits/vap_prog_stream_cntl.txt +++ b/regs/bits/vap_prog_stream_cntl.txt @@ -43,6 +43,6 @@ NORMALIZE_0 15 0x0 Determines whether the fixed to floating p DATA_TYPE_1 19:16 0x0 Similar to DATA_TYPE_0 SKIP_DWORDS_1 23:20 0x0 See SKIP_DWORDS_0 DST_VEC_LOC_1 28:24 0x0 See DST_VEC_LOC_0 -LAST_VEC_1 29 0x0 See LAST_VEC_0 -SIGNED_1 30 0x0 See SIGNED_0 -NORMALIZE_1 31 0x0 See NORMALIZE_0 +LAST_VEC_1 29 0x0 See LAST_VEC_0 +SIGNED_1 30 0x0 See SIGNED_0 +NORMALIZE_1 31 0x0 See NORMALIZE_0 diff --git a/regs/parse_bits.py b/regs/parse_bits.py index 720b1c3..9eda9a2 100644 --- a/regs/parse_bits.py +++ b/regs/parse_bits.py @@ -5,26 +5,42 @@ from dataclasses import dataclass from pprint import pprint from collections import OrderedDict -def split_line_fields(line): - fields = [0, 17, 24, 32] +def split_line_fields(line, fields): a = line[fields[0]:fields[1]] b = line[fields[1]:fields[2]] c = line[fields[2]:fields[3]] d = line[fields[3]:] + assert a[-1] == ' ' + assert b[-1] == ' ' + assert c[-1] == ' ' or len(line) < fields[3] return a, b, c, d +def find_line_fields(line): + field_name_ix = line.index('Field Name') + bits_ix = line.index('Bits') + default_ix = line.index('Default') + description_ix = line.index('Description') + assert field_name_ix == 0 + assert bits_ix > field_name_ix + assert default_ix > bits_ix + assert description_ix > default_ix + return field_name_ix, bits_ix, default_ix, description_ix + def parse_file_fields(filename): with open(filename) as f: lines = f.read().split('\n') first, *rest = lines - a, b, c, d = split_line_fields(first) - assert a == 'Field Name ', a - assert b == 'Bits ', b - assert c == 'Default ', c + fields = find_line_fields(first) + a, b, c, d = split_line_fields(first, fields) + assert a.rstrip() == 'Field Name', a + assert b.rstrip() == 'Bits', b + assert c.rstrip() == 'Default', c assert d.rstrip() == 'Description', d for line in rest: - a, b, c, d = split_line_fields(line) + if not line.strip(): + continue + a, b, c, d = split_line_fields(line, fields) yield a.strip(), b.strip(), c.strip(), d.strip() def parse_bits(s): @@ -60,8 +76,6 @@ def aggregate(fields): nonlocal ix if ix + 1 >= len(fields): return - if not fields[ix+1][0] == '': - return if not fields[ix+1][3] == 'POSSIBLE VALUES:': return ix += 1 @@ -89,7 +103,7 @@ def aggregate(fields): ix += 1 def parse_possible_value_num(s): - num, description = s.split(' - ') + num, description = s.split(' - ', maxsplit=1) num = int(num, 10) if ": " in description: name, description = description.split(": ") @@ -99,17 +113,21 @@ def aggregate(fields): while ix < len(fields): field_name, bits, default, description = fields[ix] - description_lines = [description] - description_lines.extend(parse_description_lines()) + if description == 'POSSIBLE VALUES:': + description_lines = [] + ix -= 1 + else: + description_lines = [description] + description_lines.extend(parse_description_lines()) possible_values = OrderedDict( map(parse_possible_value_num, parse_possible_values()) ) - assert default.startswith('0x'), default + assert default.startswith('0x') or default == 'none', default yield Descriptor( field_name = field_name, bits = parse_bits(bits), - default = int(default, 16), + default = 0 if default == 'none' else int(default, 16), description = ' '.join(description_lines), possible_values = possible_values ) diff --git a/regs/bits/pvs_dual_math_instruction.txt b/regs/pvs_bits/pvs_dual_math_instruction.txt similarity index 96% rename from regs/bits/pvs_dual_math_instruction.txt rename to regs/pvs_bits/pvs_dual_math_instruction.txt index f876d92..08d27ac 100644 --- a/regs/bits/pvs_dual_math_instruction.txt +++ b/regs/pvs_bits/pvs_dual_math_instruction.txt @@ -1,4 +1,4 @@ -Field Name Bit(s) Description +Field Name Bits Description PVS_SRC_REG_TYPE 1:0 Defines the Memory Select (Register Type) for the Source Operand. See Below. PVS_DST_OPCODE_MSB 2 Math Opcode MSB for Dual Math Inst. PVS_SRC_ABS_XYZW 3 If set, Take absolute value of both components of Dual Math input vector. diff --git a/regs/bits/pvs_opcode_and_destination_operand.txt b/regs/pvs_bits/pvs_opcode_and_destination_operand.txt similarity index 100% rename from regs/bits/pvs_opcode_and_destination_operand.txt rename to regs/pvs_bits/pvs_opcode_and_destination_operand.txt diff --git a/regs/bits/pvs_opcode_and_destination_operand_bits.txt b/regs/pvs_bits/pvs_opcode_and_destination_operand_bits.txt similarity index 100% rename from regs/bits/pvs_opcode_and_destination_operand_bits.txt rename to regs/pvs_bits/pvs_opcode_and_destination_operand_bits.txt diff --git a/regs/bits/pvs_source_operand.txt b/regs/pvs_bits/pvs_source_operand.txt similarity index 100% rename from regs/bits/pvs_source_operand.txt rename to regs/pvs_bits/pvs_source_operand.txt diff --git a/regs/bits/pvs_source_operand_bits.txt b/regs/pvs_bits/pvs_source_operand_bits.txt similarity index 100% rename from regs/bits/pvs_source_operand_bits.txt rename to regs/pvs_bits/pvs_source_operand_bits.txt