pci: PIO command processor response
This commit is contained in:
parent
d026c323e6
commit
8c883d76f9
234
pci/3d_registers.h
Normal file
234
pci/3d_registers.h
Normal file
@ -0,0 +1,234 @@
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#define CP_CSQ2_STAT 0x7fc
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#define CP_CSQ_ADDR 0x7f0
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#define CP_CSQ_APER_INDIRECT 0x1300-0x13fc
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#define CP_CSQ_APER_INDIRECT2 0x1200-0x12fc
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#define CP_CSQ_APER_PRIMARY 0x1000-0x11fc
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#define CP_CSQ_AVAIL 0x7b8
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#define CP_CSQ_CNTL 0x740
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#define CP_CSQ_DATA 0x7f4
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#define CP_CSQ_MODE 0x744
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#define CP_CSQ_STAT 0x7f8
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#define CP_GUI_COMMAND 0x728
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#define CP_GUI_DST_ADDR 0x724
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#define CP_GUI_SRC_ADDR 0x720
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#define CP_IB2_BASE 0x730
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#define CP_IB2_BUFSZ 0x734
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#define CP_IB_BASE 0x738
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#define CP_IB_BUFSZ 0x73c
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#define CP_ME_CNTL 0x7d0
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#define CP_ME_RAM_ADDR 0x7d4
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#define CP_ME_RAM_DATAH 0x7dc
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#define CP_ME_RAM_DATAL 0x7e0
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#define CP_ME_RAM_RADDR 0x7d8
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#define CP_RB_BASE 0x700
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#define CP_RB_CNTL 0x704
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#define CP_RB_RPTR 0x710
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#define CP_RB_RPTR_ADDR 0x70c
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#define CP_RB_RPTR_WR 0x71c
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#define CP_RB_WPTR 0x714
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#define CP_RB_WPTR_DELAY 0x718
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#define CP_RESYNC_ADDR 0x778
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#define CP_RESYNC_DATA 0x77c
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#define CP_STAT 0x7c0
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#define CP_VID_COMMAND 0x7cc
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#define CP_VID_DST_ADDR 0x7c8
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#define CP_VID_SRC_ADDR 0x7c4
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#define CP_VP_ADDR_CNTL 0x7e8
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#define RB3D_AARESOLVE_CTL 0x4e88
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#define RB3D_AARESOLVE_OFFSET 0x4e80
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#define RB3D_AARESOLVE_PITCH 0x4e84
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#define RB3D_ABLENDCNTL 0x4e08
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#define RB3D_BLENDCNTL 0x4e04
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#define RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD 0x4ea4
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#define RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD 0x4ea0
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#define RB3D_CCTL 0x4e00
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#define RB3D_CLRCMP_CLR 0x4e20
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#define RB3D_CLRCMP_FLIPE 0x4e1c
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#define RB3D_CLRCMP_MSK 0x4e24
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#define RB3D_COLOR_CHANNEL_MASK 0x4e0c
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#define RB3D_COLOR_CLEAR_VALUE 0x4e14
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#define RB3D_COLOR_CLEAR_VALUE_AR 0x46c0
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#define RB3D_COLOR_CLEAR_VALUE_GB 0x46c4
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#define RB3D_CONSTANT_COLOR 0x4e10
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#define RB3D_CONSTANT_COLOR_AR 0x4ef8
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#define RB3D_CONSTANT_COLOR_GB 0x4efc
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#define RB3D_DITHER_CTL 0x4e50
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#define RB3D_DSTCACHE_CTLSTAT 0x4e4c
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#define RB3D_FIFO_SIZE 0x4ef4
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#define RB3D_ROPCNTL 0x4e18
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#define FG_ALPHA_FUNC 0x4bd4
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#define FG_ALPHA_VALUE 0x4be0
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#define FG_DEPTH_SRC 0x4bd8
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#define FG_FOG_BLEND 0x4bc0
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#define FG_FOG_COLOR_B 0x4bd0
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#define FG_FOG_COLOR_G 0x4bcc
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#define FG_FOG_COLOR_R 0x4bc8
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#define FG_FOG_FACTOR 0x4bc4
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#define GA_COLOR_CONTROL 0x4278
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#define GA_COLOR_CONTROL_PS3 0x4258
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#define GA_ENHANCE 0x4274
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#define GA_FIFO_CNTL 0x4270
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#define GA_FILL_A 0x422c
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#define GA_FILL_B 0x4228
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#define GA_FILL_R 0x4220
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#define GA_FOG_OFFSET 0x4298
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#define GA_FOG_SCALE 0x4294
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#define GA_IDLE 0x425c
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#define GA_LINE_CNTL 0x4234
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#define GA_LINE_S0 0x4264
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#define GA_LINE_S1 0x4268
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#define GA_LINE_STIPPLE_CONFIG 0x4238
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#define GA_LINE_STIPPLE_VALUE 0x4260
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#define GA_OFFSET 0x4290
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#define GA_POINT_MINMAX 0x4230
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#define GA_POINT_S0 0x4200
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#define GA_POINT_S1 0x4208
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#define GA_POINT_SIZE 0x421c
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#define GA_POINT_T0 0x4204
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#define GA_POINT_T1 0x420c
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#define GA_POLY_MODE 0x4288
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#define GA_ROUND_MODE 0x428c
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#define GA_SOLID_BA 0x4280
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#define GA_SOLID_RG 0x427c
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#define GA_TRIANGLE_STIPPLE 0x4214
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#define GA_US_VECTOR_DATA 0x4254
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#define GA_US_VECTOR_INDEX 0x4250
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#define GB_AA_CONFIG 0x4020
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#define GB_ENABLE 0x4008
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#define GB_FIFO_SIZE 0x4024
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#define GB_FIFO_SIZE1 0x4070
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#define GB_MSPOS0 0x4010
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#define GB_MSPOS1 0x4014
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#define GB_PIPE_SELECT 0x402c
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#define GB_SELECT 0x401c
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#define GB_TILE_CONFIG 0x4018
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#define GB_Z_PEQ_CONFIG 0x4028
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#define PS3_ENABLE 0x4118
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#define PS3_TEX_SOURCE 0x4120
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#define PS3_VTX_FMT 0x411c
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#define RS_COUNT 0x4300
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#define RS_INST_COUNT 0x4304
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#define SC_CLIP_0_A 0x43b0
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#define SC_CLIP_0_B 0x43b4
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#define SC_CLIP_1_A 0x43b8
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#define SC_CLIP_1_B 0x43bc
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#define SC_CLIP_2_A 0x43c0
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#define SC_CLIP_2_B 0x43c4
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#define SC_CLIP_3_A 0x43c8
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#define SC_CLIP_3_B 0x43cc
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#define SC_CLIP_RULE 0x43d0
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#define SC_EDGERULE 0x43a8
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#define SC_HYPERZ_EN 0x43a4
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#define SC_SCISSOR0 0x43e0
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#define SC_SCISSOR1 0x43e4
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#define SC_SCREENDOOR 0x43e8
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#define SU_CULL_MODE 0x42b8
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#define SU_DEPTH_OFFSET 0x42c4
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#define SU_DEPTH_SCALE 0x42c0
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#define SU_POLY_OFFSET_BACK_OFFSET 0x42b0
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#define SU_POLY_OFFSET_BACK_SCALE 0x42ac
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#define SU_POLY_OFFSET_ENABLE 0x42b4
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#define SU_POLY_OFFSET_FRONT_OFFSET 0x42a8
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#define SU_POLY_OFFSET_FRONT_SCALE 0x42a4
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#define SU_REG_DEST 0x42c8
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#define SU_TEX_WRAP 0x42a0
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#define SU_TEX_WRAP_PS3 0x4114
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#define TX_ENABLE 0x4104
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#define TX_FILTER4 0x4110
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#define TX_INVALTAGS 0x4100
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#define US_CODE_ADDR 0x4630
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#define US_CODE_OFFSET 0x4638
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#define US_CODE_RANGE 0x4634
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#define US_CONFIG 0x4600
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#define US_FC_BOOL_CONST 0x4620
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#define US_FC_CTRL 0x4624
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#define US_PIXSIZE 0x4604
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#define US_W_FMT 0x46b4
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#define VAP_ALT_NUM_VERTICES 0x2088
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#define VAP_CLIP_CNTL 0x221c
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#define VAP_CNTL 0x2080
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#define VAP_CNTL_STATUS 0x2140
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#define VAP_GB_HORZ_CLIP_ADJ 0x2228
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#define VAP_GB_HORZ_DISC_ADJ 0x222c
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#define VAP_GB_VERT_CLIP_ADJ 0x2220
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#define VAP_GB_VERT_DISC_ADJ 0x2224
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#define VAP_INDEX_OFFSET 0x208c
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#define VAP_OUT_VTX_FMT_0 0x2090
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#define VAP_OUT_VTX_FMT_1 0x2094
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#define VAP_PORT_DATA_IDX_128 0x20b8
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#define VAP_PSC_SGN_NORM_CNTL 0x21dc
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#define VAP_PVS_CODE_CNTL_0 0x22d0
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#define VAP_PVS_CODE_CNTL_1 0x22d8
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#define VAP_PVS_CONST_CNTL 0x22d4
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#define VAP_PVS_FLOW_CNTL_OPC 0x22dc
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#define VAP_PVS_STATE_FLUSH_REG 0x2284
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#define VAP_PVS_VECTOR_DATA_REG 0x2204
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#define VAP_PVS_VECTOR_DATA_REG_128 0x2208
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#define VAP_PVS_VECTOR_INDX_REG 0x2200
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#define VAP_PVS_VTX_TIMEOUT_REG 0x2288
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#define VAP_TEX_TO_COLOR_CNTL 0x2218
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#define VAP_VF_CNTL 0x2084
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#define VAP_VF_MAX_VTX_INDX 0x2134
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#define VAP_VF_MIN_VTX_INDX 0x2138
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#define VAP_VPORT_XOFFSET 0x1d9c,
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#define VAP_VPORT_XSCALE 0x1d98,
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#define VAP_VPORT_YOFFSET 0x1da4,
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#define VAP_VPORT_YSCALE 0x1da0,
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#define VAP_VPORT_ZOFFSET 0x1dac,
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#define VAP_VPORT_ZSCALE 0x1da8,
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#define VAP_VTE_CNTL 0x20b0
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#define VAP_VTX_NUM_ARRAYS 0x20c0
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#define VAP_VTX_SIZE 0x204b
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#define VAP_VTX_STATE_CNTL 0x2180
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#define VAP_VTX_ST_DISC_FOG 0x2424
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#define VAP_VTX_ST_EDGE_FLAGS 0x245c
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#define VAP_VTX_ST_END_OF_PKT 0x24ac
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#define VAP_VTX_ST_NORM_0_PKD 0x2498
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#define VAP_VTX_ST_NORM_0_X 0x2310
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#define VAP_VTX_ST_NORM_0_Y 0x2314
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#define VAP_VTX_ST_NORM_0_Z 0x2318
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#define VAP_VTX_ST_NORM_1_X 0x2450
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#define VAP_VTX_ST_NORM_1_Y 0x2454
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#define VAP_VTX_ST_NORM_1_Z 0x2458
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#define VAP_VTX_ST_PNT_SPRT_SZ 0x2420
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#define VAP_VTX_ST_POS_0_W_4 0x230c
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#define VAP_VTX_ST_POS_0_X_2 0x2490
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#define VAP_VTX_ST_POS_0_X_3 0x24a0
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#define VAP_VTX_ST_POS_0_X_4 0x2300
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#define VAP_VTX_ST_POS_0_Y_2 0x2494
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#define VAP_VTX_ST_POS_0_Y_3 0x24a4
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#define VAP_VTX_ST_POS_0_Y_4 0x2304
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#define VAP_VTX_ST_POS_0_Z_3 0x24a8
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#define VAP_VTX_ST_POS_0_Z_4 0x2308
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#define VAP_VTX_ST_POS_1_W 0x244c
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#define VAP_VTX_ST_POS_1_X 0x2440
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#define VAP_VTX_ST_POS_1_Y 0x2444
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#define VAP_VTX_ST_POS_1_Z 0x2448
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#define VAP_VTX_ST_PVMS 0x231c
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#define VAP_VTX_ST_SHININESS_0 0x2428
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#define VAP_VTX_ST_SHININESS_1 0x242c
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#define VAP_VTX_ST_USR_CLR_A 0x246c
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#define VAP_VTX_ST_USR_CLR_B 0x2468
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#define VAP_VTX_ST_USR_CLR_G 0x2464
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#define VAP_VTX_ST_USR_CLR_PKD 0x249c
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#define VAP_VTX_ST_USR_CLR_R 0x2460
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#define ZB_BW_CNTL 0x4f1c
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#define ZB_CNTL 0x4f00
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#define ZB_DEPTHCLEARVALUE 0x4f28
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#define ZB_DEPTHOFFSET 0x4f20
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#define ZB_DEPTHPITCH 0x4f24
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#define ZB_DEPTHXY_OFFSET 0x4f60
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#define ZB_FIFO_SIZE 0x4fd0
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#define ZB_FORMAT 0x4f10
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#define ZB_HIZ_DWORD 0x4f4c
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#define ZB_HIZ_OFFSET 0x4f44
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#define ZB_HIZ_PITCH 0x4f54
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#define ZB_HIZ_RDINDEX 0x4f50
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#define ZB_HIZ_WRINDEX 0x4f48
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#define ZB_STENCILREFMASK 0x4f08
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#define ZB_STENCILREFMASK_BF 0x4fd4
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#define ZB_ZCACHE_CTLSTAT 0x4f18
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#define ZB_ZPASS_ADDR 0x4f5c
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#define ZB_ZPASS_DATA 0x4f58
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#define ZB_ZSTENCILCNTL 0x4f04
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#define ZB_ZTOP 0x4f14
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BIN
pci/R520_cp.bin
Normal file
BIN
pci/R520_cp.bin
Normal file
Binary file not shown.
413
pci/main.c
413
pci/main.c
@ -4,6 +4,9 @@
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#include <linux/delay.h>
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#include <linux/aperture.h>
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#include "3d_registers.h"
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#include "undocumented_3d_registers.h"
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#define R500 "r500"
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static struct pci_device_id r500_id_table[] = {
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@ -59,6 +62,139 @@ static inline uint32_t rreg(void __iomem * rmmio, uint32_t reg)
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return readl(((void __iomem *)rmmio) + reg);
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}
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#define bswap32 __builtin_bswap32
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static const uint8_t _cp_data[] __attribute__((aligned (4))) = {
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0x00,0x00,0x00,0x00,0x42,0x00,0xe0,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0xe0,0x00,
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0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x99,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x9d,
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0x00,0x00,0x00,0x00,0x4a,0x55,0x4b,0x4a,0x00,0x00,0x00,0x00,0x4a,0x4a,0x44,0x67,
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0x00,0x00,0x00,0x00,0x55,0x52,0x6f,0x75,0x00,0x00,0x00,0x00,0x4a,0x7e,0x7d,0x65,
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0x00,0x00,0x00,0x00,0xe0,0xda,0xe6,0xf6,0x00,0x00,0x00,0x00,0x4a,0xc5,0x4a,0x4a,
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0x00,0x00,0x00,0x00,0xc8,0x82,0x82,0x82,0x00,0x00,0x00,0x00,0xbf,0x4a,0xcf,0xc1,
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0x00,0x00,0x00,0x00,0x87,0xb0,0x4a,0xd5,0x00,0x00,0x00,0x00,0xb5,0x83,0x83,0x83,
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0x00,0x00,0x00,0x00,0x4a,0x0f,0x85,0xba,0x00,0x00,0x00,0x04,0x00,0x0c,0xa0,0x00,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x12,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0xb4,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x14,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0xb6,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x16,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x54,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x18,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x55,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x1a,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x56,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x1c,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x57,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x1e,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x24,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x20,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x25,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x22,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x30,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x24,0x00,0x00,0x00,0x04,0x00,0x00,0xf0,0xc0,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x26,0x00,0x00,0x00,0x04,0x00,0x00,0xf0,0xc1,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x28,0x00,0x00,0x00,0x04,0x00,0x00,0xe0,0x00,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x2a,0x00,0x00,0x00,0x04,0x00,0x00,0xe0,0x00,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x2c,0x00,0x00,0x00,0x04,0x00,0x00,0xe0,0x00,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x2e,0x00,0x00,0x00,0x04,0x00,0x00,0xe0,0x00,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x30,0x00,0x00,0x00,0x04,0x00,0x00,0xe0,0x00,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x32,0x00,0x00,0x00,0x04,0x00,0x00,0xf1,0x80,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x34,0x00,0x00,0x00,0x04,0x00,0x00,0xf3,0x93,
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0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x36,0x00,0x00,0x00,0x04,0x00,0x00,0xf3,0x8a,
|
||||
0x00,0x00,0x00,0x38,0x00,0x0d,0x00,0x38,0x00,0x00,0x00,0x04,0x00,0x00,0xf3,0x8e,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x21,0x00,0x00,0x00,0x04,0x01,0x40,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x43,0x00,0x00,0x00,0x04,0x00,0xcc,0xe8,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x1b,0x00,0x01,0x00,0x00,0x00,0x04,0x08,0x00,0x48,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x1b,0x00,0x01,0x00,0x00,0x00,0x04,0x08,0x00,0x48,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x1b,0x00,0x01,0x00,0x00,0x00,0x04,0x08,0x00,0x48,0x00,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x3a,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x04,0x20,0x00,0x45,0x1d,0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x80,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0c,0xe5,0x81,0x00,0x00,0x00,0x04,0x08,0x00,0x45,0x80,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0c,0xe5,0x81,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x47,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x00,0x00,0x00,0x00,0x04,0x00,0x0c,0x20,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x0e,0x00,0x00,0x00,0x04,0x00,0x03,0x20,0x00,
|
||||
0x00,0x00,0x00,0x28,0x00,0x02,0x20,0x51,0x00,0x00,0x00,0x24,0x00,0x00,0x00,0x51,
|
||||
0x00,0x00,0x00,0x04,0x08,0x00,0x45,0x0f,0x00,0x00,0x00,0x08,0x00,0x00,0xa0,0x4b,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x65,0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x66,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x52,0x00,0x00,0x00,0x04,0x03,0xcc,0xa5,0xb4,
|
||||
0x00,0x00,0x00,0x04,0x05,0x43,0x20,0x00,0x00,0x00,0x00,0x04,0x00,0x02,0x20,0x00,
|
||||
0x00,0x00,0x00,0x30,0x4c,0xcc,0xe0,0x5e,0x00,0x00,0x00,0x04,0x08,0x27,0x45,0x65,
|
||||
0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x5e,0x00,0x00,0x00,0x04,0x08,0x00,0x45,0x64,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x66,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x55,
|
||||
0x00,0x00,0x00,0x10,0x00,0x80,0x20,0x61,0x00,0x00,0x00,0x04,0x00,0x20,0x20,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x1b,0x00,0xff,0x00,0x00,0x00,0x10,0x01,0x00,0x00,0x64,
|
||||
0x00,0x00,0x00,0x04,0x00,0x1f,0x20,0x00,0x00,0x00,0x00,0x04,0x00,0x1c,0x00,0xff,
|
||||
0x00,0x00,0x00,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x72,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x55,0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x76,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x77,0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x0e,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x0f,0x00,0x00,0x00,0x04,0x01,0x40,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x69,0x00,0x00,0x00,0xc2,0x00,0xc0,0xe5,0xf9,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x69,0x00,0x00,0x00,0x04,0x00,0x14,0xe5,0x0e,
|
||||
0x00,0x00,0x00,0x04,0x00,0x40,0xe5,0x0f,0x00,0x00,0x00,0x08,0x00,0xc0,0x00,0x6c,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x70,0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x71,
|
||||
0x00,0x00,0x00,0x0c,0x00,0x00,0xe5,0x72,0x00,0x00,0x00,0x04,0x00,0x00,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x04,0x01,0x40,0xa0,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0x68,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0c,0x20,0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x76,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0b,0x00,0x00,0x00,0x00,0x00,0x04,0x18,0xc0,0xe5,0x62,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x78,0x00,0x00,0x00,0x08,0x00,0xc0,0x00,0x77,
|
||||
0x00,0x00,0x00,0x04,0x00,0x07,0x00,0xc7,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x80,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe5,0xbb,0x00,0x00,0x00,0x00,0x00,0x00,0xe5,0xbc,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xa0,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x21,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0x21,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0xe8,0x2e,0x00,0x00,0x00,0x04,0x02,0xcc,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x0c,0xe1,0xcc,
|
||||
0x00,0x00,0x00,0x04,0x05,0x0d,0xe1,0xcd,0x00,0x00,0x00,0x04,0x00,0x40,0x00,0x00,
|
||||
0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x8f,0x00,0x00,0x00,0x04,0x00,0xc0,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x8c,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x91,
|
||||
0x00,0x00,0x00,0x00,0x42,0x00,0xe0,0x00,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x98,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0c,0xa0,0x00,0x00,0x00,0x00,0x04,0x00,0x14,0x00,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0c,0x20,0x00,0x00,0x00,0x00,0x04,0x00,0x16,0x00,0x00,
|
||||
0x00,0x00,0x00,0x04,0x70,0x0c,0xe0,0x00,0x00,0x00,0x00,0x08,0x00,0x14,0x00,0x94,
|
||||
0x00,0x00,0x00,0x00,0x40,0x00,0xe0,0x00,0x00,0x00,0x00,0x04,0x02,0x40,0x00,0x00,
|
||||
0x00,0x00,0x00,0x04,0x40,0x0e,0xe0,0x00,0x00,0x00,0x00,0x04,0x02,0x40,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x40,0x00,0xe0,0x00,0x00,0x00,0x00,0x04,0x00,0x0c,0x20,0x00,
|
||||
0x00,0x00,0x00,0x04,0x02,0x40,0xe5,0x1b,0x00,0x00,0x00,0x05,0x00,0x80,0xe5,0x0a,
|
||||
0x00,0x00,0x00,0x05,0x00,0x80,0xe5,0x0b,0x00,0x00,0x00,0x04,0x00,0x22,0x00,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x07,0x00,0xc7,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0xa4,
|
||||
0x00,0x00,0x00,0x05,0x00,0x80,0xe5,0xbd,0x00,0x00,0x00,0x05,0x00,0x00,0xe5,0xbb,
|
||||
0x00,0x00,0x00,0x05,0x00,0x80,0xe5,0xbc,0x00,0x00,0x00,0x04,0x00,0x21,0x00,0x00,
|
||||
0x00,0x00,0x00,0x04,0x02,0x80,0x00,0x00,0x00,0x00,0x00,0x18,0x00,0xc0,0x00,0xab,
|
||||
0x00,0x00,0x00,0x40,0x41,0x80,0xe0,0x00,0x00,0x00,0x00,0x24,0x00,0x00,0x00,0xad,
|
||||
0x00,0x00,0x00,0x0c,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x0c,0x01,0x00,0xe5,0x1d,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0x45,0xbb,0x00,0x00,0x00,0x08,0x00,0x00,0x80,0xa7,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xf3,0xce,0x00,0x00,0x00,0x04,0x01,0x40,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0xcc,0x20,0x00,0x00,0x00,0x00,0x40,0x08,0xc0,0x53,0xcf,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0xf3,0xd2,
|
||||
0x00,0x00,0x00,0x04,0x01,0x40,0xa0,0x00,0x00,0x00,0x00,0x04,0x00,0xcc,0x20,0x00,
|
||||
0x00,0x00,0x00,0x40,0x08,0xc0,0x53,0xd3,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xf3,0x9d,0x00,0x00,0x00,0x04,0x01,0x40,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0xcc,0x20,0x00,0x00,0x00,0x00,0x40,0x08,0xc0,0x53,0x9e,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x04,0x03,0xc0,0x08,0x30,
|
||||
0x00,0x00,0x00,0x00,0x42,0x00,0xe0,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x04,0x20,0x00,0x45,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0xe5,0xe1,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x04,0x00,0x07,0x00,0xc4,
|
||||
0x00,0x00,0x00,0x00,0x08,0x00,0xe3,0x94,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0xc4,0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0xc5,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe8,0xc6,0x00,0x00,0x00,0x04,0x00,0x00,0xe9,0x28,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe9,0x29,0x00,0x00,0x00,0x04,0x00,0x00,0xe9,0x2a,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0xc8,0x00,0x00,0x00,0x04,0x00,0x00,0xe9,0x28,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe9,0x29,0x00,0x00,0x00,0x04,0x00,0x00,0xe9,0x2a,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0xcf,0x00,0x00,0x00,0x00,0xde,0xad,0xbe,0xef,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x16,0x00,0x00,0x00,0x04,0x00,0x07,0x00,0xd3,
|
||||
0x00,0x00,0x00,0x04,0x08,0x00,0x50,0xe7,0x00,0x00,0x00,0x04,0x00,0x07,0x00,0xd4,
|
||||
0x00,0x00,0x00,0x04,0x08,0x00,0x40,0x1c,0x00,0x00,0x00,0x00,0x00,0x00,0xe0,0x1d,
|
||||
0x00,0x00,0x00,0x04,0x02,0xc0,0x20,0x00,0x00,0x00,0x00,0x04,0x00,0x06,0x00,0x00,
|
||||
0x00,0x00,0x00,0x34,0x00,0x00,0x00,0xde,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0xdb,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0xc0,0x00,0xe0,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x00,0xe1,0xcc,0x00,0x00,0x00,0x04,0x05,0x00,0xe1,0xcd,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0c,0xa0,0x00,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0xe5,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0xe1,0x00,0x00,0x00,0x00,0x00,0x00,0xa0,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x19,0xe1,0xcc,0x00,0x00,0x00,0x04,0x00,0x1b,0x00,0x01,
|
||||
0x00,0x00,0x00,0x04,0x05,0x00,0xa0,0x00,0x00,0x00,0x00,0x04,0x08,0x00,0x41,0xcd,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0c,0xa0,0x00,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0xfb,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x4a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x04,0x00,0x0c,0x20,0x00,0x00,0x00,0x00,0x04,0x00,0x1d,0x00,0x18,
|
||||
0x00,0x00,0x00,0x04,0x00,0x1a,0x00,0x01,0x00,0x00,0x00,0x34,0x00,0x00,0x00,0xfb,
|
||||
0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x4a,0x00,0x00,0x00,0x08,0x05,0x00,0xa0,0x4a,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
|
||||
};
|
||||
|
||||
/* This function is called by the kernel */
|
||||
static int r500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
@ -67,7 +203,6 @@ static int r500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
pci_read_config_word(pdev, PCI_DEVICE_ID, &device);
|
||||
printk(KERN_INFO "[r500] VENDOR_ID: %04x DEVICE_ID: %04x\n", vendor, device);
|
||||
|
||||
struct resource mem;
|
||||
int ret;
|
||||
|
||||
ret = aperture_remove_conflicting_pci_devices(pdev, "R500");
|
||||
@ -76,22 +211,288 @@ static int r500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
|
||||
ret = pci_enable_device(pdev);
|
||||
if (ret)
|
||||
goto err_free;
|
||||
return ret;
|
||||
|
||||
|
||||
if (!request_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0), "R500")) {
|
||||
printk(KERN_INFO "[r500] !request_mem_region resource 0\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
if (!request_mem_region(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2), "R500")) {
|
||||
printk(KERN_INFO "[r500] !request_mem_region resource 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
resource_size_t rmmio_base = pci_resource_start(pdev, 2);
|
||||
resource_size_t rmmio_size = pci_resource_len(pdev, 2);
|
||||
printk(KERN_INFO "[r500] rmmio base: %08x ; rmmio size: %08x\n", rmmio_base, rmmio_size);
|
||||
|
||||
void __iomem * rmmio = ioremap(rmmio_base, rmmio_size);
|
||||
printk(KERN_INFO "[r500] rmmio base: %08x ; rmmio size: %08x\n", rmmio_base, rmmio_size);
|
||||
|
||||
uint32_t value1 = rreg(rmmio, 0x6080);
|
||||
printk(KERN_INFO "[r500] D1CRTC_CONTROL %08x\n", value1);
|
||||
uint32_t value2 = rreg(rmmio, 0x6880);
|
||||
uint32_t value2 = rreg(rmmio, 0x6080 + 0x800);
|
||||
printk(KERN_INFO "[r500] D2CRTC_CONTROL %08x\n", value2);
|
||||
|
||||
wreg(rmmio, 0x6080, 1);
|
||||
{
|
||||
uint32_t value1 = rreg(rmmio, 0x6110);
|
||||
printk(KERN_INFO "[r500] D1GRPH_PRIMARY_SURFACE_ADDRESS %08x\n", value1);
|
||||
uint32_t value2 = rreg(rmmio, 0x6110 + 0x800);
|
||||
printk(KERN_INFO "[r500] D2GRPH_PRIMARY_SURFACE_ADDRESS %08x\n", value2);
|
||||
|
||||
uint32_t value3 = rreg(rmmio, 0x6118);
|
||||
printk(KERN_INFO "[r500] D1GRPH_SECONDARY_SURFACE_ADDRESS %08x\n", value3);
|
||||
uint32_t value4 = rreg(rmmio, 0x6118 + 0x800);
|
||||
printk(KERN_INFO "[r500] D2GRPH_SECONDARY_SURFACE_ADDRESS %08x\n", value4);
|
||||
|
||||
//wreg(rmmio, 0x6110, 0xe0100000);
|
||||
//wreg(rmmio, 0x6110 + 0x800, 0xe0100000);
|
||||
|
||||
//wreg(rmmio, 0x6118, 0xe0100000);
|
||||
//wreg(rmmio, 0x6118 + 0x800, 0xe0100000);
|
||||
}
|
||||
|
||||
uint32_t memsize = rreg(rmmio, 0xf8);
|
||||
printk(KERN_INFO "[r500] CONFIG_MEMSIZE %08x\n", memsize);
|
||||
|
||||
uint32_t config_cntl = rreg(rmmio, 0xe0);
|
||||
printk(KERN_INFO "[r500] CONFIG_CNTL %08x\n", config_cntl);
|
||||
config_cntl |= (1 << 9); // VGA DISABLE
|
||||
wreg(rmmio, 0xe0, config_cntl);
|
||||
|
||||
// atombios_crtc.c avivo_crtc_do_set_base
|
||||
|
||||
uint32_t d1vga_control = rreg(rmmio, 0x330);
|
||||
printk(KERN_INFO "[r500] D1VGA_CONTROL %08x\n", d1vga_control);
|
||||
wreg(rmmio, 0x330, 0);
|
||||
|
||||
uint32_t d2vga_control = rreg(rmmio, 0x338);
|
||||
printk(KERN_INFO "[r500] D2VGA_CONTROL %08x\n", d2vga_control);
|
||||
wreg(rmmio, 0x338, 0);
|
||||
|
||||
uint32_t d1grph_x_start = rreg(rmmio, 0x612c);
|
||||
printk(KERN_INFO "[r500] D1GRPH_X_START %08x\n", d1grph_x_start);
|
||||
wreg(rmmio, 0x612c, 0);
|
||||
|
||||
uint32_t d1grph_y_start = rreg(rmmio, 0x6130);
|
||||
printk(KERN_INFO "[r500] D1GRPH_Y_START %08x\n", d1grph_y_start);
|
||||
wreg(rmmio, 0x6130, 0);
|
||||
|
||||
uint32_t d1grph_x_end = rreg(rmmio, 0x6134);
|
||||
printk(KERN_INFO "[r500] D1GRPH_X_END %08x\n", d1grph_x_end);
|
||||
wreg(rmmio, 0x6134, 1600);
|
||||
|
||||
uint32_t d1grph_y_end = rreg(rmmio, 0x6138);
|
||||
printk(KERN_INFO "[r500] D1GRPH_Y_END %08x\n", d1grph_y_end);
|
||||
wreg(rmmio, 0x6138, 1200);
|
||||
|
||||
uint32_t d1grph_pitch = rreg(rmmio, 0x6120);
|
||||
printk(KERN_INFO "[r500] D1GRPH_PITCH %08x\n", d1grph_pitch);
|
||||
wreg(rmmio, 0x6120, 1600);
|
||||
|
||||
uint32_t d1grph_enable = rreg(rmmio, 0x6100);
|
||||
printk(KERN_INFO "[r500] D1GRPH_ENABLE %08x\n", d1grph_enable);
|
||||
wreg(rmmio, 0x6100, 1);
|
||||
|
||||
void __iomem * fb;
|
||||
{
|
||||
resource_size_t fb_base = pci_resource_start(pdev, 0);
|
||||
uint32_t fb_size = 64 * 1024 * 1024;
|
||||
fb = ioremap(fb_base, fb_size);
|
||||
if (!fb_base) {
|
||||
printk(KERN_INFO "[r500] could not map fb\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for (int y = 0; y < 1200; y++) {
|
||||
for (int x = 0; x < 1600; x++) {
|
||||
int red = x % 256;
|
||||
int green = y % 256;
|
||||
|
||||
//wreg(fb, 0x00100000 + y * 1600 + x, red << 16 | green << 8);
|
||||
wreg(fb, 0x00100000 + (y * 1600 + x) * 4, red << 16 | green << 8);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// r100.c r100_cp_init
|
||||
|
||||
wreg(rmmio, CP_ME_RAM_ADDR, 0);
|
||||
const uint32_t * cp_data = (const uint32_t *)_cp_data;
|
||||
for (int i = 0; i < (sizeof (_cp_data)) / (4 * 2); i++) {
|
||||
wreg(rmmio, CP_ME_RAM_DATAH, bswap32(cp_data[i * 2 + 0]));
|
||||
wreg(rmmio, CP_ME_RAM_DATAL, bswap32(cp_data[i * 2 + 1]));
|
||||
}
|
||||
mb();
|
||||
mdelay(500);
|
||||
|
||||
// cp
|
||||
|
||||
// 1) Write CP_CSQ_CNTL and CP_CSQ_MODE to zero, effectively disabling the CP.
|
||||
wreg(rmmio, CP_CSQ_CNTL, 0);
|
||||
wreg(rmmio, CP_CSQ_MODE, 0);
|
||||
// 2) Write to the proper RBBM register to assert and then de-assert the Soft Reset signal to the CP.
|
||||
wreg(rmmio, RBBM_SOFT_RESET, RBBM_SOFT_RESET_CP);
|
||||
rreg(rmmio, RBBM_SOFT_RESET);
|
||||
mdelay(500);
|
||||
wreg(rmmio, RBBM_SOFT_RESET, 0);
|
||||
mdelay(1);
|
||||
// 3) Set the RB_RPTR_WR_ENA bit to enable writing of the RPTR if desired not to start from the
|
||||
// beginning of the buffer.
|
||||
uint32_t tmp = rreg(rmmio, CP_RB_CNTL);
|
||||
wreg(rmmio, CP_RB_CNTL, tmp | (1 << 31)); // RB_RPTR_WR_ENA
|
||||
// 4) Write the CP_RB_RPTR_WR register if it is desired not to start at the beginning of the buffer.
|
||||
wreg(rmmio, CP_RB_RPTR_WR, 0);
|
||||
// 5) Write CP_RB_WPTR, to make it match the RPTR, causing the ring buffer to appear to be empty.
|
||||
wreg(rmmio, CP_RB_WPTR, 0);
|
||||
// 6) Clear the RB_RPTR_WR_ENA bit if no further writes of the RPTR are desired.
|
||||
wreg(rmmio, CP_RB_CNTL, tmp);
|
||||
// 7) Write CP_CSQ_CNTL or CP_CSQ_MODE to set the mode back to whatever you want.
|
||||
wreg(rmmio, CP_CSQ_CNTL, 1 << 28); // Primary PIO, Indirect Disabled
|
||||
wreg(rmmio, CP_CSQ_MODE, 0); // Primary PIO, Indirect Disabled
|
||||
|
||||
//pci_set_master(pdev);
|
||||
|
||||
uint32_t scratch;
|
||||
|
||||
scratch = rreg(rmmio, SCRATCH_REG0);
|
||||
printk(KERN_INFO "[r500] SCRATCH_REG0 0 %08x\n", scratch);
|
||||
|
||||
wreg(rmmio, SCRATCH_REG0, 0xEEAABBCC);
|
||||
scratch = rreg(rmmio, SCRATCH_REG0);
|
||||
printk(KERN_INFO "[r500] SCRATCH_REG0 1 %08x\n", scratch);
|
||||
|
||||
#define PACKET_TYPE_0(base, count) \
|
||||
(((base) >> 2) | ((count) << 16))
|
||||
|
||||
wreg(rmmio, 0x1000, PACKET_TYPE_0(SCRATCH_REG0, 0));
|
||||
mb();
|
||||
wreg(rmmio, 0x1000, 0xdeadbeef);
|
||||
mb();
|
||||
mdelay(1);
|
||||
|
||||
scratch = rreg(rmmio, SCRATCH_REG0);
|
||||
printk(KERN_INFO "[r500] SCRATCH_REG0 2 %08x\n", scratch);
|
||||
|
||||
if (0) {
|
||||
wreg(rmmio, CP_CSQ_CNTL, 1); // Primary PIO, Indirect Disabled
|
||||
wreg(rmmio, CP_CSQ_MODE, (1 << 30) | (1 << 31)); // Primary PIO, Indirect Disabled
|
||||
|
||||
///
|
||||
wreg(rmmio, CP_RB_BASE, 0); // start of framebuffer memory
|
||||
uint32_t cp_rb_cntl = ( (1 << 27) // RB_NO_UPDATE
|
||||
);
|
||||
wreg(rmmio, CP_RB_CNTL, cp_rb_cntl); // start of framebuffer memory
|
||||
wreg(rmmio, CP_RB_RPTR_ADDR, 0);
|
||||
udelay(10);
|
||||
wreg(rmmio, CP_RB_WPTR_DELAY, 0);
|
||||
wreg(rmmio, CP_CSQ_CNTL, 2 << 28);
|
||||
|
||||
volatile uint32_t * ring = (volatile uint32_t *)fb;
|
||||
ring[0] = PACKET_TYPE_0(0x1724, 0); // ISYNC_CNTL
|
||||
ring[1] = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5);
|
||||
mb();
|
||||
wreg(rmmio, CP_RB_WPTR, 2);
|
||||
(void)rreg(rmmio, CP_RB_WPTR);
|
||||
|
||||
ring[2] = PACKET_TYPE_0(SCRATCH_REG0, 0);
|
||||
ring[3] = 0xdeadbeef;
|
||||
mb();
|
||||
wreg(rmmio, CP_RB_WPTR, 4);
|
||||
(void)rreg(rmmio, CP_RB_WPTR);
|
||||
|
||||
udelay(500);
|
||||
}
|
||||
|
||||
uint32_t scratch_reg0_2 = rreg(rmmio, SCRATCH_REG0);
|
||||
printk(KERN_INFO "[r500] SCRATCH_REG0 2 %08x\n", scratch_reg0_2);
|
||||
|
||||
if (1) {
|
||||
// GB_PIPE_SELECT
|
||||
// GB_TILE_CONFIG
|
||||
// GA_SOFT_RESET
|
||||
uint32_t gb_pipe_select = rreg(rmmio, GB_PIPE_SELECT);
|
||||
printk(KERN_INFO "[r500] GB_PIPE_SELECT %08x\n", gb_pipe_select);
|
||||
uint32_t gb_tile_config = rreg(rmmio, GB_TILE_CONFIG);
|
||||
printk(KERN_INFO "[r500] GB_TILE_CONFIG %08x\n", gb_tile_config);
|
||||
|
||||
uint32_t cp_csq_cntl = rreg(rmmio, CP_CSQ_CNTL);
|
||||
printk(KERN_INFO "[r500] CP_CSQ_CNTL %08x\n", cp_csq_cntl);
|
||||
uint32_t cp_csq_mode = rreg(rmmio, CP_CSQ_MODE);
|
||||
printk(KERN_INFO "[r500] CP_CSQ_MODE %08x\n", cp_csq_mode);
|
||||
uint32_t cp_csq_stat = rreg(rmmio, CP_CSQ_STAT);
|
||||
printk(KERN_INFO "[r500] CP_CSQ_STAT %08x\n", cp_csq_stat);
|
||||
uint32_t cp_csq2_stat = rreg(rmmio, CP_CSQ2_STAT);
|
||||
printk(KERN_INFO "[r500] CP_CSQ2_STAT %08x\n", cp_csq2_stat);
|
||||
uint32_t cp_csq_avail = rreg(rmmio, CP_CSQ_AVAIL);
|
||||
printk(KERN_INFO "[r500] CP_CSQ_AVAIL %08x\n", cp_csq_avail);
|
||||
|
||||
uint32_t cp_rb_rptr = rreg(rmmio, CP_RB_RPTR);
|
||||
printk(KERN_INFO "[r500] CP_RB_RPTR %08x\n", cp_rb_rptr);
|
||||
uint32_t cp_rb_wptr = rreg(rmmio, CP_RB_WPTR);
|
||||
printk(KERN_INFO "[r500] CP_RB_WPTR %08x\n", cp_rb_wptr);
|
||||
}
|
||||
|
||||
if (0) {
|
||||
wreg(rmmio, 0x1000, PACKET_TYPE_0(SCRATCH_REG0, 0));
|
||||
wreg(rmmio, 0x1004, 0xdeadbeef);
|
||||
for (int i = 0; i < 14; i++)
|
||||
wreg(rmmio, 0x1008 + i * 4, 0x80000000);
|
||||
mb();
|
||||
|
||||
mdelay(500);
|
||||
|
||||
uint32_t scratch_reg02 = rreg(rmmio, SCRATCH_REG0);
|
||||
printk(KERN_INFO "[r500] SCRATCH_REG0 2 %08x\n", scratch_reg02);
|
||||
|
||||
wreg(rmmio, CP_RB_WPTR, 16);
|
||||
(void)rreg(rmmio, CP_RB_WPTR);
|
||||
|
||||
mdelay(500);
|
||||
|
||||
uint32_t scratch_reg03 = rreg(rmmio, SCRATCH_REG0);
|
||||
printk(KERN_INFO "[r500] SCRATCH_REG0 3 %08x\n", scratch_reg03);
|
||||
}
|
||||
|
||||
if (0) {
|
||||
uint32_t tmp;
|
||||
tmp = rreg(rmmio, 0xf8);
|
||||
printk(KERN_INFO "CONFIG_MEMSIZE 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x4);
|
||||
printk(KERN_INFO "MC_FB_LOCATION 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x4c);
|
||||
printk(KERN_INFO "BUS_CNTL 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x5);
|
||||
printk(KERN_INFO "MC_AGP_LOCATION 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x6);
|
||||
printk(KERN_INFO "AGP_BASE 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x130);
|
||||
printk(KERN_INFO "HOST_PATH_CNTL 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x1d0);
|
||||
printk(KERN_INFO "AIC_CTRL 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x1dc);
|
||||
printk(KERN_INFO "AIC_LO_ADDR 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x1e0);
|
||||
printk(KERN_INFO "AIC_HI_ADDR 0x%08x\n", tmp);
|
||||
tmp = rreg(rmmio, 0x01e4);
|
||||
printk(KERN_INFO "AIC_TLB_ADDR 0x%08x\n", tmp);
|
||||
}
|
||||
|
||||
|
||||
// write packet0
|
||||
|
||||
// align to 16 dwords
|
||||
|
||||
// write wptr
|
||||
|
||||
// check reg0
|
||||
|
||||
iounmap(fb);
|
||||
iounmap(rmmio);
|
||||
release_mem_region(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
|
||||
release_mem_region(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
|
||||
|
||||
err_free:
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
18
pci/undocumented_3d_registers.h
Normal file
18
pci/undocumented_3d_registers.h
Normal file
@ -0,0 +1,18 @@
|
||||
#define RBBM_SOFT_RESET 0x00f0
|
||||
#define RBBM_SOFT_RESET_CP (1 << 0)
|
||||
#define RBBM_SOFT_RESET_HI (1 << 1)
|
||||
#define RBBM_SOFT_RESET_VAP (1 << 2)
|
||||
#define RBBM_SOFT_RESET_RE (1 << 3)
|
||||
#define RBBM_SOFT_RESET_PP (1 << 4)
|
||||
#define RBBM_SOFT_RESET_E2 (1 << 5)
|
||||
#define RBBM_SOFT_RESET_RB (1 << 6)
|
||||
#define RBBM_SOFT_RESET_HDP (1 << 7)
|
||||
#define RBBM_SOFT_RESET_MC (1 << 8)
|
||||
#define RBBM_SOFT_RESET_AIC (1 << 9)
|
||||
#define RBBM_SOFT_RESET_VIP (1 << 10)
|
||||
#define RBBM_SOFT_RESET_DISP (1 << 11)
|
||||
#define RBBM_SOFT_RESET_CG (1 << 12)
|
||||
#define RBBM_SOFT_RESET_GA (1 << 13)
|
||||
#define RBBM_SOFT_RESET_IDCT (1 << 14)
|
||||
|
||||
#define SCRATCH_REG0 0x15e0
|
||||
9
regs/3d_registers.py
Normal file
9
regs/3d_registers.py
Normal file
@ -0,0 +1,9 @@
|
||||
with open('3d_registers.txt') as f:
|
||||
lines = f.read().split('\n')
|
||||
|
||||
for line in lines:
|
||||
if not line.strip():
|
||||
continue
|
||||
reg_name = line.split(':')[1].split(' ')[0]
|
||||
reg_value = line.split('MMReg:')[1]
|
||||
print("#define", reg_name, reg_value)
|
||||
Loading…
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Reference in New Issue
Block a user