us_disassemble2: invent a better fragment shader syntax
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0879b6b8f1
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59b6b2a0d2
@ -64,7 +64,7 @@ ADDR2_REL 29 0x0 Specifies whether the loop register is added to
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01 - RELATIVE: Add aL before lookup.
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SRCP_OP 31:30 0x0 Specifies how the pre-subtract value (SRCP) is computed.
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POSSIBLE VALUES:
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00 - 1.0-2.0*A0
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01 - A1-A0
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02 - A1+A0
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03 - 1.0-A0
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00 - neg2: 1.0-2.0*A0
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01 - sub: A1-A0
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02 - add: A1+A0
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03 - neg: 1.0-A0
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@ -65,7 +65,7 @@ ADDR2_REL 29 0x0 Specifies whether the loop register is added to
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SRCP_OP 31:30 0x0 Specifies how the pre-subtract value (SRCP) is
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computed.
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POSSIBLE VALUES:
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00 - 1.0-2.0*RGB0
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01 - RGB1-RGB0
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02 - RGB1+RGB0
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03 - 1.0-RGB0
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00 - neg2: 1.0-2.0*RGB0
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01 - sub: RGB1-RGB0
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02 - add: RGB1+RGB0
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03 - neg: 1.0-RGB0
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@ -45,8 +45,10 @@ fc = [
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]
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def parse_registers():
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base = path.dirname(__file__)
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for register in register_names:
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filename = path.join("bits", register.lower() + ".txt")
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filename = path.join(base, "bits", register.lower() + ".txt")
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l = list(parse_bits.parse_file_fields(filename))
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yield register, OrderedDict(
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(d.field_name, d) for d in parse_bits.aggregate(l)
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@ -142,5 +144,4 @@ if __name__ == "__main__":
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buf = f.read()
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code = [parse_hex(c.strip()) for c in buf.split(',') if c.strip()]
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for i in range(len(code) // 6):
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disassemble(code, i * 6)
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354
regs/us_disassemble2.py
Normal file
354
regs/us_disassemble2.py
Normal file
@ -0,0 +1,354 @@
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import sys
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from os import path
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import parse_bits
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from collections import OrderedDict
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from functools import partial
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from pprint import pprint
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VERBOSE = False
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class BaseRegister:
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def get(self, code, *, code_ix, descriptor):
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n = code[code_ix]
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if type(descriptor.bits) is int:
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return (n >> descriptor.bits) & 1
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else:
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high, low = descriptor.bits
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assert high > low
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mask_length = (high - low) + 1
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mask = (1 << mask_length) - 1
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return (n >> low) & mask
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def get_name(self, n, *, code_ix, descriptor):
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value = self.get(n, code_ix=code_ix, descriptor=descriptor)
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return value, *descriptor.possible_values[value]
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_descriptor_indicies = {
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"US_CMN_INST": 0,
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"US_ALU_RGB_ADDR": 1,
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"US_ALU_ALPHA_ADDR": 2,
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"US_ALU_RGB_INST": 3,
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"US_ALU_ALPHA_INST": 4,
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"US_ALU_RGBA_INST": 5,
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"US_TEX_INST": 1,
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"US_TEX_ADDR": 2,
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"US_TEX_ADDR_DXDY": 3,
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"US_FC_INST": 2,
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"US_FC_ADDR": 3,
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}
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def parse_register(register_name):
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base = path.dirname(__file__)
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filename = path.join(base, "bits", register_name.lower() + ".txt")
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l = list(parse_bits.parse_file_fields(filename))
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cls = type(register_name, (BaseRegister,), {})
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instance = cls()
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descriptors = list(parse_bits.aggregate(l))
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code_ix = _descriptor_indicies[register_name]
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for descriptor in descriptors:
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setattr(instance, descriptor.field_name,
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partial(instance.get, code_ix=code_ix, descriptor=descriptor))
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setattr(instance, f"_{descriptor.field_name}",
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partial(instance.get_name, code_ix=code_ix, descriptor=descriptor))
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func = getattr(instance, descriptor.field_name)
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for pv_value, (pv_name, _) in descriptor.possible_values.items():
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if pv_name is not None:
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setattr(func, pv_name, pv_value)
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assert getattr(instance, "descriptors", None) is None
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instance.descriptors = descriptors
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return instance
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US_CMN_INST = parse_register("US_CMN_INST")
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US_ALU_RGB_ADDR = parse_register("US_ALU_RGB_ADDR")
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US_ALU_ALPHA_ADDR = parse_register("US_ALU_ALPHA_ADDR")
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US_ALU_RGB_INST = parse_register("US_ALU_RGB_INST")
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US_ALU_ALPHA_INST = parse_register("US_ALU_ALPHA_INST")
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US_ALU_RGBA_INST = parse_register("US_ALU_RGBA_INST")
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US_TEX_INST = parse_register("US_TEX_INST")
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US_TEX_ADDR = parse_register("US_TEX_ADDR")
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US_TEX_ADDR_DXDY = parse_register("US_TEX_ADDR_DXDY")
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US_FC_INST = parse_register("US_FC_INST")
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US_FC_ADDR = parse_register("US_FC_ADDR")
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def disassemble_addr_inner(register_const, address, const, rel):
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assert rel == 0
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if const == register_const.TEMPORARY:
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if address & (1 << 7):
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value = address & 0x7f
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return f"float({value})"
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else:
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return f"temp[{address}]"
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elif const == register_const.CONSTANT:
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return f"const[{address}]"
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else:
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assert False, const
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swizzle_strs = ['r', 'g', 'b', 'a', '0', 'h', '1', '_']
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sel_strs = ['0', '1', '2', 'p']
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def disassemble_addr(register, code, suffix):
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addr0 = register.ADDR0(code)
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addr0_const = register.ADDR0_CONST(code)
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addr0_rel = register.ADDR0_REL(code)
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addr1 = register.ADDR1(code)
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addr1_const = register.ADDR1_CONST(code)
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addr1_rel = register.ADDR1_REL(code)
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addr2 = register.ADDR2(code)
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addr2_const = register.ADDR2_CONST(code)
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addr2_rel = register.ADDR2_REL(code)
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_, srcp_op, _ = register._SRCP_OP(code)
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s0 = disassemble_addr_inner(register.ADDR0_CONST, addr0, addr0_const, addr0_rel)
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s1 = disassemble_addr_inner(register.ADDR1_CONST, addr1, addr1_const, addr1_rel)
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s2 = disassemble_addr_inner(register.ADDR2_CONST, addr2, addr2_const, addr2_rel)
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sp = srcp_op.lower()
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return [
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f"src{sel_strs[i]}.{suffix} = {s}"
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for i, s in enumerate([s0, s1, s2, sp])
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]
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def mod_str(s, mod):
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if mod == 0: # NOP
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return s
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elif mod == 1: # NEG
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return f"-{s}"
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elif mod == 2: # ABS
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return f"|{s}|"
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elif mod == 3: # NAB
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return f"-|{s}|"
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else:
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assert False, mod
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def disassemble_rgb_swizzle_sel(code):
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rgb_sel_a = US_ALU_RGB_INST.RGB_SEL_A(code)
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red_swiz_a = US_ALU_RGB_INST.RED_SWIZ_A(code)
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green_swiz_a = US_ALU_RGB_INST.GREEN_SWIZ_A(code)
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blue_swiz_a = US_ALU_RGB_INST.BLUE_SWIZ_A(code)
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rgb_mod_a = US_ALU_RGB_INST.RGB_MOD_A(code)
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rgb_sel_b = US_ALU_RGB_INST.RGB_SEL_B(code)
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red_swiz_b = US_ALU_RGB_INST.RED_SWIZ_B(code)
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green_swiz_b = US_ALU_RGB_INST.GREEN_SWIZ_B(code)
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blue_swiz_b = US_ALU_RGB_INST.BLUE_SWIZ_B(code)
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rgb_mod_b = US_ALU_RGB_INST.RGB_MOD_B(code)
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rgb_sel_c = US_ALU_RGBA_INST.RGB_SEL_C(code)
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red_swiz_c = US_ALU_RGBA_INST.RED_SWIZ_C(code)
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green_swiz_c = US_ALU_RGBA_INST.GREEN_SWIZ_C(code)
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blue_swiz_c = US_ALU_RGBA_INST.BLUE_SWIZ_C(code)
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rgb_mod_c = US_ALU_RGBA_INST.RGB_MOD_C(code)
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rgb_swiz_a = ''.join(swizzle_strs[n] for n in [red_swiz_a, green_swiz_a, blue_swiz_a])
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rgb_swiz_b = ''.join(swizzle_strs[n] for n in [red_swiz_b, green_swiz_b, blue_swiz_b])
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rgb_swiz_c = ''.join(swizzle_strs[n] for n in [red_swiz_c, green_swiz_c, blue_swiz_c])
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rgb_swiz = [rgb_swiz_a, rgb_swiz_b, rgb_swiz_c]
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rgb_sels = [rgb_sel_a, rgb_sel_b, rgb_sel_c]
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rgb_mods = [rgb_mod_a, rgb_mod_b, rgb_mod_c]
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return [mod_str(f"src{sel_strs[sel]}.{swiz}", mod)
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for swiz, sel, mod in zip(rgb_swiz, rgb_sels, rgb_mods)], rgb_sels
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def disassemble_a_swizzle_sel(code):
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alpha_sel_a = US_ALU_ALPHA_INST.ALPHA_SEL_A(code)
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alpha_swiz_a = US_ALU_ALPHA_INST.ALPHA_SWIZ_A(code)
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alpha_mod_a = US_ALU_ALPHA_INST.ALPHA_MOD_A(code)
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alpha_sel_b = US_ALU_ALPHA_INST.ALPHA_SEL_B(code)
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alpha_swiz_b = US_ALU_ALPHA_INST.ALPHA_SWIZ_B(code)
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alpha_mod_b = US_ALU_ALPHA_INST.ALPHA_MOD_B(code)
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alpha_sel_c = US_ALU_RGBA_INST.ALPHA_SEL_C(code)
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alpha_swiz_c = US_ALU_RGBA_INST.ALPHA_SWIZ_C(code)
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alpha_mod_c = US_ALU_RGBA_INST.ALPHA_MOD_C(code)
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a_swiz = [swizzle_strs[n] for n in [alpha_swiz_a, alpha_swiz_b, alpha_swiz_c]]
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a_sels = [alpha_sel_a, alpha_sel_b, alpha_sel_c]
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a_mods = [alpha_mod_a, alpha_mod_b, alpha_mod_c]
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return [mod_str(f"src{sel_strs[sel]}.{swiz}", mod)
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for swiz, sel, mod in zip(a_swiz, a_sels, a_mods)], a_sels
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def omod_str(s, mod):
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if s == 0: # * 1
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return s
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elif s == 1: # * 1
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return f"({s}) * 1"
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elif s == 2: # * 2
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return f"({s}) * 2"
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elif s == 3: # * 4
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return f"({s}) * 4"
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elif s == 4: # * 8
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return f"({s}) * 8"
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elif s == 5: # / 2
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return f"({s}) / 2"
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elif s == 6: # / 4
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return f"({s}) / 4"
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elif s == 7: # DISABLE OMOD
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return s
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def disassemble_alu_dest(code):
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a_addrd = US_ALU_ALPHA_INST.ALPHA_ADDRD(code)
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a_addrd_rel = US_ALU_ALPHA_INST.ALPHA_ADDRD_REL(code)
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assert a_addrd_rel == 0
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rgb_addrd = US_ALU_RGBA_INST.RGB_ADDRD(code)
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rgb_addrd_rel = US_ALU_RGBA_INST.RGB_ADDRD_REL(code)
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assert rgb_addrd_rel == 0
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_, rgb_wmask, _ = US_CMN_INST._RGB_WMASK(code)
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_, a_wmask, _ = US_CMN_INST._ALPHA_WMASK(code)
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_, rgb_omask, _ = US_CMN_INST._RGB_OMASK(code)
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_, a_omask, _ = US_CMN_INST._ALPHA_OMASK(code)
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a_out_str = f"out[{a_addrd}].{a_omask.lower().ljust(4)}"
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a_temp_str = f"temp[{a_addrd}].{a_wmask.lower().ljust(4)}"
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rgb_out_str = f"out[{rgb_addrd}].{rgb_omask.lower().ljust(4)}"
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rgb_temp_str = f"temp[{rgb_addrd}].{rgb_wmask.lower().ljust(4)}"
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return (a_out_str, a_temp_str), (rgb_out_str, rgb_temp_str)
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def assert_zeros(code):
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rgb_pred_sel = US_CMN_INST.RGB_PRED_SEL(code)
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assert rgb_pred_sel == 0
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rgb_pred_inv = US_CMN_INST.RGB_PRED_INV(code)
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assert rgb_pred_inv == 0
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write_inactive = US_CMN_INST.WRITE_INACTIVE(code)
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assert write_inactive == 0
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last = US_CMN_INST.LAST(code)
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assert last == 0
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nop = US_CMN_INST.NOP(code)
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assert nop == 0
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alu_wait = US_CMN_INST.ALU_WAIT(code)
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assert alu_wait == 0
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rgb_clamp = US_CMN_INST.RGB_CLAMP(code)
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assert rgb_clamp == 0
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alpha_clamp = US_CMN_INST.ALPHA_CLAMP(code)
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assert alpha_clamp == 0
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alu_result_sel = US_CMN_INST.ALU_RESULT_SEL(code)
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assert alu_result_sel == 0
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alpha_pred_inv = US_CMN_INST.ALPHA_PRED_INV(code)
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assert alpha_pred_inv == 0
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alu_result_op = US_CMN_INST.ALU_RESULT_OP(code)
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assert alu_result_op == 0
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alpha_pred_sel = US_CMN_INST.ALPHA_PRED_SEL(code)
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assert alpha_pred_sel == 0
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stat_we = US_CMN_INST.STAT_WE(code)
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assert stat_we == 0
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rgb_omod = US_ALU_RGB_INST.OMOD(code)
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rgb_target = US_ALU_RGB_INST.TARGET(code)
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alu_wmask = US_ALU_RGB_INST.ALU_WMASK(code)
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assert rgb_omod in {0, 7}
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assert rgb_target == 0
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assert alu_wmask == 0
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a_omod = US_ALU_ALPHA_INST.OMOD(code)
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a_target = US_ALU_ALPHA_INST.TARGET(code)
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w_omask = US_ALU_ALPHA_INST.W_OMASK(code)
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assert a_omod in {0, 7}
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assert a_target == 0
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assert w_omask == 0
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_rgb_op_operands = {
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"OP_MAD": 3,
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"OP_DP3": 2,
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"OP_DP4": 2,
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"OP_D2A": 3,
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"OP_MIN": 2,
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"OP_MAX": 2,
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"OP_CND": 3,
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"OP_CMP": 3,
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"OP_FRC": 1,
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"OP_SOP": 0,
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"OP_MDH": 3,
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"OP_MDV": 3,
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}
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_a_op_operands = {
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"OP_MAD": 3,
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"OP_DP": 0,
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"OP_MIN": 2,
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"OP_MAX": 2,
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"OP_CND": 3,
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"OP_CMP": 3,
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"OP_FRC": 1,
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"OP_EX2": 1,
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"OP_RCP": 1,
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"OP_RSQ": 1,
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"OP_SIN": 1,
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"OP_COS": 1,
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"OP_MDH": 3,
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"OP_MDV": 3
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}
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def disassemble_alu(code, is_output):
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assert_zeros(code)
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a_addr_strs = disassemble_addr(US_ALU_ALPHA_ADDR, code, "a")
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rgb_addr_strs = disassemble_addr(US_ALU_RGB_ADDR, code, "rgb")
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a_swizzle_sel, a_sels = disassemble_a_swizzle_sel(code)
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rgb_swizzle_sel, rgb_sels = disassemble_rgb_swizzle_sel(code)
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#print(", ".join([*rgb_swizzle_sel, *a_swizzle_sel]))
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tex_sem_wait = US_CMN_INST.TEX_SEM_WAIT(code)
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_, a_op, _ = US_ALU_ALPHA_INST._ALPHA_OP(code)
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_, rgb_op, _ = US_ALU_RGBA_INST._RGB_OP(code)
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a_op_operands = _a_op_operands[a_op]
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rgb_op_operands = _rgb_op_operands[rgb_op]
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(a_out_str, a_temp_str), (rgb_out_str, rgb_temp_str) = disassemble_alu_dest(code)
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if tex_sem_wait:
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print("TEX_SEM_WAIT")
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if not VERBOSE:
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a_swizzle_sel = a_swizzle_sel[:a_op_operands]
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rgb_swizzle_sel = rgb_swizzle_sel[:rgb_op_operands]
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a_sources = set(a_sels)
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rgb_sources = set(rgb_sels)
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a_addr_strs = [s for i, s in enumerate(a_addr_strs) if i in a_sources]
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rgb_addr_strs = [s for i, s in enumerate(rgb_addr_strs) if i in rgb_sources]
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print(", ".join([*a_addr_strs, *rgb_addr_strs]), ":")
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#print(", ".join(a_addr_strs), ":")
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print(f" {a_out_str} = {a_temp_str} = {a_op.ljust(6)} {' '.join(a_swizzle_sel)}", ",")
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#print(", ".join(rgb_addr_strs), ":")
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print(f" {rgb_out_str} = {rgb_temp_str} = {rgb_op.ljust(6)} {' '.join(rgb_swizzle_sel)}", ";")
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def disassemble(code):
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assert len(code) == 6, len(code)
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type = US_CMN_INST.TYPE(code)
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if type == US_CMN_INST.TYPE.US_INST_TYPE_OUT:
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disassemble_alu(code, is_output=True)
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elif type == US_CMN_INST.TYPE.US_INST_TYPE_ALU:
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disassemble_alu(code, is_output=False)
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else:
|
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assert False, US_CMN_INST._TYPE(code[ix + 0])
|
||||
|
||||
def parse_hex(s):
|
||||
assert s.startswith('0x')
|
||||
return int(s.removeprefix('0x'), 16)
|
||||
|
||||
if __name__ == "__main__":
|
||||
filename = sys.argv[1]
|
||||
with open(filename) as f:
|
||||
buf = f.read()
|
||||
code = [parse_hex(c.strip()) for c in buf.split(',') if c.strip()]
|
||||
for i in range(len(code) // 6):
|
||||
start = (i + 0) * 6
|
||||
end = (i + 1) * 6
|
||||
disassemble(code[start:end])
|
||||
print()
|
||||
Loading…
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Reference in New Issue
Block a user