add triangle.c
This commit is contained in:
parent
66dca90a98
commit
18772f0976
@ -170,12 +170,12 @@
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#define VAP_VF_CNTL 0x2084
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#define VAP_VF_MAX_VTX_INDX 0x2134
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#define VAP_VF_MIN_VTX_INDX 0x2138
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#define VAP_VPORT_XOFFSET 0x1d9c,
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#define VAP_VPORT_XSCALE 0x1d98,
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#define VAP_VPORT_YOFFSET 0x1da4,
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#define VAP_VPORT_YSCALE 0x1da0,
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#define VAP_VPORT_ZOFFSET 0x1dac,
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#define VAP_VPORT_ZSCALE 0x1da8,
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#define VAP_VPORT_XOFFSET 0x1d9c
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#define VAP_VPORT_XSCALE 0x1d98
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#define VAP_VPORT_YOFFSET 0x1da4
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#define VAP_VPORT_YSCALE 0x1da0
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#define VAP_VPORT_ZOFFSET 0x1dac
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#define VAP_VPORT_ZSCALE 0x1da8
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#define VAP_VTE_CNTL 0x20b0
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#define VAP_VTX_NUM_ARRAYS 0x20c0
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#define VAP_VTX_SIZE 0x204b
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21
pci/3d_registers2.h
Normal file
21
pci/3d_registers2.h
Normal file
@ -0,0 +1,21 @@
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#define VAP_PVS_FLOW_CNTL_ADDRS_LW_0 0x2500
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#define VAP_PVS_FLOW_CNTL_ADDRS_UW_0 0x2504
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#define VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 0x2290
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#define RS_IP_0 0x4074
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#define RS_INST_0 0x4320
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#define VAP_OUTPUT_VTX_FMT_0 0x2090
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#define VAP_OUTPUT_VTX_FMT_1 0x2094
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#define VAP_PROG_STREAM_CNTL_0 0x2150
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#define VAP_PROG_STREAM_CNTL_EXT_0 0x21e0
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#define US_OUT_FMT_0 0x46a4
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#define US_OUT_FMT_1 0x46a8
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#define US_OUT_FMT_2 0x46ac
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#define US_OUT_FMT_3 0x46b0
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#define RB3D_COLOROFFSET0 0x4e28
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#define RB3D_COLORPITCH0 0x4e38
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30
pci/main.c
30
pci/main.c
@ -5,6 +5,7 @@
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#include <linux/aperture.h>
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#include "3d_registers.h"
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#include "3d_registers2.h"
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#include "undocumented_3d_registers.h"
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#define R500 "r500"
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@ -64,6 +65,8 @@ static inline uint32_t rreg(void __iomem * rmmio, uint32_t reg)
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#define bswap32 __builtin_bswap32
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#include "triangle.c"
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static const uint8_t _cp_data[] __attribute__((aligned (4))) = {
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0x00,0x00,0x00,0x00,0x42,0x00,0xe0,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0xe0,0x00,
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0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x99,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x9d,
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@ -370,11 +373,28 @@ static int r500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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mb();
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wreg(rmmio, 0x1000, 0xdeadbeef);
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mb();
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for (int i = 0; i < 3; i++) {
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wreg(rmmio, 0x1000, 0xc0001000); // NOP
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mb();
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wreg(rmmio, 0x1000, 0);
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mb();
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}
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mdelay(1);
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scratch = rreg(rmmio, SCRATCH_REG0);
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printk(KERN_INFO "[r500] SCRATCH_REG0 2 %08x\n", scratch);
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mdelay(100);
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triangle(rmmio);
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mdelay(100);
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RM(GA_IDLE);
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RM(VAP_CNTL_STATUS);
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RM(CP_STAT);
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if (0) {
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wreg(rmmio, CP_CSQ_CNTL, 1); // Primary PIO, Indirect Disabled
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wreg(rmmio, CP_CSQ_MODE, (1 << 30) | (1 << 31)); // Primary PIO, Indirect Disabled
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@ -403,12 +423,12 @@ static int r500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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(void)rreg(rmmio, CP_RB_WPTR);
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udelay(500);
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uint32_t scratch_reg0_2 = rreg(rmmio, SCRATCH_REG0);
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printk(KERN_INFO "[r500] SCRATCH_REG0 2 %08x\n", scratch_reg0_2);
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}
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uint32_t scratch_reg0_2 = rreg(rmmio, SCRATCH_REG0);
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printk(KERN_INFO "[r500] SCRATCH_REG0 2 %08x\n", scratch_reg0_2);
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if (1) {
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if (0) {
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// GB_PIPE_SELECT
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// GB_TILE_CONFIG
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// GA_SOFT_RESET
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@ -455,7 +475,7 @@ static int r500_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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printk(KERN_INFO "[r500] SCRATCH_REG0 3 %08x\n", scratch_reg03);
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}
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if (0) {
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if (1) {
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uint32_t tmp;
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tmp = rreg(rmmio, 0xf8);
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printk(KERN_INFO "CONFIG_MEMSIZE 0x%08x\n", tmp);
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275
pci/triangle.c
Normal file
275
pci/triangle.c
Normal file
@ -0,0 +1,275 @@
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#define WM(offset, value) \
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do { \
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wreg(rmmio, offset, value); \
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mb(); \
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mdelay(1); \
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printk(KERN_INFO "[r500] %s %08x\n", #offset, value); \
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} while (0);
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#define RM(offset) \
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do { \
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printk(KERN_INFO "[r500] %s %08x\n", #offset, rreg(rmmio, offset)); \
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} while (0);
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static void triangle(void __iomem * rmmio)
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{
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// r300_emit_gpu_flush
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WM(SC_SCISSOR0, 0);
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uint32_t sc_scissor1 = ((1600 - 1) << 13) | ((1600 - 1) << 0);
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WM(SC_SCISSOR1, sc_scissor1);
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WM(RB3D_DSTCACHE_CTLSTAT, 0xa); // DC_FLUSH | DC_FREE
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WM(ZB_ZCACHE_CTLSTAT, 0x3); // ZC_FLUSH | ZC_FREE
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mb();
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mdelay(100);
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// r300_emit_aa_state
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WM(GB_AA_CONFIG, 0);
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WM(RB3D_AARESOLVE_CTL, 0);
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// r300_emit_fb_state
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WM(RB3D_CCTL, 0x4000); // INDEPENDENT_COLORFORMAT_ENABLE
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WM(RB3D_COLOROFFSET0, 0);
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mb();
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uint32_t rb3d_colorpitch0
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= (1600 << 0) // COLORPITCH
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| (1 << 16) // COLORTILE (is macrotiled)
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| (6 << 21) // COLORFORMAT (ARGB8888)
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;
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WM(RB3D_COLORPITCH0, rb3d_colorpitch0);
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mb();
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WM(ZB_FORMAT, 2); // 24-bit integer, 8 bit stencil
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WM(ZB_DEPTHOFFSET, 0);
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mb();
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uint32_t zb_depthpitch
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= (1600 << 0)
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| (1 << 16) // DEPTHMACROTILE
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| (0b01 << 17) // DEPTHMICROTILE (32 byte cache line is tiled)
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;
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WM(ZB_DEPTHPITCH, zb_depthpitch);
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mb();
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// r300_emit_hyperz_state
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WM(ZB_BW_CNTL, 0);
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WM(ZB_DEPTHCLEARVALUE, 0);
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WM(SC_HYPERZ_EN, 0x1c); // HZ_ADJ (add or subtract 1/2)
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WM(GB_Z_PEQ_CONFIG, 0);
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// r300_emit_ztop_state
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WM(ZB_ZTOP, 1); // Z is at top of pipe, after the scan unit
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// r300_emit_dsa_state
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WM(FG_ALPHA_FUNC, 0);
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WM(ZB_CNTL, 0);
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WM(ZB_ZSTENCILCNTL, 0);
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WM(ZB_STENCILREFMASK, 0);
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WM(ZB_STENCILREFMASK_BF, 0);
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WM(FG_ALPHA_VALUE, 0);
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// r300_emit_blend_state
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WM(RB3D_ROPCNTL, 0);
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WM(RB3D_BLENDCNTL, 0);
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WM(RB3D_ABLENDCNTL, 0);
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WM(RB3D_COLOR_CHANNEL_MASK, 0xf); // BLUE_MASK | GREEN_MASK | RED_MASK | ALPHA_MASK
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WM(RB3D_DITHER_CTL, 0);
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// r300_emit_blend_color_state
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WM(RB3D_CONSTANT_COLOR_AR, 0);
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WM(RB3D_CONSTANT_COLOR_GB, 0);
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// r300_emit_scissor_state
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WM(SC_CLIP_0_A, 0);
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WM(SC_CLIP_0_B, 0x3ffffff);
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// r300_emit_sample_mask
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WM(SC_SCREENDOOR, 0xffffff);
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// r300_emit_invariant_state
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WM(GB_SELECT, 0);
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WM(FG_FOG_BLEND, 0);
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WM(GA_OFFSET, 0);
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WM(SU_TEX_WRAP, 0);
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WM(SU_DEPTH_SCALE, 0x4b7fffff); // 16777215.0f
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WM(SU_DEPTH_OFFSET, 0);
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WM(SC_EDGERULE, 0x2da49525);
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WM(RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x1010101);
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WM(RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xfefefefe);
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WM(GA_COLOR_CONTROL_PS3, 0);
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WM(SU_TEX_WRAP_PS3, 0);
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// r300_emit_viewport_state
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WM(VAP_VPORT_XSCALE, 0x44160000); // 600.0f
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WM(VAP_VPORT_XOFFSET, 0x44480000); // 800.0f
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WM(VAP_VPORT_YSCALE, 0xc4160000); // -600.0f
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WM(VAP_VPORT_YOFFSET, 0x44160000); // 600.0f
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WM(VAP_VPORT_ZSCALE, 0x3f000000); // 0.5f
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WM(VAP_VPORT_ZOFFSET, 0x3f000000); // 0.5f
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// r300_emit_pvs_flush
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WM(VAP_PVS_STATE_FLUSH_REG, 0);
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// r300_emit_vap_invariant_state
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WM(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
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WM(VAP_GB_VERT_CLIP_ADJ, 0x3f800000); // 1.0f
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WM(VAP_GB_VERT_DISC_ADJ, 0x3f800000); // 1.0f
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WM(VAP_GB_HORZ_CLIP_ADJ, 0x3f800000); // 1.0f
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WM(VAP_GB_HORZ_DISC_ADJ, 0x3f800000); // 1.0f
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WM(VAP_PSC_SGN_NORM_CNTL, 0xaaaaaaaa); // SGN_NORM_NO_ZERO
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WM(VAP_TEX_TO_COLOR_CNTL, 0);
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// r300_emit_vertex_stream_state
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WM(VAP_PROG_STREAM_CNTL_0, 0x2002); // DATA_TYPE_0(FLOAT_3) | LAST_VEC_0
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/*
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= SWIZZLE_SELECT_X_0(SELECT_X)
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| SWIZZLE_SELECT_Y_0(SELECT_Y)
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| SWIZZLE_SELECT_Z_0(SELECT_Z)
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| SWIZZLE_SELECT_W_0(SELECT_FP_ONE)
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| WRITE_ENA_0(XYZW)
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*/
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WM(VAP_PROG_STREAM_CNTL_EXT_0, 0xfa88);
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// r300_emit_vs_state
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WM(VAP_PVS_CODE_CNTL_0, 0);
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WM(VAP_PVS_CODE_CNTL_1, 0);
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WM(VAP_PVS_VECTOR_INDX_REG, 0);
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const uint32_t vertex_program[] = {0xf00203, 0xd10001, 0x1248001, 0x1248001};
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for (int i = 0; i < (sizeof (vertex_program)) / (sizeof (vertex_program[0])); i++) {
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wreg(rmmio, VAP_PVS_VECTOR_DATA_REG_128, vertex_program[i]);
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mb();
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}
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/*
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= PVS_NUM_SLOTS(10)
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| PVS_NUM_CNTLRS(5)
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| PVS_NUM_FPUS(5)
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| VF_MAX_VTX_NUM(12)
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| TCL_STATE_OPTIMIZATION
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*/
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WM(VAP_CNTL, 0xb0055a);
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WM(VAP_PVS_FLOW_CNTL_OPC, 0);
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for (int i = 0; i < 16; i++) {
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wreg(rmmio, VAP_PVS_FLOW_CNTL_ADDRS_LW_0 + i * 8, 0);
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wreg(rmmio, VAP_PVS_FLOW_CNTL_ADDRS_UW_0 + i * 8, 0);
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mb();
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}
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for (int i = 0; i < 16; i++) {
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wreg(rmmio, VAP_PVS_FLOW_CNTL_LOOP_INDEX_0 + i * 4, 0);
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mb();
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}
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// r300_emit_clip_state
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WM(VAP_PVS_VECTOR_INDX_REG, 0x600);
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for (int i = 0; i < 128; i++) {
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wreg(rmmio, VAP_PVS_VECTOR_DATA_REG_128, 0);
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mb();
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}
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// r300_emit_rs_block_stat
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WM(VAP_VTX_STATE_CNTL, 0x5555); // Select User Color 0
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WM(VAP_VSM_VTX_ASSM, 0x1);
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WM(VAP_OUTPUT_VTX_FMT_0, 0x1); // output position vector
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WM(VAP_OUTPUT_VTX_FMT_1, 0x4); // TEX_0_COMP_CNT(4)
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WM(GB_ENABLE, 0);
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WM(RS_IP_0, 0x30000000); // Zero components (0,0,0,1)
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WM(RS_COUNT, 0x40080); // IC_COUNT(1) | HIRES_EN
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WM(RS_INST_COUNT, 0);
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WM(RS_INST_0, 0);
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// r300_emit_rs_state
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WM(VAP_CNTL_STATUS, 0);
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WM(VAP_CLIP_CNTL, 0xc000); // PS_UCP_MODE(3)
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WM(GA_POINT_SIZE, 0x60006);
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WM(GA_POINT_MINMAX, 0x60006);
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WM(GA_LINE_CNTL, 0x20006);
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WM(SU_POLY_OFFSET_ENABLE, 0);
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WM(SU_CULL_MODE, 0);
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WM(GA_LINE_STIPPLE_CONFIG, 0);
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WM(GA_LINE_STIPPLE_VALUE, 0);
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WM(GA_POLY_MODE, 0);
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WM(GA_ROUND_MODE, 0x31); // round to nearest | RGB_CLAMP | ALPHA_CLAMP
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WM(SC_CLIP_RULE, 0xffff);
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WM(GA_POINT_S0, 0); // 0.0f
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WM(GA_POINT_T0, 0x3f800000); // 1.0f
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WM(GA_POINT_S1, 0x3f800000); // 1.0f
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WM(GA_POINT_T1, 0); // 0.0f
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// r300_emit_fb_state_pipelined
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//
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WM(US_OUT_FMT_0, 0x1b00); // C4_8 | C0_SEL(Blue) | C1_SEL(Green) | C2_SEL(Red) | C3_SEL(Alpha)
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WM(US_OUT_FMT_1, 0xf); // unused
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WM(US_OUT_FMT_2, 0xf); // unused
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WM(US_OUT_FMT_3, 0xf); // unused
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WM(GB_MSPOS0, 0x66666666);
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WM(GB_MSPOS0, 0x6666666);
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// r500_emit_fs
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WM(US_CONFIG, 0x2); // Legacy behavior for shader model 1
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WM(US_PIXSIZE, 1);
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WM(US_FC_CTRL, 0);
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WM(US_CODE_RANGE, 0);
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WM(US_CODE_OFFSET, 0);
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WM(US_CODE_ADDR, 0);
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WM(GA_US_VECTOR_INDEX, 0);
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const uint32_t fragment_program[] = {0x78005, 0x8020080, 0x8020080, 0x1c9b04d8, 0x1c810003, 0x5};
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for (int i = 0; i < (sizeof (fragment_program)) / (sizeof (fragment_program[0])); i++) {
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wreg(rmmio, GA_US_VECTOR_DATA, fragment_program[i]);
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mb();
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}
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WM(FG_DEPTH_SRC, 0);
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WM(US_W_FMT, 0);
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// r300_emit_vs_constants
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WM(VAP_PVS_CONST_CNTL, 0);
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// r300_emit_texture_cache_inval
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WM(TX_INVALTAGS, 0);
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// r300_emit_textures_state
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WM(TX_ENABLE, 0);
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// r500_emit_index_bias
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WM(VAP_INDEX_OFFSET, 0);
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// r300_emit_draw_init
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WM(GA_COLOR_CONTROL, 0x3aaaa); // gouraud shading | provoking is always last vertex
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WM(VAP_VF_MAX_VTX_INDX, 2);
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WM(VAP_VF_MIN_VTX_INDX, 0);
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// r300_draw_arrays_immediate
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WM(VAP_VTX_SIZE, 3);
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const float vertices[] = {
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0.5, -0.5, 0,
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-0.5, -0.5, 0,
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0, 0.5, 0,
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};
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#define _3D_DRAW_IMMD_2 (0x35)
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#define NOP (0x10)
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#define TYPE_3_PACKET(opcode, count) \
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((3 << 30) | ((count) << 16) | (opcode << 8))
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printk(KERN_INFO "[r500] draw start\n");
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wreg(rmmio, 0x1000, TYPE_3_PACKET(_3D_DRAW_IMMD_2, (3 * 3)));
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mb();
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mdelay(1);
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wreg(rmmio, 0x1000, 0x30034); // VAP_VF_CNTL
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mb();
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mdelay(1);
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const uint32_t * vertices_u32 = (const uint32_t *)vertices;
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for (int i = 0; i < 9; i++) {
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wreg(rmmio, 0x1000, vertices_u32[i]);
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mb();
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mdelay(1);
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}
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wreg(rmmio, 0x1000, TYPE_3_PACKET(NOP, 4 - 1));
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mb();
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mdelay(1);
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for (int i = 0; i < 4; i++) {
|
||||
wreg(rmmio, 0x1000, 0);
|
||||
mb();
|
||||
mdelay(1);
|
||||
}
|
||||
|
||||
printk(KERN_INFO "[r500] draw end\n");
|
||||
|
||||
WM(0x6110, 0xe0000000);
|
||||
}
|
||||
@ -16,3 +16,5 @@
|
||||
#define RBBM_SOFT_RESET_IDCT (1 << 14)
|
||||
|
||||
#define SCRATCH_REG0 0x15e0
|
||||
|
||||
#define VAP_VSM_VTX_ASSM 0x2184
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user