Zack Buhman
da49dbeb2b
I'm still not satisfied with the Makefile, but this at least makes it converge in a single make invocation again. This also removes the enum value arrays.
474 lines
14 KiB
C++
474 lines
14 KiB
C++
#include <cstdint>
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#include "vdp2.h"
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#include "vdp1.h"
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#include "scu.h"
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#include "smpc.h"
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#include "sh2.h"
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#include "common/copy.hpp"
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#include "common/vdp2_func.hpp"
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#include "common/intback.hpp"
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#include "input.hpp"
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#include "gen/maps.hpp"
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#include "gen/sprites.hpp"
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#include "map_objects.hpp"
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constexpr inline uint16_t rgb15(int32_t r, int32_t g, int32_t b)
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{
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return ((b & 31) << 10) | ((g & 31) << 5) | ((r & 31) << 0);
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}
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void palette_data()
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{
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vdp2.cram.u16[3] = rgb15( 0, 0, 0);
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vdp2.cram.u16[2] = rgb15(10, 10, 10);
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vdp2.cram.u16[1] = rgb15(21, 21, 21);
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vdp2.cram.u16[0] = rgb15(31, 31, 31);
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}
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static inline void _2bpp_4bpp_vram_copy(uint32_t * vram, const start_size_t& buf)
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{
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for (uint32_t ix = 0; ix < buf.size / 4; ix += 1) {
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const uint32_t pixels = reinterpret_cast<uint32_t const * const>(buf.start)[ix];
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const uint32_t px0 = pixels >> 16 & 0xffff;
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const uint32_t px1 = pixels >> 0 & 0xffff;
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#define lshift(n) ((7 - n) * 2)
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#define rshift(n) ((7 - n) * 4)
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#define px(p, n) (((p >> lshift(n)) & 0b11) << rshift(n))
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#define p0(n) (px(px0, n))
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#define p1(n) (px(px1, n))
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vram[ix * 2 + 0] = p0(7) | p0(6) | p0(5) | p0(4) | p0(3) | p0(2) | p0(1) | p0(0);
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vram[ix * 2 + 1] = p1(7) | p1(6) | p1(5) | p1(4) | p1(3) | p1(2) | p1(1) | p1(0);
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#undef p1
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#undef p0
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#undef px
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#undef lshift
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#undef rshift
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}
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}
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uint32_t character_pattern_table(const start_size_t& buf, const uint32_t top)
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{
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// round to nearest multiple of 32
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const uint32_t table_size = ((buf.size * 2) + 0x20 - 1) & (-0x20);
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const uint32_t base_address = top - table_size;
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uint32_t * vram = &vdp1.vram.u32[(base_address / 4)];
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_2bpp_4bpp_vram_copy(vram, buf);
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return base_address;
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}
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uint32_t cell_data(const start_size_t& buf, const uint32_t top)
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{
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// round to nearest multiple of 32
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const uint32_t table_size = ((buf.size * 2) + 0x20 - 1) & (-0x20);
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const uint32_t base_address = top - table_size; // in bytes
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uint32_t * vram = &vdp2.vram.u32[(base_address / 4)];
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_2bpp_4bpp_vram_copy(vram, buf);
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return base_address;
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}
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constexpr inline void render_block(const uint32_t base_pattern,
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const tileset_t& tileset,
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const int32_t map_x,
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const int32_t map_y,
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const uint8_t block)
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{
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for (int32_t block_y = 0; block_y < 4; block_y++) {
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for (int32_t block_x = 0; block_x < 4; block_x++) {
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const int32_t block_ix = 4 * block_y + block_x;
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const uint8_t tile_ix = tileset.blockset.start[block * 4 * 4 + block_ix];
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const uint32_t cell_y = map_y * 4 + block_y;
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const uint32_t cell_x = map_x * 4 + block_x;
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// assumes NBG0 map plane_a is at offset 0
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vdp2.vram.u16[64 * (cell_y % 64) + (cell_x % 64)] = (base_pattern & 0xfff) + tile_ix;
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//vdp2.vram.u32[64 * cell_y + cell_x] = base_pattern + tile_ix;
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}
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}
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}
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constexpr int32_t last_map = map_t::wardens_house;
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struct draw_t {
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struct {
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uint16_t tilesets[tileset_t::count]; // div 32
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uint16_t spritesheets[spritesheet_t::count]; // div 128
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} base_pattern;
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};
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struct player_t {
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struct {
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int32_t x;
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int32_t y;
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};
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};
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struct state_t {
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enum map_t::map map;
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draw_t draw;
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player_t player;
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};
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static state_t state = { map_t::pallet_town, 0 };
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uint32_t load_tileset(uint32_t top, enum tileset_t::tileset tileset)
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{
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uint32_t base_address = top = cell_data(tilesets[tileset].tileset, top);
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state.draw.base_pattern.tilesets[tileset] = base_address / 32;
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return top;
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}
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uint32_t load_sprite(uint32_t top, enum spritesheet_t::spritesheet spritesheet)
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{
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const spritesheet_t& s = spritesheets[spritesheet];
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uint32_t base_address = top = character_pattern_table(s.spritesheet, top);
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state.draw.base_pattern.spritesheets[spritesheet] = base_address / 128;
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return top;
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}
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void load_vram()
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{
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vdp2.reg.CYCA0 = 0xeeee'eeee;
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vdp2.reg.CYCA1 = 0xeeee'eeee;
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vdp2.reg.CYCB0 = 0xeeee'eeee;
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vdp2.reg.CYCB1 = 0xeeee'eeee;
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uint32_t vdp2_top = (sizeof (union vdp2_vram));
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for (uint32_t i = 0; i < tileset_t::count; i++)
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vdp2_top = load_tileset(vdp2_top, static_cast<enum tileset_t::tileset>(i));
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vdp2.reg.CYCA0 = 0x0121'ffff;
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vdp2.reg.CYCA1 = 0x0121'ffff;
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vdp2.reg.CYCB0 = 0x4565'ffff;
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vdp2.reg.CYCB1 = 0x4565'ffff;
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uint32_t vdp1_top = (sizeof (union vdp1_vram));
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for (uint32_t i = 0; i < spritesheet_t::count; i++)
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vdp1_top = load_sprite(vdp1_top, static_cast<enum spritesheet_t::spritesheet>(i));
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}
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// screen space
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constexpr int32_t origin_px_x = ((320 - 160) / 2);
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constexpr int32_t origin_px_y = ((240 - 144) / 2);
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constexpr int32_t origin_cell_x = origin_px_x / 8;
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constexpr int32_t origin_cell_y = origin_px_y / 8;
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void render_sprites()
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{
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uint32_t ix = 2;
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constexpr uint32_t color_address = 0;
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const uint32_t character_address = (state.draw.base_pattern.spritesheets[spritesheet_t::oak] * 128) / 8;
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vdp1.vram.cmd[ix].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__NORMAL_SPRITE;
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vdp1.vram.cmd[ix].LINK = 0;
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// The "end code" is 0xf, which is being used in the mai sprite palette. If
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// both transparency and end codes are enabled, it seems there are only 14
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// usable colors in the 4-bit color mode.
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vdp1.vram.cmd[ix].PMOD = PMOD__ECD | PMOD__COLOR_MODE__COLOR_BANK_16;
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// It appears Kronos does not correctly calculate the color address in the
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// VDP1 debugger. Kronos will report FFFC when the actual color table address
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// in this example is 7FFE0.
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vdp1.vram.cmd[ix].COLR = color_address; // non-palettized (rgb15) color data
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vdp1.vram.cmd[ix].SRCA = character_address;
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vdp1.vram.cmd[ix].SIZE = SIZE__X(16) | SIZE__Y(16);
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vdp1.vram.cmd[ix].XA = origin_px_x + 4 * 16;
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vdp1.vram.cmd[ix].YA = origin_px_y + 4 * 16 - 4;
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ix++;
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constexpr uint16_t top_x = 80 - 1;
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constexpr uint16_t top_y = 48 - 1;
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constexpr uint16_t bot_x = 239 + 1;
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constexpr uint16_t bot_y = 191 + 1;
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vdp1.vram.cmd[ix].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__POLYLINE;
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vdp1.vram.cmd[ix].LINK = 0;
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// "Set [ECD] to '1' for polygons, polylines, and lines"
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// "Be sure to set [SPD] to '1' for polygons, polylines, and lines"
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//
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// The "user clip mode" bit is not set in PMOD here, so setting "user clip
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// coordinates" has no effect on this draw command. However, "system clip
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// coordinates" and "local coordinates" are always applied, and must be set to
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// reasonable values.
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vdp1.vram.cmd[ix].PMOD = PMOD__ECD | PMOD__SPD;
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vdp1.vram.cmd[ix].COLR = COLR__RGB | rgb15(255, 0, 255);
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vdp1.vram.cmd[ix].XA = top_x;
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vdp1.vram.cmd[ix].YA = top_y;
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vdp1.vram.cmd[ix].XB = bot_x;
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vdp1.vram.cmd[ix].YB = top_y;
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vdp1.vram.cmd[ix].XC = bot_x;
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vdp1.vram.cmd[ix].YC = bot_y;
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vdp1.vram.cmd[ix].XD = top_x;
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vdp1.vram.cmd[ix].YD = bot_y;
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ix++;
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vdp1.vram.cmd[ix].CTRL = CTRL__END;
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}
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static uint16_t scroll = 0;
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/*
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in block units:
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world screen
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-----------|---------
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player 0,0 | map 4,4
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scrolled 16,16
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player 1,1 |
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world | screen
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--------------------------|---------
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top left = player x - 5 | (add 4)
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top right = player x - 5 | (add 4)
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----
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screen scroll
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0,0 -> screen 0,0
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1,1 -> screen 16,16
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*/
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// there are 16 pixels per block
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void render_map()
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{
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if (++scroll > 4) {
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scroll = 0;
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state.player.x += 1;
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state.player.y += 1;
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}
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vdp2.reg.SCXIN0 = state.player.x - 16;
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vdp2.reg.SCYIN0 = state.player.y - 16;
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/*
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vdp2.reg.WPSX0 = 80 << 1;
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vdp2.reg.WPSY0 = 48;
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vdp2.reg.WPEX0 = 239 << 1;
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vdp2.reg.WPEY0 = 191;
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vdp2.reg.WCTLA = WCTLA__N0W0E | WCTLA__N0W0A__OUTSIDE;
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*/
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const map_t& map = maps[state.map];
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const uint8_t border_block = map_objects[state.map].border_block;
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const uint32_t base_pattern = state.draw.base_pattern.tilesets[map.tileset];
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vdp2.reg.PNCN0 = PNCN0__N0PNB__1WORD | PNCN0__N0CNSM | PNCN0__N0SCN((base_pattern >> 10) & 0x1f);
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int32_t origin_x = state.player.x / 32;
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int32_t origin_y = state.player.y / 32;
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fill<uint32_t>(vdp2.vram.u32, 0, 64 * 64 * 2);
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for (int32_t y = origin_y - 3; y <= (origin_y + 3); y++) {
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for (int32_t x = origin_x - 3; x <= (origin_x + 3); x++) {
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const uint8_t block = ( (x < static_cast<int32_t>(map.width))
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&& (y < static_cast<int32_t>(map.height))
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&& (x >= 0)
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&& (y >= 0))
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? map.blocks.start[map.width * y + x]
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: border_block;
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//const uint8_t block = map.blocks.start[map.width * 0 + 0];
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render_block(base_pattern,
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tilesets[map.tileset],
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x + 4,
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y + 3,
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block);
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}
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}
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vdp2.reg.BGON = BGON__N0ON | BGON__N0TPON;
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}
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void render()
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{
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render_map();
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render_sprites();
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}
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extern "C"
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void v_blank_in_int(void) __attribute__ ((interrupt_handler));
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void v_blank_in_int()
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{
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scu.reg.IST &= ~(IST__V_BLANK_IN);
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scu.reg.IMS = ~(IMS__SMPC | IMS__V_BLANK_IN);
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sh2.reg.FRC.H = 0;
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sh2.reg.FRC.L = 0;
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sh2.reg.FTCSR = 0; // clear flags
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render();
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// wait at least 300us, as specified in the SMPC manual.
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// It appears reading FRC.H is mandatory and *must* occur before FRC.L on real
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// hardware.
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while ((sh2.reg.FTCSR & FTCSR__OVF) == 0 && sh2.reg.FRC.H == 0 && sh2.reg.FRC.L < 63);
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// on real hardware, SF contains uninitialized garbage bits other than the
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// lsb.
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while ((smpc.reg.SF & 1) != 0);
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smpc.reg.SF = 0;
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smpc.reg.IREG[0].val = INTBACK__IREG0__STATUS_DISABLE;
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smpc.reg.IREG[1].val = ( INTBACK__IREG1__PERIPHERAL_DATA_ENABLE
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| INTBACK__IREG1__PORT2_15BYTE
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| INTBACK__IREG1__PORT1_15BYTE
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);
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smpc.reg.IREG[2].val = INTBACK__IREG2__MAGIC;
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smpc.reg.COMREG = COMREG__INTBACK;
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}
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extern "C"
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void smpc_int(void) __attribute__ ((interrupt_handler));
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void smpc_int(void)
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{
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scu.reg.IST &= ~(IST__SMPC);
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scu.reg.IMS = ~(IMS__SMPC | IMS__V_BLANK_IN);
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intback::fsm(digital_callback, nullptr);
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}
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void init_vdp1()
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{
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/* TVM settings must be performed from the second H-blank IN interrupt after the
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V-blank IN interrupt to the H-blank IN interrupt immediately after the V-blank
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OUT interrupt. */
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// "normal" display resolution, 16 bits per pixel, 512x256 framebuffer
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vdp1.reg.TVMR = TVMR__TVM__NORMAL;
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// swap framebuffers every 1 cycle; non-interlace
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vdp1.reg.FBCR = 0;
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// during a framebuffer erase cycle, write the color "black" to each pixel
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constexpr uint16_t black = 0x0000;
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vdp1.reg.EWDR = black;
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// the EWLR/EWRR macros use somewhat nontrivial math for the X coordinates
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// erase upper-left coordinate
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vdp1.reg.EWLR = EWLR__16BPP_X1(0) | EWLR__Y1(0);
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// erase lower-right coordinate
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vdp1.reg.EWRR = EWRR__16BPP_X3(319) | EWRR__Y3(239);
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vdp1.vram.cmd[0].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__SYSTEM_CLIP_COORDINATES;
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vdp1.vram.cmd[0].LINK = 0;
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vdp1.vram.cmd[0].XC = 319;
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vdp1.vram.cmd[0].YC = 239;
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vdp1.vram.cmd[1].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__LOCAL_COORDINATE;
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vdp1.vram.cmd[1].LINK = 0;
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vdp1.vram.cmd[1].XA = 0;
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vdp1.vram.cmd[1].YA = 0;
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vdp1.vram.cmd[2].CTRL = CTRL__END;
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// start drawing (execute the command list) on every frame
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vdp1.reg.PTMR = PTMR__PTM__FRAME_CHANGE;
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}
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void init_vdp2()
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{
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vdp2.reg.PRISA = PRISA__S0PRIN(7); // Sprite register 0 PRIority Number
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vdp2.reg.PRINA = PRINA__N0PRIN(5)
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| PRINA__N1PRIN(6);
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// DISP: Please make sure to change this bit from 0 to 1 during V blank.
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vdp2.reg.TVMD = ( TVMD__DISP | TVMD__LSMD__NON_INTERLACE
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| TVMD__VRESO__240 | TVMD__HRESO__NORMAL_320);
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vdp2.reg.EXTEN = 0;
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/* set the color mode to 5bits per channel, 1024 colors */
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vdp2.reg.RAMCTL = RAMCTL__CRKTE | RAMCTL__CRMD__RGB_5BIT_1024;// | RAMCTL__VRAMD | RAMCTL__VRBMD;
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/* disable display of NBG0 */
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vdp2.reg.BGON = 0;
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/* set character format for NBG0 to palettized 16 color
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set enable "cell format" for NBG0
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set character size for NBG0 to 1x1 cell */
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vdp2.reg.CHCTLA = CHCTLA__N0CHCN__16_COLOR
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| CHCTLA__N0BMEN__CELL_FORMAT
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| CHCTLA__N0CHSZ__1x1_CELL
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| CHCTLA__N1CHCN__16_COLOR
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| CHCTLA__N1BMEN__CELL_FORMAT
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| CHCTLA__N1CHSZ__1x1_CELL;
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/* plane size */
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vdp2.reg.PLSZ = PLSZ__N0PLSZ__1x1
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| PLSZ__N1PLSZ__1x1;
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/* map plane offset
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1-word: value of bit 6-0 * 0x2000
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2-word: value of bit 5-0 * 0x4000
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*/
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constexpr int nbg0_plane_a = 0;
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constexpr int nbg1_plane_a = 1;
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//constexpr int plane_a_offset = plane_a * 0x2000;
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//constexpr int page_size = 64 * 64 * 2; // N0PNB__1WORD (16-bit)
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//constexpr int plane_size = page_size * 1;
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// bits 8~6
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vdp2.reg.MPOFN = MPOFN__N0MP(0)
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| MPOFN__N1MP(0);
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vdp2.reg.MPABN0 = MPABN0__N0MPB(0) | MPABN0__N0MPA(nbg0_plane_a); // bits 5~0
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vdp2.reg.MPCDN0 = MPCDN0__N0MPD(0) | MPCDN0__N0MPC(0); // bits 5~0
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vdp2.reg.MPABN1 = MPABN1__N1MPB(0) | MPABN1__N1MPA(nbg1_plane_a); // bits 5~0
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vdp2.reg.MPCDN1 = MPCDN1__N1MPD(0) | MPCDN1__N1MPC(0); // bits 5~0
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auto& base_pattern = state.draw.base_pattern.tilesets[tileset_t::overworld];
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vdp2.reg.PNCN0 = PNCN0__N0PNB__1WORD | PNCN0__N0CNSM | PNCN0__N0SCN((base_pattern >> 10) & 0x1f);
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vdp2.reg.PNCN1 = PNCN1__N1PNB__1WORD | PNCN1__N1CNSM | PNCN1__N1SCN((base_pattern >> 10) & 0x1f);
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vdp2.vram.u16[0x2000 / 2 + 0] = (base_pattern & 0xfff) + 1;
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vdp2.vram.u16[0x2000 / 2 + 1] = (base_pattern & 0xfff) + 2;
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palette_data();
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}
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void main()
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{
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state.map = map_t::pallet_town;
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load_vram();
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v_blank_in();
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init_vdp1();
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init_vdp2();
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// free-running timer
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sh2.reg.TCR = TCR__CKS__INTERNAL_DIV128;
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sh2.reg.FTCSR = 0;
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// initialize smpc
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smpc.reg.DDR1 = 0; // INPUT
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smpc.reg.DDR2 = 0; // INPUT
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smpc.reg.IOSEL = 0; // SMPC control
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smpc.reg.EXLE = 0; //
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sh2_vec[SCU_VEC__SMPC] = (u32)(&smpc_int);
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sh2_vec[SCU_VEC__V_BLANK_IN] = (u32)(&v_blank_in_int);
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scu.reg.IST = 0;
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scu.reg.IMS = ~(IMS__SMPC | IMS__V_BLANK_IN);
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}
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