66 lines
1.8 KiB
C
66 lines
1.8 KiB
C
#include "sh7091_scif.h"
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void scif_init_wait()
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{
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sh7091_TMU.TSTR &= (~tmu__tstr__str1__counter_start) & 0xff; // stop TCNT1
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sh7091_TMU.TOCR = tmu__tocr__tcoe__tclk_is_external_clock_or_input_capture;
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sh7091_TMU.TCR1 = tmu__tcr1__tpsc__p_phi_1024; // 1024 / 50MHz = 20.48 μs
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sh7091_TMU.TCOR1 = 0xffffffff;
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sh7091_TMU.TCNT1 = 0xffffffff;
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sh7091_TMU.TSTR |= tmu__tstr__str1__counter_start;
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uint32_t start = sh7091_TMU.TCNT1;
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while ((start - sh7091_TMU.TCNT1) < 20);
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sh7091_TMU.TSTR &= (~tmu__tstr__str1__counter_start) & 0xff; // stop TCNT1
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}
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void scif_init(int bit_rate)
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{
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sh7091_SCIF.SCSCR2 = 0; // disable transmission / reception
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sh7091_SCIF.SCSPTR2 = 0; // clear output data pins
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sh7091_SCIF.SCFCR2 = scfcr2__tfrst__reset_operation_enabled
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| scfcr2__rfrst__reset_operation_enabled;
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sh7091_SCIF.SCSMR2 = scsmr2__chr__8_bit_data
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| scsmr2__pe__parity_disabled
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| scsmr2__stop__1_stop_bit
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| scsmr2__cks__p_phi_clock;
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sh7091_SCIF.SCBRR2 = bit_rate; // bps = 1562500 / (SCBRR2 + 1)
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sh7091_SCIF.SCFSR2 = (~scfsr2__er__bit_mask)
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& (~scfsr2__tend__bit_mask)
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& (~scfsr2__tdfe__bit_mask)
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& (~scfsr2__brk__bit_mask)
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& (~scfsr2__rdf__bit_mask)
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& (~scfsr2__dr__bit_mask)
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& 0xffff;
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// wait 1 bit interval
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scif_init_wait();
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sh7091_SCIF.SCFCR2 = scfcr2__rtrg__trigger_on_1_byte
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| scfcr2__ttrg__trigger_on_8_bytes
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//| scfcr2__mce__modem_signals_enabled
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;
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sh7091_SCIF.SCSCR2 = scscr2__te__transmission_enabled
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| scscr2__re__reception_enabled;
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sh7091_SCIF.SCLSR2 = 0; // clear ORER
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}
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void scif_character(const char c)
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{
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// wait for transmit fifo to become partially empty
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while ((sh7091_SCIF.SCFSR2 & scfsr2__tdfe__bit_mask) == 0);
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sh7091_SCIF.SCFSR2 &= ~scfsr2__tdfe__bit_mask;
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sh7091_SCIF.SCFTDR2 = (uint8_t)(c);
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}
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