g2-fpga/Makefile
2025-01-29 06:09:33 -06:00

26 lines
618 B
Makefile

LIB = /home/bilbo/cc-toolchain-linux
YOSYS = $(LIB)/bin/yosys/yosys
PR = $(LIB)/bin/p_r/p_r
OFL = $(LIB)/../openFPGALoader/build/openFPGALoader
GTKW = gtkwave
IVL = iverilog
VVP = vvp
IVLFLAGS = -g2012 -gspecify -Ttyp
GHDL = ghdl
VLOG_SRC = $(shell find ./src -type f \( -iname \*.v -o -iname \*.sv \))
TOP = top
PRFLAGS = -uCIO -ccf src/$(TOP).ccf -cCP
synth_vlog: $(VLOG_SRC)
$(YOSYS) -qql log/synth.log -p 'read_verilog -sv $^; synth_gatemate -top $(TOP) -nomx8 -vlog net/$(TOP)_synth.v'
impl:
$(PR) -i net/$(TOP)_synth.v -o $(TOP) $(PRFLAGS) > log/$@.log
prog:
$(OFL) -c dirtyJtag $(TOP)_00.cfg.bit