From d29e666c5becfa9aa449995e8582e7a641728762 Mon Sep 17 00:00:00 2001 From: Zack Buhman Date: Wed, 29 Jan 2025 06:09:33 -0600 Subject: [PATCH] initial --- .gitignore | 21 ++++++++ Makefile | 25 +++++++++ log/.empty | 0 net/.empty | 0 src/top.ccf | 72 ++++++++++++++++++++++++++ src/top.v | 146 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 264 insertions(+) create mode 100644 .gitignore create mode 100644 Makefile create mode 100644 log/.empty create mode 100644 net/.empty create mode 100644 src/top.ccf create mode 100644 src/top.v diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..bdb1c3d --- /dev/null +++ b/.gitignore @@ -0,0 +1,21 @@ +*.log +*.txt +*.id +*.net +*.pathes +*.pos +*.refcomp +*.refparam +*.refwire +*.cdf +*.cfg +*.cfg.bit +*.pin +*.place +*.sdf +*.used +*.prn + + +net/*.v +top_00.v diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..416e655 --- /dev/null +++ b/Makefile @@ -0,0 +1,25 @@ +LIB = /home/bilbo/cc-toolchain-linux + +YOSYS = $(LIB)/bin/yosys/yosys +PR = $(LIB)/bin/p_r/p_r +OFL = $(LIB)/../openFPGALoader/build/openFPGALoader + +GTKW = gtkwave +IVL = iverilog +VVP = vvp +IVLFLAGS = -g2012 -gspecify -Ttyp +GHDL = ghdl + +VLOG_SRC = $(shell find ./src -type f \( -iname \*.v -o -iname \*.sv \)) + +TOP = top +PRFLAGS = -uCIO -ccf src/$(TOP).ccf -cCP + +synth_vlog: $(VLOG_SRC) + $(YOSYS) -qql log/synth.log -p 'read_verilog -sv $^; synth_gatemate -top $(TOP) -nomx8 -vlog net/$(TOP)_synth.v' + +impl: + $(PR) -i net/$(TOP)_synth.v -o $(TOP) $(PRFLAGS) > log/$@.log + +prog: + $(OFL) -c dirtyJtag $(TOP)_00.cfg.bit diff --git a/log/.empty b/log/.empty new file mode 100644 index 0000000..e69de29 diff --git a/net/.empty b/net/.empty new file mode 100644 index 0000000..e69de29 diff --git a/src/top.ccf b/src/top.ccf new file mode 100644 index 0000000..120f8b9 --- /dev/null +++ b/src/top.ccf @@ -0,0 +1,72 @@ +Net "G2_MDMCSN" Loc = "IO_NA_A0"; +Net "G2_IRMDMIN" Loc = "IO_NA_B0"; +Net "G2_RQDEVN" Loc = "IO_NA_A1"; +Net "G2_RQEX1N" Loc = "IO_NA_B1"; +Net "G2_RQEX0N" Loc = "IO_NA_A2"; +Net "G2_IREXTN" Loc = "IO_NA_A3"; + +Net "G2_BLN" Loc = "IO_NA_B2"; +Net "G2_STN" Loc = "IO_NA_A4"; +Net "G2_BHN" Loc = "IO_NA_B3"; +Net "G2_DSN" Loc = "IO_NA_B4"; +Net "G2_FRN" Loc = "IO_NA_A5"; +Net "G2_TRN" Loc = "IO_NA_B5"; + +Net "G2_AD[15]" Loc = "IO_NA_A6"; +Net "G2_AD[14]" Loc = "IO_NA_A7"; +Net "G2_AD[13]" Loc = "IO_NB_A0"; +Net "G2_AD[12]" Loc = "IO_NB_B0"; +Net "G2_AD[11]" Loc = "IO_NB_A1"; +Net "G2_AD[10]" Loc = "IO_NB_B1"; +Net "G2_AD[9]" Loc = "IO_NB_A2"; +Net "G2_AD[8]" Loc = "IO_NB_B2"; +Net "G2_AD[7]" Loc = "IO_NB_A3"; +Net "G2_AD[6]" Loc = "IO_NB_B3"; +Net "G2_AD[5]" Loc = "IO_NB_A4"; +Net "G2_AD[4]" Loc = "IO_NB_B4"; +Net "G2_AD[3]" Loc = "IO_NB_A5"; +Net "G2_AD[2]" Loc = "IO_NB_B5"; +Net "G2_AD[1]" Loc = "IO_NB_A6"; +Net "G2_AD[0]" Loc = "IO_NB_B6"; + +Net "G_RST" Loc = "IO_NA_B8"; +Net "G2_CLK" Loc = "IO_NB_A8" | SCHMITT_TRIGGER=true; + +Net "MIDIOUT" Loc = "IO_NA_B6"; +Net "MIDIIN" Loc = "IO_NA_B7"; + +Net "GND_NA_A8" Loc = "IO_NA_A8"; + +Net "GND_NB_B7" Loc = "IO_NB_B7"; +Net "GND_NB_B8" Loc = "IO_NB_B8"; +Net "GND_NB_A7" Loc = "IO_NB_A7"; + +Net "led" Loc = "IO_SB_B6"; + +# outputs + +Net "PROBE_AD[15]" Loc = "IO_EB_B1"; +Net "PROBE_AD[14]" Loc = "IO_EB_B2"; +Net "PROBE_AD[13]" Loc = "IO_EB_B3"; +Net "PROBE_AD[12]" Loc = "IO_EB_B4"; +Net "PROBE_AD[11]" Loc = "IO_EB_B5"; +Net "PROBE_AD[10]" Loc = "IO_EB_B6"; +Net "PROBE_AD[9]" Loc = "IO_EB_B7"; +Net "PROBE_AD[8]" Loc = "IO_EB_B8"; +Net "PROBE_AD[7]" Loc = "IO_EB_A1"; +Net "PROBE_AD[6]" Loc = "IO_EB_A2"; +Net "PROBE_AD[5]" Loc = "IO_EB_A3"; +Net "PROBE_AD[4]" Loc = "IO_EB_A4"; +Net "PROBE_AD[3]" Loc = "IO_EB_A5"; +Net "PROBE_AD[2]" Loc = "IO_EB_A6"; +Net "PROBE_AD[1]" Loc = "IO_EB_A7"; +Net "PROBE_AD[0]" Loc = "IO_EB_A8"; + +Net "PROBE_BLN" Loc = "IO_EA_A8"; # 16 +Net "PROBE_STN" Loc = "IO_EA_B8"; # 17 +Net "PROBE_BHN" Loc = "IO_WB_A8"; # 18 +Net "PROBE_DSN" Loc = "IO_WB_B8"; # 19 +Net "PROBE_FRN" Loc = "IO_SB_B3"; # 20 +Net "PROBE_TRN" Loc = "IO_SB_A3"; # 21 + +Net "PROBE_CLK" Loc = "IO_SB_B2"; # 22 \ No newline at end of file diff --git a/src/top.v b/src/top.v new file mode 100644 index 0000000..b4e821b --- /dev/null +++ b/src/top.v @@ -0,0 +1,146 @@ +module top( + input wire G2_MDMCSN, + input wire G2_IRMDMIN, + input wire G2_RQDEVN, + input wire G2_RQEX1N, + input wire G2_RQEX0N, + input wire G2_IREXTN, + + input wire G2_BLN, + input wire G2_STN, + input wire G2_BHN, + output wire G2_DSN, + input wire G2_FRN, + input wire G2_TRN, + + input wire [15:0] G2_AD, + + input wire G_RST, + input wire G2_CLK, + + input wire MIDIOUT, + input wire MIDIIN, + + input wire GND_NA_A8, + input wire GND_NB_B7, + input wire GND_NB_B8, + input wire GND_NB_A7, + + output wire led, + + output wire [15:0] PROBE_AD, + + output wire PROBE_BLN, + output wire PROBE_STN, + output wire PROBE_BHN, + output wire PROBE_DSN, + output wire PROBE_FRN, + output wire PROBE_TRN, + + output wire PROBE_CLK + + ); + + /* logic analyzer probes */ + + assign PROBE_AD = G2_AD; + assign PROBE_BLN = G2_BLN; + assign PROBE_STN = G2_STN; + assign PROBE_BHN = G2_BHN; + //assign PROBE_DSN = G2_DSN; + assign PROBE_FRN = G2_FRN; + assign PROBE_TRN = G2_TRN; + + assign PROBE_CLK = G2_CLK; + + //assign led = counter[25]; + + always_ff @(negedge G2_CLK) + begin + counter <= counter + 1'b1; + end + + /* begin G2 bus protocol implementation: */ + + reg [26:0] counter; + + reg dsn = 1'b0; + assign PROBE_DSN = dsn; + assign G2_DSN = dsn; + + reg last_frn = 1'b1; + + reg led_on = 1'b1; + assign led = led_on; + +`define STATE_ADDRESS_LOW 2'd0 +`define STATE_ADDRESS_HIGH 2'd1 +`define STATE_DATA_LOW 2'd2 +`define STATE_DATA_HIGH 2'd3 + + reg [1:0] state = `STATE_ADDRESS_LOW; + + reg [31:0] address; + reg [31:0] data; + + always_ff @(negedge G2_CLK) + begin + last_frn <= G2_FRN; + end + + always_ff @(negedge G2_CLK) + begin + if (last_frn & !G2_FRN) + led_on <= !led_on; + end + + always_ff @(negedge G2_CLK) + begin + if (G2_FRN) + dsn <= 1'b1; + end + + always_ff @(negedge G2_CLK) + begin + if (last_frn & !G2_FRN) + begin + if (!G2_BLN) + begin + /* we are only given 1 clock cycle to latch [15:0] of the + address, so we need to latch G2_AD right now */ + /* this is a write operation */ + address[15:0] <= G2_AD; + state <= `STATE_ADDRESS_HIGH; + end + else + begin + /* this is a read operation */ + state <= `STATE_ADDRESS_LOW; + end + end + end + + always_ff @(negedge G2_CLK) + begin + if (!G2_FRN) + if (state == `STATE_ADDRESS_LOW & !G2_BLN) + begin + address[15:0] <= G2_AD; + state <= `STATE_ADDRESS_HIGH; + end + end + + always_ff @(negedge G2_CLK) + begin + if (!G2_FRN) + if (state == `STATE_ADDRESS_HIGH & !G2_BHN) + begin + address[31:16] <= G2_AD; + state <= `STATE_DATA_LOW; + /* signal that we are ready to receive the data */ + dsn <= 1'b0; + led_on <= 1'b0; + end + end + +endmodule