grammar.txt: initial

grammar.txt

@@ -0,0 +1,101 @@
+alu → and | or | xor | add | sub | ad2 | sr | rr | sl | rl | rl8
+
+xy_src → "mc0" | "mc1" | "mc2" | "mc3"
+       | "m0"  | "m1"  | "m2"  | "m3"
+
+mov_ram_x → "mov" xy_src  "," "x"
+mov_mul_p → "mov" "mul"    "," "p"
+mov_ram_p → "mov" xy_src  "," "p"
+
+x_bus → mov_ram_x | mov_mul_p | mov_ram_p
+
+mov_ram_y → "mov" xy_src  "," "y"
+clr_a     → "clr" "a"
+mov_alu_a → "mov" "alu"    "," "a"
+mov_ram_a → "mov" xy_src  "," "a"
+
+y_bus → mov_ram_y | clr_a | mpv_alu_a | mov_ram_a
+
+d1_dest → "rx"  | "pl"
+        | "ra0" | "wa0"
+        | "lop" | "top"
+        | "ct0" | "ct1" | "ct2" | "ct3"
+
+d1_src → "mc0" | "mc1" | "mc2" | "mc3"
+       | "m0"  | "m1"  | "m2"  | "m3"
+       | "alh" | "all"
+
+mov_imm_d1 → "mov" simm8  d1_dest
+mov_ram_d1 → "mov" d1_src d1_dest
+
+d1_bus → mov_imm_d1 → mov_ram_d1
+
+op → ( alu | x_bus | y_bus | d1_bus ) +
+
+load_dest → "mc0" | "mc1" | "mc2" | "mc3"
+          | "rx"  | "pl"
+          | "ra0" | "wa0"
+          | "lop" | "pc"
+
+load_cond → "z"  | "nz"
+          | "s"  | "ns"
+          | "c"  | "nc"
+          | "t0" | "nt0"
+          | "zs" | "nzs"
+
+mvi      → "mvi" uimm25 load_dest
+mvi_cond → "mvi" uimm19 load_dest load_cond
+
+load → mvi | mvi_cond
+
+dma_ingress → "m0" | "m1" | "m2" | "m3"
+            | "prg"
+         
+dma_egress  → "m0" | "m1" | "m2" | "m3"
+
+add_mode = "0" | "1" | "2" | "4" | "8" | "16" | "32" | "64"
+
+dma_dmah → ("dma" | "dmah") add_mode?
+
+dma_length_ram → "m0"  | "m1"  | "m2"  | "m3"
+               | "mc0" | "mc1" | "mc2" | "mc3"
+
+dma_ingress_imm → dma_dmah "d0"       "," dma_ingress "," simm8
+dma_egress_imm  → dma_dmah dma_egress "," "d0"        "," simm8
+dma_ingress_ram → dma_dmah "d0"       "," dma_ingress "," dma_length_ram
+dma_egress_ram  → dma_dmah dma_egress "," "d0"        "," dma_length_ram
+
+dma → dma_ingress_imm | dma_egress_imm | dma_ingress_ram | dma_egress_ram
+
+jump_cond → "z"  | "nz"
+          | "s"  | "ns"
+          | "c"  | "nc"
+          | "t0" | "nt0"
+          | "zs" | "nzs"
+
+jmp      → "jmp" uimm8
+jmp_cond → "jmp" jump_cond
+
+jump → jmp | jmp_cond
+
+loop → "btm" | "lps"
+
+end → "end" | "endi"
+
+instruction → "nop"
+            | op
+	    | load
+	    | dma
+	    | jump
+	    | loop
+	    | end
+
+assignment_statement → identifier "=" expression "\n"
+
+label → identifier ":"
+
+instruction_statement → label? instruction "\n"
+
+statement → assignment_statement
+          | instruction_statement
+

stmt.hpp

@@ -1,4 +1,10 @@
+#include <vector>
 
+#include "expr.hpp"
+
+namespace dsp {
+
+/*
 struct assign_t : stmt_accept_t<assign_t>
 {
   assign_t(token_t name, expr_t * value)
@@ -7,3 +13,223 @@ struct assign_t : stmt_accept_t<assign_t>
   const token_t name;
   const expr_t * value;
 };
+*/
+
+template <bool S, int N>
+struct imm_t {
+  const expr_t * expr;
+
+  static constexpr bool sign = S;
+  static constexpr int bits = N;
+};
+
+template <int N>
+using simm_t = imm_t<true, N>;
+
+template <int N>
+using uimm_t = imm_t<false, N>;
+
+namespace op {
+
+enum alu_type_t {
+  andl,
+  orl,
+  xorl,
+  add,
+  sub,
+  ad2,
+  sr,
+  rr,
+  sl,
+  rl,
+  rl8,
+};
+
+struct alu_t {
+  const alu_type_t type;
+};
+
+enum struct xy_src_t {
+  mc0, mc1, mc2, mc3,
+  m0 , m1 , m2 ,  m3,
+};
+
+struct op_t {
+};
+
+struct mov_ram_x_t : op_t {
+  const xy_src_t src;
+};
+
+struct mov_mul_p_t : op_t {
+};
+
+struct mov_ram_p_t : op_t {
+  const xy_src_t src;
+};
+
+struct mov_ram_y_t : op_t {
+  const xy_src_t src;
+};
+
+struct clr_a_t : op_t {
+};
+
+struct mov_alu_a_t : op_t {
+};
+
+struct mov_ram_a_t : op_t {
+  const xy_src_t src;
+};
+
+enum struct d1_dest_t {
+  rx , pl ,
+  ra0, wa0,
+  lop, top,
+  ct0, ct1, ct2, ct3,
+};
+
+enum struct d1_src_t {
+  mc0, mc1, mc2, mc3,
+  m0 , m1 , m2 , m3 ,
+};
+
+struct mov_imm_d1 : op_t {
+  const simm_t<8> imm;
+  const d1_dest_t dest;
+};
+
+struct mov_ram_d1 : op_t {
+  const d1_src_t src;
+  const d1_dest_t dest;
+};
+
+struct instruction_t {
+  const std::vector<op_t *> ops;
+};
+
+} // op
+
+namespace load {
+
+enum struct dest_t {
+  mc0, mc1, mc2, mc3,
+  rx , pl ,
+  ra0, wa0,
+  lop, pc ,
+};
+
+enum struct cond_t {
+  z , nz ,
+  s , ns ,
+  c , nc ,
+  t0, nt0,
+  zs, nzs,
+};
+
+struct mvi_t {
+  const uimm_t<25> imm;
+};
+
+struct mvi_cond_t {
+  const uimm_t<19> imm;
+};
+
+} // load
+
+namespace dma {
+
+enum struct add_mode_t {
+  _0 ,
+  _1 ,
+  _2 ,
+  _4 ,
+  _8 ,
+  _16,
+  _32,
+  _64,
+};
+
+enum struct ingress_t {
+  m0, m1, m2, m3
+};
+
+enum struct egress_t {
+  m0, m1, m2, m3,
+  prg,
+};
+
+struct ingress_imm_t {
+  const bool hold;
+  const ingress_t ingress;
+  const simm_t<8> imm;
+};
+
+struct egress_imm_t {
+  const bool hold;
+  const egress_t egress;
+  const simm_t<8> imm;
+};
+
+enum struct length_ram_t {
+  m0, m1, m2, m3,
+  mc0, mc1, mc2, mc3,
+};
+
+struct ingress_ram_t {
+  const bool hold;
+  const ingress_t ingress;
+  const length_ram_t ram;
+};
+
+struct egress_ram_t {
+  const bool hold;
+  const egress_t egress;
+  const length_ram_t ram;
+};
+
+} // dma
+
+namespace jump
+{
+
+enum struct cond_t {
+  z , nz,
+  s , ns,
+  c , nc,
+  t0, nt0,
+  zs, nzs,
+};
+
+struct jmp_t {
+  uimm_t<8> imm;
+};
+
+struct jmp_cond_t {
+  uimm_t<8> imm;
+  cond_t cond;
+};
+
+} // jump
+
+namespace loop {
+
+struct btm_t {
+};
+
+struct lps_t {
+};
+
+} // loop
+
+namespace end {
+
+struct end_t {
+};
+
+struct endi_t {
+};
+
+} // loop
+
+} // dsp