diff --git a/test/sample1.asm b/test/sample1.asm new file mode 100644 index 0000000..5770d8f --- /dev/null +++ b/test/sample1.asm @@ -0,0 +1,16 @@ +;; (1) The contents of internal RAM0 of the DSP are copied to internal RAM1. + +; ------- sample (1) start ------- + +COPY_SIZE = 12 ; copy size +RAM0_ADR = $00 ; copy source address +RAM1_ADR = $00 ; copy destination address + + MOV RAM0_ADR,CT0 ; Set copy source address of RAM0 + MOV RAM1_ADR,CT1 ; Set copy destination address for RAM1 + MOV COPY_SIZE-1,LOP ; Set transfer size minus 1 to LOP register + LPS ; Execution of one instruction loop + MOV MC0,MC1 ; Transfer from RAM0 to RAM1 + ENDI + +; ------- sample (1) end ------- diff --git a/test/sample2a.asm b/test/sample2a.asm new file mode 100644 index 0000000..8b5b265 --- /dev/null +++ b/test/sample2a.asm @@ -0,0 +1,30 @@ +;; (2) When calculating 2 x 3 + 4 x 5. (RAM0 x RAM1 + RAM0 x RAM1 = RAM2) +;; (sample 2b is an optimized version of 2a.) + +; ------- sample (2a) start ------- + +RAM0_ADR = $00 ; 2, 4 Start of storage address +RAM1_ADR = $00 ; 3, 5 storage address start +RAM2_ADR = $00 ; Result storage address + + MOV RAM0_ADR,CT0 ; Set RAM0 address + MOV RAM1_ADR,CT1 ; Set RAM1 address + MVI #2,MC0 ; Store "2" to RAM0 (at RAM0 address 0, post-incrementing CT0) + MVI #3,MC1 ; Store "3" to RAM1 (at RAM1 address 0, post-incrementing CT1) + MVI #4,MC0 ; Store "4" to RAM0 (at RAM0 address 1, post-incrementing CT0) + MVI #5,MC1 ; Store "5" to RAM1 (at RAM1 address 1, post-incrementing CT1) + MOV RAM0_ADR,CT0 ; Set RAM0 address + MOV RAM1_ADR,CT1 ; Set RAM1 address + MOV RAM2_ADR,CT2 ; Set RAM2 address + MOV MC0,X ; Transfer data from RAM0 to RX + MOV MC1,Y ; Transfer data from RAM1 to RY + MOV MUL,P ; Store the integration result of RX and RY in PH,PL + MOV MC0,X ; Transfer data from RAM0 to RX + MOV MC1,Y ; Transfer data from RAM1 to RY + CLR A ; Set "0" to ACH and ACL + AD2 MOV ALU,A ; Store the addition result of PH,PL and ACH,ACL in ACH,ACL + MOV MUL,P ; Store the integration result of RX and RY in PH,PL + AD2 MOV ALL,MC2 ; Store the addition result of PH, PL and ACH, ACL in RAM2 + ENDI + +; ------- sample (2a) end ------- diff --git a/test/sample2b.asm b/test/sample2b.asm new file mode 100644 index 0000000..bbaaf30 --- /dev/null +++ b/test/sample2b.asm @@ -0,0 +1,24 @@ +;; (2) When calculating 2 x 3 + 4 x 5. (RAM0 x RAM1 + RAM0 x RAM1 = RAM2) +;; (sample 2b is an optimized version of 2a.) + +; ------- sample (2b) start ------- + +RAM0_ADR = $00 ; 2, 4 Start of storage address +RAM1_ADR = $00 ; 3, 5 storage address start +RAM2_ADR = $00 ; Result storage address + + MOV RAM0_ADR,CT0 + MOV RAM1_ADR,CT1 + MVI #2,MC0 + MVI #3,MC1 + MVI #4,MC0 + MVI #5,MC1 + MOV RAM0_ADR,CT0 + MOV RAM1_ADR,CT1 + MOV MC0,X MOV MC1,Y MOV RAM2_ADR,CT2 + MOV MC0,X MOV MUL,P MOV MC1,Y CLR A + AD2 MOV MUL,P MOV ALU,A + AD2 MOV ALL,MC2 + ENDI + +; ------- sample (2b) end ------- diff --git a/test/sample3.asm b/test/sample3.asm new file mode 100644 index 0000000..d44e0e6 --- /dev/null +++ b/test/sample3.asm @@ -0,0 +1,52 @@ +;; (3) When calculating movement processing for a matrix. (RAM0×RAM1=RAM2) + +;; ┌ ┐ ┌ ┐ ┌ ┐ +;; │ M00 M01 M02 M03 │ │ 1 0 0 x │ │ M00 M01 M02 M03 │ +;; │ M10 M11 M12 M13 │ │ 0 1 0 y │ → │ M10 M11 M12 M13 │ +;; │ M20 M21 M22 M23 │ │ 0 0 1 z │ │ M20 M21 M22 M23 │ +;; └ ┘ │ 0 0 0 1 │ └ ┘ +;; └ ┘ + +; ------- sample (3) start ------- + +DATA_TOP = $10000 >> 2 ; External memory addresses are in units of 4 bytes +MAT_SIZE = $0C ; array size +RAM0_ADR = $00 ; Start address to store X, Y, Z movement amount +RAM1_ADR = $00 ; Work address for array +RAM2_ADR = $00 ; Address of original array + +; (Transfer array with movement amount set from external memory to RAM0) +; + MVI DATA_TOP,RA0 + MOV RAM0_ADR,CT0 + DMA D0,MC0,#$02 +; +; (Copy of array to be operated from RAM2 to RAM1) + MOV RAM2_ADR,CT2 + MOV RAM1_ADR,CT1 + MOV MAT_SIZE-1,LOP + LPS + MOV MC2,MC1 +WAITING: + JMP T0,WAITING +; +; (execute array calculation) + MOV RAM0_ADR,CT0 + MOV RAM1_ADR,CT1 + MOV MC0,X MOV MC1,Y + MOV MC0,X MOV MUL,P MOV MC1,Y CLR A + AD2 MOV MC0,X MOV MUL,P MOV MC1,Y MOV ALU,A MOV RAM0_ADR,CT0 + AD2 MOV MUL,P MOV MC1,Y MOV ALU,A MOV #1,RX + AD2 MOV MC0,X MOV MUL,P MOV MC1,Y MOV ALU,A MOV RAM2_ADR+3,CT2 + AD2 MOV MC0,X MOV MUL,P MOV MC1,Y CLR A MOV ALL,MC2 + AD2 MOV MC0,X MOV MUL,P MOV MC1,Y MOV ALU,A MOV RAM0_ADR,CT0 + AD2 MOV MUL,P MOV MC1,Y MOV ALU,A MOV #1,RX + AD2 MOV MC0,X MOV MUL,P MOV MC1,Y MOV ALU,A MOV RAM2_ADR+7,CT2 + AD2 MOV MC0,X MOV MUL,P MOV MC1,Y CLR A MOV ALL,MC2 + AD2 MOV MC0,X MOV MUL,P MOV MC1,Y MOV ALU,A MOV RAM0_ADR,CT0 + AD2 MOV MUL,P MOV MC1,Y MOV ALU,A MOV #1,RX + AD2 MOV MUL,P MOV ALU,A MOV RAM2_ADR+11,CT2 + AD2 MOV ALL,MC2 + ENDI + +; ------- sample (3) end -------