From 07aecf1b4a6ad46a02770c0d63fbadba4fb49bdb Mon Sep 17 00:00:00 2001 From: Zack Buhman Date: Thu, 24 Aug 2023 19:40:11 +0000 Subject: [PATCH] README: improve DMA add mode explanation --- README.rst | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/README.rst b/README.rst index 040291b..4b99aa5 100644 --- a/README.rst +++ b/README.rst @@ -123,9 +123,10 @@ emit "add mode 1" via the ``DMA1`` and ``DMAH1`` mnemonics. DMA "add mode" and bytes ------------------------ -All of the documentation you have read is invalid; this is the correct -relationship between DMA "add mode" mnemonics. The right columns represent the -the increment added an offset of RA0/WA0 after each bus transfer: +All of the SEGA-authored documentation on this topic is invalid. The +the correct relationship between DMA "add mode" mnemonics and bus +address offsets is shown below. The right columns represent the +increment added to the bus address after each bus transfer: .. list-table:: :header-rows: 1 @@ -176,7 +177,7 @@ writes; instead, the following happens: dst[1] = src[3]; ... - // dst = { 1, 1, 3, 3, ... }; + // dst = { 2, 2, 4, 4, ... }; The SCU manual (ST-97-R5-072694) contains this contradictory text: