Zack Buhman
25e299feba
This is a reshuffling of filenames, extensions, paths, make rules, just because I felt like it.
102 lines
4.3 KiB
C++
102 lines
4.3 KiB
C++
#define CCR__IIX (1 << 15)
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#define CCR__ICI (1 << 11)
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#define CCR__ICE (1 << 8)
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#define CCR__OIX (1 << 7)
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#define CCR__ORA (1 << 5)
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#define CCR__OCI (1 << 4)
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#define CCR__CB (1 << 2)
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#define CCR__WT (1 << 1)
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#define CCR__OCE (1 << 0)
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#define PDTRA__MASK (0b11 << 8)
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#define PDTRA__VGA (0b00 << 8)
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#define PDTRA__RESERVED (0b01 << 8)
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#define PDTRA__RGB (0b10 << 8)
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#define PDTRA__AV (0b11 << 8)
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#define SCFCR2__TFRST (1 << 2)
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#define SCFCR2__RFRST (1 << 1)
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#define SCSCR2__TE (1 << 5)
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#define SCSCR2__RE (1 << 4)
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#define SCFSR2__ER (1 << 7) /* read error */
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#define SCFSR2__TEND (1 << 6) /* transmit end */
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#define SCFSR2__TDFE (1 << 5) /* transmit fifo data empty */
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#define SCFSR2__BRK (1 << 4) /* break detect */
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#define SCFSR2__FER (1 << 3) /* framing error */
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#define SCFSR2__PER (1 << 2) /* parity error */
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#define SCFSR2__RDF (1 << 1) /* receive FIFO data full */
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#define SCFSR2__DR (1 << 0) /* receive data ready */
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#define DMAOR__DDT (1 << 15) /* on-demand data transfer mode */
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/* priority mode */
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#define DMAOR__PR__CH0_CH1_CH2_CH3 (0b11 << 8)
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#define DMAOR__PR__CH0_CH2_CH3_CH1 (0b01 << 8)
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#define DMAOR__PR__CH2_CH0_CH1_CH3 (0b10 << 8)
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#define DMAOR__PR__ROUND_ROBIN (0b11 << 8)
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#define DMAOR__AE (1 << 2) /* address error flag; clear-only */
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#define DMAOR__NMIF (1 << 1) /* non-maskable interrupt flag; clear-only */
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#define DMAOR__DME (1 << 0) /* DMAC master enable */
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/* source address space attribute specification */
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#define CHCR2__SSA__RESERVED_IN_PCMCIA_ACCESS (0b000 << 29)
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#define CHCR2__SSA__DYNAMIC_BUS_SIZING_IO_SPACE (0b001 << 29)
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#define CHCR2__SSA__8BIT_IO_SPACE (0b010 << 29)
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#define CHCR2__SSA__16BIT_IO_SPACE (0b011 << 29)
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#define CHCR2__SSA__8BIT_COMMON_MEMORY_SPACE (0b100 << 29)
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#define CHCR2__SSA__16BIT_COMMON_MEMORY_SPACE (0b101 << 29)
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#define CHCR2__SSA__8BIT_ATTRIBUTE_MEMORY_SPACE (0b110 << 29)
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#define CHCR2__SSA__16BIT_ATTRIBUTE_MEMORY_SPACE (0b111 << 29)
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/* source address wait control select */
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#define CHCR2__STC__C5_SPACE_WAIT_CYCLE_SELECTION (0 << 28)
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#define CHCR2__STC__C6_SPACE_WAIT_CYCLE_SELECTION (1 << 28)
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/* destination address space attribute specification */
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#define CHCR2__DSA__RESERVED_IN_PCMCIA_ACCESS (0b000 << 25)
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#define CHCR2__DSA__DYNAMIC_BUS_SIZING_IO_SPACE (0b001 << 25)
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#define CHCR2__DSA__8BIT_IO_SPACE (0b010 << 25)
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#define CHCR2__DSA__16BIT_IO_SPACE (0b011 << 25)
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#define CHCR2__DSA__8BIT_COMMON_MEMORY_SPACE (0b100 << 25)
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#define CHCR2__DSA__16BIT_COMMON_MEMORY_SPACE (0b101 << 25)
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#define CHCR2__DSA__8BIT_ATTRIBUTE_MEMORY_SPACE (0b110 << 25)
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#define CHCR2__DSA__16BIT_ATTRIBUTE_MEMORY_SPACE (0b111 << 25)
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/* destination address wait control select */
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#define CHCR2__DTC__C5_SPACE_WAIT_CYCLE_SELECTION (0 << 24)
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#define CHCR2__DTC__C6_SPACE_WAIT_CYCLE_SELECTION (1 << 24)
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/* DREQ select */
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#define CHCR2__DS__LOW_LEVEL_DETECTION (0 << 19)
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#define CHCR2__DS__FALLING_EDGE_DETECTION (1 << 19)
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/* request check level */
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#define CHCR2__RL__DRAK_IS_AN_ACTIVE_HIGH_OUTPUT (0 << 18)
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#define CHCR2__RL__DRAK_IS_AN_ACTIVE_LOW_OUTPUT (1 << 18)
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/* acknowledge mode */
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#define CHCR2__AM__DACK_IS_OUTPUT_IN_READ_CYCLE (0 << 17)
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#define CHCR2__AM__DACK_IS_OUTPUT_IN_WRITE_CYCLE (1 << 17)
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/* acknowledge level */
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#define CHCR2__AL__ACTIVE_HIGH_OUTPUT (0 << 16)
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#define CHCR2__AL__ACTIVE_LOW_OUTPUT (1 << 16)
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/* destination address mode */
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#define CHCR2__DM__DESTINATION_ADDRESS_FIXED (0b00 << 14)
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#define CHCR2__DM__DESTINATION_ADDRESS_INCREMENTED (0b01 << 14)
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#define CHCR2__DM__DESTINATION_ADDRESS_DECREMENTED (0b10 << 14)
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/* source address mode */
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#define CHCR2__SM__SOURCE_ADDRESS_FIXED (0b00 << 12)
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#define CHCR2__SM__SOURCE_ADDRESS_INCREMENTED (0b01 << 12)
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#define CHCR2__SM__SOURCE_ADDRESS_DECREMENTED (0b10 << 12)
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/* resource select */
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#define CHCR2__RS(n) (((n) & 0b1111) << 8)
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/* transmit mode */
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#define CHCR2__TM__CYCLE_STEAL_MODE (0 << 7)
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#define CHCR2__TM__BURST_MODE (1 << 7)
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/* transmit size */
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#define CHCR2__TS__64_BIT (0b000 << 4)
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#define CHCR2__TS__8_BIT (0b001 << 4)
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#define CHCR2__TS__16_BIT (0b010 << 4)
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#define CHCR2__TS__32_BIT (0b011 << 4)
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#define CHCR2__TS__32_BYTE (0b100 << 4)
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#define CHCR2__IE (1 << 2) /* interrupt enable */
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#define CHCR2__TE (1 << 1) /* transfer end; clear only */
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#define CHCR2__DE (1 << 0) /* DMAC (channel) enable */
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#define DMATCR2__TRANSFER_COUNT(n) (((n) & 0xffffff) << 0)
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