Zack Buhman
511d99563d
From the GCC manual.
> GCC permits a C structure to have no members:
struct empty {
};
> The structure has size zero. In C++, empty structures are part of the
> language. G++ treats empty structures as if they had a single member of type
> char.
I was not aware of the different behavior in C++.
This fixes every maple example--most were broken for multiple reasons, including
this one.
This also enables SH4 caching. This includes linking code/data into the P1
area (previously this was not the case).
The maple examples (which indeed involve much use of DMA) require much work to
successfully work with the operand and copyback caches. The vibration example
currently is the most complete, though I should consider more on how I want to
structure maple response operand cache invalidation more generally.
60 lines
2.8 KiB
C++
60 lines
2.8 KiB
C++
#define C2DST__STATUS (1 << 0)
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#define CD2LEN__LENGTH(n) (((n) & 0xffffe0) << 0)
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#define C2DSTAT__ADDRESS(n) ((((n) & 0x13ffffe0) | 0x10000000) << 0)
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#define ISTNRM__END_OF_TRANSFERRING_PUNCH_THROUGH_LIST (1 << 21)
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#define ISTNRM__END_OF_DMA_SORT_DMA (1 << 20)
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#define ISTNRM__END_OF_DMA_CH2_DMA (1 << 19)
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#define ISTNRM__END_OF_DMA_DEV_DMA (1 << 18)
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#define ISTNRM__END_OF_DMA_EXT_DMA2 (1 << 17)
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#define ISTNRM__END_OF_DMA_EXT_DMA1 (1 << 16)
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#define ISTNRM__END_OF_DMA_AICA_DMA (1 << 15)
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#define ISTNRM__END_OF_DMA_GD_DMA (1 << 14)
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#define ISTNRM__MAPLE_V_BLANK_OVER_INTERRUPT (1 << 13)
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#define ISTNRM__END_OF_DMA_MAPLE_DMA (1 << 12)
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#define ISTNRM__END_OF_DMA_PVR_DMA (1 << 11)
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#define ISTNRM__END_OF_TRANSFERRING_TRANSLUCENT_MODIFIER_VOLUME_LIST (1 << 10)
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#define ISTNRM__END_OF_TRANSFERRING_TRANSLUCENT_LIST (1 << 9)
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#define ISTNRM__END_OF_TRANSFERRING_OPAQUE_MODIFIER_VOLUME_LIST (1 << 8)
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#define ISTNRM__END_OF_TRANSFERRING_OPAQUE_LIST (1 << 7)
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#define ISTNRM__END_OF_TRANSFERRING_YUV (1 << 6)
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#define ISTNRM__H_BLANK_IN_INTERRUPT (1 << 5)
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#define ISTNRM__V_BLANK_OUT_INTERRUPT (1 << 4)
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#define ISTNRM__V_BLANK_IN_INTERRUPT (1 << 3)
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#define ISTNRM__END_OF_RENDER_TSP (1 << 2)
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#define ISTNRM__END_OF_RENDER_ISP (1 << 1)
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#define ISTNRM__END_OF_RENDER_VIDEO (1 << 0)
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#define ISTERR__SH4__IF_ACCESS_INHIBITED_AREA (1 << 31)
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#define ISTERR__DDT__IF_SORT_DMA_COMMAND_ERROR (1 << 28)
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#define ISTERR__G2__TIME_OUT_IN_CPU_ACCESS (1 << 27)
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#define ISTERR__G2__DEV_DMA_TIME_OUT (1 << 26)
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#define ISTERR__G2__EXT_DMA2_TIME_OUT (1 << 25)
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#define ISTERR__G2__EXT_DMA1_TIME_OUT (1 << 24)
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#define ISTERR__G2__AICA_DMA_TIME_OUT (1 << 23)
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#define ISTERR__G2__DEV_DMA_OVER_RUN (1 << 22)
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#define ISTERR__G2__EXT_DMA2_OVER_RUN (1 << 21)
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#define ISTERR__G2__EXT_DMA1_OVER_RUN (1 << 20)
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#define ISTERR__G2__AICA_DMA_OVER_RUN (1 << 19)
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#define ISTERR__G2__DEV_DMA_ILLEGAL_ADDRESS_SET (1 << 18)
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#define ISTERR__G2__EXT_DMA2_ILLEGAL_ADDRESS_SET (1 << 17)
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#define ISTERR__G2__EXT_DMA1_ILLEGAL_ADDRESS_SET (1 << 16)
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#define ISTERR__G2__AICA_DMA_ILLEGAL_ADDRESS_SET (1 << 15)
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#define ISTERR__G1__ROM_FLASH_ACCESS_AT_GD_DMA (1 << 14)
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#define ISTERR__G1__GD_DMA_OVER_RUN (1 << 13)
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#define ISTERR__G1__ILLEGAL_ADDRESS_SET (1 << 12)
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#define ISTERR__MAPLE__ILLEGAL_COMMAND (1 << 11)
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#define ISTERR__MAPLE__WRITE_FIFO_OVER_FLOW (1 << 10)
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#define ISTERR__MAPLE__DMA_OVER_RUN (1 << 9)
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#define ISTERR__MAPLE__ILLEGAL_ADDRESS_SET (1 << 8)
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#define ISTERR__PVRIF__DMA_OVER_RUN (1 << 7)
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#define ISTERR__PVRIF__ILLEGAL_ADDRESS_SET (1 << 6)
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#define ISTERR__TA__FIFO_OVERFLOW (1 << 5)
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#define ISTERR__TA__ILLEGAL_PARAMETER (1 << 4)
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#define ISTERR__TA__OBJECT_LIST_POINTER_OVERFLOW (1 << 3)
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#define ISTERR__TA__ISP_TSP_PARAMETER_OVERFLOW (1 << 2)
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#define ISTERR__RENDER__HAZARD_PROCESSING_OF_STRIP_BUFFER (1 << 1)
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#define ISTERR__RENDER__ISP_OUT_OF_CACHE (1 << 0)
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