Zack Buhman
f1a32d0719
On an emulator, the receive buffer is filled with the correct/expected data for 'device status'. I found this experiment useful: - it revealed a bug in my register struct generator code (the maple_if-related registers were not at the correct offsets) - it validates my understanding about endianness-swapping between the maple bus and the SH4
99 lines
2.9 KiB
C++
99 lines
2.9 KiB
C++
#include <cstdint>
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#include <bit>
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#include "sh7091.h"
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#include "sh7091_bits.h"
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#include "systembus.h"
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#include "systembus_bits.h"
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#include "maple_bits.h"
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#include "maple.h"
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#define AP__PO__A (0b00 << 6)
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#define AP__PO__B (0b01 << 6)
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#define AP__PO__C (0b10 << 6)
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#define AP__PO__D (0b11 << 6)
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#define AP__DE__DEVICE (1 << 5)
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#define AP__DE__EXPANSION_DEVICE (0 << 5)
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#define AP__DE__PORT (0 << 5)
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#define AP__LM(reg) ((reg) & 0b11111)
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// 2.6.8 "Peripheral Data Transfers"
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// 5 "User Interface"; page 269
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#define HOST_INSTRUCTION__END_FLAG (1 << 31)
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#define HOST_INSTRUCTION__PORT_SELECT__A (0b00 << 16)
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#define HOST_INSTRUCTION__PORT_SELECT__B (0b01 << 16)
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#define HOST_INSTRUCTION__PORT_SELECT__C (0b10 << 16)
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#define HOST_INSTRUCTION__PORT_SELECT__D (0b11 << 16)
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#define HOST_INSTRUCTION__TRANSFER_LENGTH(n) (((n) & 0xff) << 0)
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template <int N>
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struct maple_host_command {
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uint32_t host_instruction;
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uint32_t receive_data_storage_address;
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uint32_t protocol_data[N];
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};
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void maple_init_host_command(uint32_t * buf, uint32_t * receive_address)
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{
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auto command = reinterpret_cast<maple_host_command<1> *>(buf);
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command->host_instruction = HOST_INSTRUCTION__END_FLAG
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| HOST_INSTRUCTION__PORT_SELECT__A
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| HOST_INSTRUCTION__TRANSFER_LENGTH(0); // 4 bytes
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command->receive_data_storage_address = reinterpret_cast<uint32_t>(receive_address);
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uint32_t command_code = 0x01; // 'Device Request'
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uint32_t destination_ap = AP__DE__DEVICE | AP__PO__A;
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uint32_t source_ap = AP__PO__A;
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uint32_t data_size = 0;
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// maple bus is big endian
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command->protocol_data[0] = std::byteswap( (command_code << 24)
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| (destination_ap << 16)
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| (source_ap << 8)
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| (data_size << 0));
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}
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void maple_dma_start(uint32_t * command_buf)
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{
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sh7091.DMAC.DMAOR = DMAOR__DDT /* on-demand data transfer mode */
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| DMAOR__PR__CH2_CH0_CH1_CH3 /* priority mode; CH2 > CH0 > CH1 > CH3 */
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| DMAOR__DME; /* DMAC master enable */
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// clear maple-DMA end status
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system.ISTNRM = ISTNRM__END_OF_DMA_MAPLE_DMA;
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// disable maple-DMA
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maple_if.MDEN = mden::dma_enable::abort;
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volatile uint32_t _dummy = maple_if.MDST;
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(void)_dummy;
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// 20nsec * 0xc350 = 1ms
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constexpr uint32_t one_msec = 0xc350;
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maple_if.MSYS = msys::time_out_counter(one_msec)
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| msys::sending_rate::_2M;
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maple_if.MDTSEL = mdtsel::trigger_select::software_initiation;
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/* top address: the first/lowest address
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bottom address: the last/highest address */
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maple_if.MDAPRO = mdapro::security_code
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| mdapro::top_address(0x00)
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| mdapro::bottom_address(0x7f);
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maple_if.MDSTAR = mdstar::table_address(reinterpret_cast<uint32_t>(command_buf));
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maple_if.MDEN = mden::dma_enable::enable;
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maple_if.MDST = mdst::start_status::start;
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// wait for completion
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while ((system.ISTNRM & ISTNRM__END_OF_DMA_MAPLE_DMA) == 0);
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system.ISTNRM = ISTNRM__END_OF_DMA_MAPLE_DMA;
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}
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