Successfully tested on real hardware on multiple optimization levels. I knew in the previous commit that __attribute__((aligned(32))) did not actually align to 32-bytes. However, at -Os specifically, and only with that exact code, GCC was coincidentally generating a 32-byte alignment. When the code or optimization level changed, this changed the alignment of the "scene" buffer, which caused CH2-DMA to perform incomplete copies of the TA parameters, which in turn variously caused the TA to generate incomplete/nonsensical/nonexistent object lists. This also fixes an unrelated issue with the background ISP/TSP parameters. This "worked" in flycast but not on real hardware by complete accident (a coincidence of the specific timing that the ISP/TSP parameters are read in each Dreamcast implementation). The issue is that the TSP parameters are 60 bytes long, which is greater than the 32 bytes were previously being allocated. After changing the allocation to 64 bytes, the background color is now drawn on real hardware as expected. In addition, though this did not cause issues yet, I corrected the length of p1ram/p2ram in the linker script, to prevent future issues where GCC's memory allocations wrap around past the end of the system memory address space.
127 lines
2.9 KiB
C++
127 lines
2.9 KiB
C++
#include <stdint.h>
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#include "memorymap.h"
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#include "sh7091.h"
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#include "sh7091_bits.h"
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#include "holly.h"
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#include "holly/core.h"
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#include "holly/core_bits.h"
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#include "holly/ta_fifo_polygon_converter.h"
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#include "systembus.h"
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#include "cache.h"
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#include "load.h"
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#include "vga.h"
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#include "rgb.h"
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#include "scene.h"
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extern uint32_t __bss_link_start __asm("__bss_link_start");
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extern uint32_t __bss_link_end __asm("__bss_link_end");
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void serial()
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{
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sh7091.SCIF.SCSCR2 = 0;
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sh7091.SCIF.SCSMR2 = 0;
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sh7091.SCIF.SCBRR2 = 1; // 520833.3
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sh7091.SCIF.SCFCR2 = SCFCR2__TFRST | SCFCR2__RFRST;
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// tx/rx trigger on 1 byte
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sh7091.SCIF.SCFCR2 = 0;
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sh7091.SCIF.SCSPTR2 = 0;
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sh7091.SCIF.SCLSR2 = 0;
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sh7091.SCIF.SCSCR2 = SCSCR2__TE | SCSCR2__RE;
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}
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inline void serial_char(const char c)
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{
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// wait for transmit fifo to become empty
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while ((sh7091.SCIF.SCFSR2 & SCFSR2__TDFE) == 0);
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sh7091.SCIF.SCFTDR2 = static_cast<uint8_t>(c);
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}
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void serial_string(const char * s)
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{
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while (*s != '\0') {
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serial_char(*s++);
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}
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}
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/* must be aligned to 32-bytes for DMA transfer */
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// the aligned(32) attribute does not actually align to 32 bytes; gcc is the best compiler.
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// `+ 32` to allow for repositioning _scene to an actual 32-byte alignment.
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uint32_t __attribute__((aligned(32))) _scene[((32 * 5) + 32) / 4];
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uint32_t * align_32byte(uint32_t * mem)
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{
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return reinterpret_cast<uint32_t *>(((reinterpret_cast<uint32_t>(_scene) + 31) & ~31));
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}
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extern "C"
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void main()
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{
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cache_init();
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// clear BSS
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uint32_t * start = &__bss_link_start;
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uint32_t * end = &__bss_link_end;
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while (start < end) {
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*start++ = 0;
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}
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//serial();
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vga();
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v_sync_in();
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volatile uint16_t * framebuffer = reinterpret_cast<volatile uint16_t *>(&texture_memory[0]);
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for (int y = 0; y < 480; y++) {
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for (int x = 0; x < 640; x++) {
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struct hsv hsv = {(y * 255) / 480, 255, 255};
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struct rgb rgb = hsv_to_rgb(hsv);
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framebuffer[y * 640 + x] = ((rgb.r >> 3) << 11) | ((rgb.g >> 2) << 5) | ((rgb.b >> 3) << 0);
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}
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}
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holly.SOFTRESET = softreset::pipeline_soft_reset
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| softreset::ta_soft_reset;
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holly.SOFTRESET = 0;
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system.LMMODE0 = 1;
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system.LMMODE1 = 1;
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v_sync_out();
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v_sync_in();
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core_init();
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core_init_texture_memory();
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int frame = 0;
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// the address of `scene` must be a multiple of 32 bytes
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// this is mandatory for ch2-dma to the ta fifo polygon converter
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uint32_t * scene = align_32byte(_scene);
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if ((reinterpret_cast<uint32_t>(scene) & 31) != 0) {
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serial_string("unaligned\n");
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while(1);
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}
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while (true) {
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v_sync_out();
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v_sync_in();
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ta_polygon_converter_init();
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uint32_t ta_parameter_count = scene_transform(&scene[0]);
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uint32_t ta_parameter_size = ta_parameter_count * 32; /* 32 bytes per parameter */
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ta_polygon_converter_transfer(&scene[0], ta_parameter_size);
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ta_wait_opaque_list();
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core_start_render(frame);
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frame = !frame;
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}
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}
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