Zack Buhman
bcaa9789cf
The previous texture_memory_alloc.hpp was written based on an incorrect understanding of the "32-bit" and "64-bit" texture memory address mapping. The primary motivation is to rearrange the texture memory address map so that "textures" (64-bit access) do not overlap with 32-bit accesses, such as REGION_BASE or PARAM_BASE.
71 lines
1.2 KiB
Plaintext
71 lines
1.2 KiB
Plaintext
OUTPUT_FORMAT("elf32-shl", "elf32-shl", "elf32-shl")
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MEMORY
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{
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p1ram : ORIGIN = 0x8c010000, LENGTH = 0xff0000
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p2ram : ORIGIN = 0xac010000, LENGTH = 0xff0000
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ldram : ORIGIN = 0x8cfff000, LENGTH = 0x1000
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}
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SECTIONS
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{
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. = ORIGIN(p2ram);
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.text.startup ALIGN(4) : SUBALIGN(4)
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{
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KEEP(*(.text.start))
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*(.text.startup.*)
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. = ALIGN(4);
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} > p2ram AT> p2ram
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.ctors ALIGN(4) : SUBALIGN(4)
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{
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KEEP(*(.ctors))
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KEEP(*(.ctors.*))
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. = ALIGN(4);
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} > p2ram AT> p2ram
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. = ORIGIN(ldram);
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.text ALIGN(4) : SUBALIGN(4)
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{
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*(.text.*)
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*(.text)
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. = ALIGN(4);
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} > ldram AT> p2ram
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.data ALIGN(4) : SUBALIGN(4)
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{
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*(.data)
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*(.data.*)
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. = ALIGN(4);
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} > ldram AT> p2ram
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.rodata ALIGN(4) : SUBALIGN(4)
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{
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*(.rodata)
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*(.rodata.*)
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. = ALIGN(4);
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} > ldram AT> p2ram
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.bss ALIGN(4) (NOLOAD) : SUBALIGN(4)
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{
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*(.bss)
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*(.bss.*)
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*(COMMON)
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. = ALIGN(4);
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} > ldram
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.text.vbr ALIGN(4) : SUBALIGN(4)
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{
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KEEP(*(.vbr.100))
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. = ALIGN(0x300);
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KEEP(*(.vbr.400))
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. = ALIGN(0x200);
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KEEP(*(.vbr.600))
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} > p1ram
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INCLUDE "debug.lds"
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}
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__stack_reservation = 0x0000;
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INCLUDE "symbols.lds"
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INCLUDE "addresses.lds"
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