Zack Buhman
73a685face
Real hardware does not support TIMA reads--SCIPD is the correct way to achieve this.
253 lines
9.0 KiB
Python
253 lines
9.0 KiB
Python
import sys
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from dataclasses import dataclass
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from collections import defaultdict
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from generate import renderer
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from csv_input import read_input
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@dataclass
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class Part:
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index: int
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address: int
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register_bits: tuple[int, int]
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argument_bits: tuple[int, int]
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@dataclass
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class Register:
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name: str
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rw: set[str]
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parts: list[Part]
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def parse_slice(s):
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if '-' in s:
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start0, end0 = s.split('-')
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start, end = int(start0, 10), int(end0, 10)
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assert start > end, s
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return start, end
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else:
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start = int(s, 10)
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return start, start
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def slice_bits(s):
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start, end = s
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return set(range(start, end+1))
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def parse_row(row):
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address = int(row["address"], 16)
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name = row["name"]
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part_index0 = row["part"].strip()
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part_index = int(part_index0, 10) if part_index0 else 0
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register_bits = parse_slice(row["register_bits"])
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if row["argument_bits"].strip():
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argument_bits = parse_slice(row["argument_bits"])
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assert len(slice_bits(argument_bits)) == len(slice_bits(register_bits)), row
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else:
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start, end = register_bits
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argument_bits = (start - end, 0)
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part = Part(
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part_index,
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address,
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register_bits,
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argument_bits,
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)
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rw = set(row["rw"])
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return name, rw, part
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def group_parts(rows, address_increment):
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by_name: dict[str, Register] = {}
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register_bit_alloc: dict[int, set[int]] = defaultdict(set)
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argument_bit_alloc: dict[str, set[int]] = defaultdict(set)
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register_order = []
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addresses = []
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last_address = 0
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parts_by_register_name: dict[str, list] = defaultdict(list)
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for row in rows:
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name, rw, part = parse_row(row)
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if rw == set():
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continue
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assert part.address >= last_address, row
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assert part.address % address_increment == 0, row
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last_address = part.address
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if part.address not in set(a[0] for a in addresses):
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addresses.append((part.address, [(name, part.index)]))
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else:
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assert addresses[-1][0] == part.address
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addresses[-1][1].append((name, part.index))
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bits = slice_bits(part.register_bits)
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assert bits.intersection(register_bit_alloc[part.address]) == set(), row
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register_bit_alloc[part.address] |= bits
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bits = slice_bits(part.argument_bits)
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assert bits.intersection(argument_bit_alloc[name]) == set(), row
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argument_bit_alloc[part.address] |= bits
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if name not in by_name:
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assert part.index == 0, row
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register = Register(name, rw, [part])
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by_name[name] = register
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register_order.append(register)
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else:
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assert len(by_name[name].parts) == part.index
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by_name[name].parts.append(part)
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parts_by_register_name[name].append(part.index)
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return addresses, register_order, parts_by_register_name
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def format_reg(address):
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return f"reg_{address:04x}"
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def format_reg_friendly_name(names, parts_by_register_name):
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return "_".join(
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name.lower() if len(parts_by_register_name[name]) == 1
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else f"{name.lower()}{part_index}"
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for name, part_index in names
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)
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def render_struct_fields(struct_size, addresses, address_increment, c_type, c_type_size, parts_by_register_name):
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assert address_increment >= c_type_size
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assert address_increment % c_type_size == 0
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next_address = None
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pad_index = 0
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for address, names in addresses:
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if next_address is None:
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next_address = address
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if address != next_address:
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assert address > next_address, (address, next_address)
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padding = (address - next_address) // c_type_size
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yield f"const {c_type} _pad{pad_index}[{padding}];"
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pad_index += 1
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# render the actual field
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yield "union {"
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yield f"{c_type} {format_reg(address)};"
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yield f"{c_type} {format_reg_friendly_name(names, parts_by_register_name)};"
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yield "};"
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if c_type_size < address_increment:
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padding = (address_increment - c_type_size) // c_type_size
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yield f"const {c_type} _pad{pad_index}[{padding}];"
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pad_index += 1
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next_address = address + address_increment
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if struct_size is not None:
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assert struct_size % address_increment == 0
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assert struct_size >= next_address
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if struct_size > next_address:
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padding = (struct_size - next_address) // c_type_size
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yield f"const {c_type} _pad{pad_index}[{padding}];"
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def render_struct_static_assertions(struct_name, struct_size, addresses, address_increment):
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first_address = addresses[0][0]
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last_address = addresses[-1][0]
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if struct_size is None:
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struct_size = last_address + address_increment
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yield f"static_assert((sizeof ({struct_name})) == {hex(struct_size)} - {hex(first_address)});"
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for address, _ in addresses:
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yield f"static_assert((offsetof ({struct_name}, {format_reg(address)})) == {hex(address)} - {hex(first_address)});"
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def mask_from_bits(bit_slice):
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h, l = bit_slice
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mask = 2 ** ((h - l) + 1) - 1
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return mask
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def part_get_expression(part, value=None):
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_, reg_end = part.register_bits
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_, arg_end = part.argument_bits
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arg_mask = mask_from_bits(part.argument_bits)
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value_expression = format_reg(part.address) if value is None else value
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return f"(static_cast<uint32_t>(({value_expression} >> {reg_end}) & {hex(arg_mask)}) << {arg_end})"
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def part_set_expression(part):
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_, reg_end = part.register_bits
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_, arg_end = part.argument_bits
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arg_mask = mask_from_bits(part.argument_bits)
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expression = f"(((v >> {arg_end}) & {hex(arg_mask)}) << {reg_end})"
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return expression
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def part_set_statement(addresses_dict, c_type_real_size, part):
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_, reg_end = part.register_bits
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assignment = f"{format_reg(part.address)} = {part_set_expression(part)}"
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if len(addresses_dict[part.address]) > 1:
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reg_mask = mask_from_bits(part.register_bits) << reg_end
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inverse_mask = (~reg_mask) & ((2 ** (c_type_real_size * 8)) - 1)
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assignment += f" | ({format_reg(part.address)} & {hex(inverse_mask)});"
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else:
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assignment += ";"
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return assignment
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def render_struct_accessors(addresses_dict, c_type, c_type_real_size, registers):
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for register in registers:
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yield f"uint32_t {register.name}() const"
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yield "{"
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get_expression = " | ".join(map(part_get_expression, register.parts))
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yield f"return {get_expression};"
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yield "}"
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yield f"void {register.name}(const uint32_t v)"
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yield "{"
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for part in register.parts:
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yield part_set_statement(addresses_dict, c_type_real_size, part)
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yield "}"
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yield ""
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def render_bits(addresses_dict, registers, parts_by_register_name):
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parts_by_address = defaultdict(list)
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for register in registers:
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for part in register.parts:
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parts_by_address[part.address].append((register, part))
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for address, names in addresses_dict.items():
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namespace = format_reg_friendly_name(names, parts_by_register_name)
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yield f"namespace {namespace} {{"
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for register, part in parts_by_address[address]:
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if 'w' in register.rw:
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arg = "v"
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expression = part_set_expression(part)
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elif 'r' in register.rw:
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arg = "reg"
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expression = part_get_expression(part, arg)
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else:
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continue
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yield f"constexpr uint32_t {register.name}(const uint32_t {arg}) {{ return {expression}; }}";
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yield "}"
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def render_struct(struct_name, struct_size, addresses, address_increment, c_type, c_type_size, c_type_real_size, registers, parts_by_register_name):
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yield f"struct {struct_name} {{"
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yield from render_struct_fields(struct_size, addresses, address_increment, c_type, c_type_size, parts_by_register_name)
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yield ""
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addresses_dict = dict(addresses)
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yield from render_struct_accessors(addresses_dict, c_type, c_type_real_size, registers)
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yield "};"
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yield from render_struct_static_assertions(struct_name, struct_size, addresses, address_increment)
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yield ""
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yield f"namespace aica {{"
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yield from render_bits(addresses_dict, registers, parts_by_register_name)
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yield "}"
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def header():
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yield '#include <stdint.h>'
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yield '#include <stddef.h>'
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yield ""
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yield '#include "type.hpp"'
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yield ""
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if __name__ == "__main__":
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input_file = sys.argv[1]
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struct_name = sys.argv[2]
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struct_size = int(sys.argv[3], 16) if len(sys.argv) > 3 else None
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rows = read_input(input_file)
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address_increment = 4
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c_type = "reg32"
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c_type_size = 4
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c_type_real_size = 2
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addresses, registers, parts_by_register_name = group_parts(rows, address_increment)
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render, out = renderer()
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render(header())
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render(render_struct(struct_name, struct_size, addresses, address_increment, c_type, c_type_size, c_type_real_size, registers, parts_by_register_name))
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sys.stdout.write(out.getvalue())
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