Zack Buhman
bcaa9789cf
The previous texture_memory_alloc.hpp was written based on an incorrect understanding of the "32-bit" and "64-bit" texture memory address mapping. The primary motivation is to rearrange the texture memory address map so that "textures" (64-bit access) do not overlap with 32-bit accesses, such as REGION_BASE or PARAM_BASE.
37 lines
1.0 KiB
C++
37 lines
1.0 KiB
C++
#pragma once
|
|
|
|
#include "sh7091.hpp"
|
|
#include "memorymap.hpp"
|
|
|
|
static inline void sq_transfer_32byte(volatile void * dst)
|
|
{
|
|
// dst typically 0x10000000 (ta polygon converter)
|
|
sh7091.CCN.QACR0 = ((reinterpret_cast<uint32_t>(dst) >> 26) & 0b111) << 2;
|
|
|
|
// start 32-byte transfer from store queue 0 (SQ0) to QACR0
|
|
asm volatile ("pref @%0"
|
|
: // output
|
|
: "r" (&store_queue[0]) // input
|
|
: "memory");
|
|
}
|
|
|
|
|
|
static inline void sq_transfer_64byte(volatile void * dst)
|
|
{
|
|
// dst typically 0x10000000 (ta polygon converter)
|
|
sh7091.CCN.QACR0 = ((reinterpret_cast<uint32_t>(dst) >> 26) & 0b111) << 2;
|
|
sh7091.CCN.QACR1 = ((reinterpret_cast<uint32_t>(dst) >> 26) & 0b111) << 2;
|
|
|
|
// start 32-byte transfer from store queue 0 (SQ0) to QACR0
|
|
asm volatile ("pref @%0"
|
|
: // output
|
|
: "r" (&store_queue[0]) // input
|
|
: "memory");
|
|
|
|
// start 32-byte transfer from store queue 1 (SQ1) to QACR1
|
|
asm volatile ("pref @%0"
|
|
: // output
|
|
: "r" (&store_queue[8]) // input
|
|
: "memory");
|
|
}
|