173 lines
6.6 KiB
C++
173 lines
6.6 KiB
C++
#include <cstdint>
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#include "systembus.hpp"
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#include "systembus_bits.hpp"
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#include "sh7091/sh7091.hpp"
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#include "sh7091/sh7091_bits.hpp"
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#include "sh7091/serial.hpp"
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#include "core_bits.hpp"
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#include "ta_bits.hpp"
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#include "holly.hpp"
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#include "texture_memory_alloc.hpp"
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#include "ta_fifo_polygon_converter.hpp"
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void ta_polygon_converter_init(uint32_t opb_total_size, // for one tile, for all render passes
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uint32_t ta_alloc,
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uint32_t tile_width, // in tile units (e.g: (640 / 32))
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uint32_t tile_height) // in tile units (e.g: (480 / 32))
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{
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// opb_size is the total size of all OPBs for all passes
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const uint32_t ta_next_opb_offset = opb_total_size * tile_width * tile_height;
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holly.SOFTRESET = softreset::ta_soft_reset;
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holly.SOFTRESET = 0;
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holly.TA_GLOB_TILE_CLIP = ta_glob_tile_clip::tile_y_num(tile_height - 1)
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| ta_glob_tile_clip::tile_x_num(tile_width - 1);
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holly.TA_ALLOC_CTRL = ta_alloc_ctrl::opb_mode::increasing_addresses
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| ta_alloc;
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holly.TA_ISP_BASE = texture_memory_alloc::isp_tsp_parameters.start;
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holly.TA_ISP_LIMIT = texture_memory_alloc::isp_tsp_parameters.end; // the end of isp_tsp_parameters
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holly.TA_OL_BASE = texture_memory_alloc::object_list.start;
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holly.TA_OL_LIMIT = texture_memory_alloc::object_list.end; // the end of the object_list
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holly.TA_NEXT_OPB_INIT = texture_memory_alloc::object_list.start + ta_next_opb_offset;
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holly.TA_LIST_INIT = ta_list_init::list_init;
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uint32_t _dummy_read = holly.TA_LIST_INIT;
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(void)_dummy_read;
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}
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void ta_polygon_converter_init2(uint32_t isp_tsp_parameters_start,
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uint32_t isp_tsp_parameters_end,
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uint32_t object_list_start,
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uint32_t object_list_end,
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uint32_t opb_total_size, // for one tile, for all render passes
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uint32_t ta_alloc,
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uint32_t tile_width, // in tile units (e.g: (640 / 32))
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uint32_t tile_height) // in tile units (e.g: (480 / 32))
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{
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// opb_size is the total size of all OPBs for all passes
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const uint32_t ta_next_opb_offset = opb_total_size * tile_width * tile_height;
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holly.SOFTRESET = softreset::ta_soft_reset;
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holly.SOFTRESET = 0;
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holly.TA_GLOB_TILE_CLIP = ta_glob_tile_clip::tile_y_num(tile_height - 1)
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| ta_glob_tile_clip::tile_x_num(tile_width - 1);
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holly.TA_ALLOC_CTRL = ta_alloc_ctrl::opb_mode::increasing_addresses
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| ta_alloc;
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holly.TA_ISP_BASE = isp_tsp_parameters_start;
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holly.TA_ISP_LIMIT = isp_tsp_parameters_end; // the end of isp_tsp_parameters
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holly.TA_OL_BASE = object_list_start;
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holly.TA_OL_LIMIT = object_list_end; // the end of the object_list
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holly.TA_NEXT_OPB_INIT = object_list_start + ta_next_opb_offset;
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holly.TA_LIST_INIT = ta_list_init::list_init;
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uint32_t _dummy_read = holly.TA_LIST_INIT;
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(void)_dummy_read;
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}
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void ta_polygon_converter_cont(uint32_t ol_base_offset,
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uint32_t ta_alloc)
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{
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holly.TA_ALLOC_CTRL = ta_alloc_ctrl::opb_mode::increasing_addresses
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| ta_alloc;
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holly.TA_OL_BASE = texture_memory_alloc::object_list.start + ol_base_offset;
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holly.TA_LIST_CONT = ta_list_cont::list_cont;
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uint32_t _dummy_read = holly.TA_LIST_CONT;
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(void)_dummy_read;
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}
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void ta_polygon_converter_transfer(volatile uint32_t const * const buf, uint32_t size)
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{
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/* wait for previous transfer to complete (if any) */
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//while ((system.C2DST & C2DST__STATUS) != 0); /* 1 == transfer is in progress */
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/* CHCR2__TE can be reset even if there is no in-progress transfer. Despite
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DCDBSysArc990907E's claim, it does not appear to be useful to check TE. */
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//while ((sh7091.DMAC.CHCR2 & CHCR2__TE) == 0); /* 1 == all transfers are completed */
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/* "Write back" the entire buffer to physical memory.
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This is required on real hardware if CCR__CB is enabled, and `buf` is in a
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cacheable area (e.g: system memory access via 0x8c00_0000).*/
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for (uint32_t i = 0; i < size / 32; i++) {
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asm volatile ("ocbwb @%0"
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: // output
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: "r" (&buf[(i * 32) / 4]) // input
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);
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}
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// this dummy read appears to be required on real hardware.
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volatile uint32_t _dummy = sh7091.DMAC.CHCR2;
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(void)_dummy;
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using namespace dmac;
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/* start a new CH2-DMA transfer from "system memory" to "TA FIFO polygon converter" */
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sh7091.DMAC.CHCR2 = 0; /* disable DMA channel */
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sh7091.DMAC.SAR2 = reinterpret_cast<uint32_t>(&buf[0]); /* start address, must be aligned to a CHCHR__TS-sized (32-byte) boundary */
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sh7091.DMAC.DMATCR2 = dmatcr::transfer_count(size / 32); /* transfer count, in CHCHR__TS-sized (32-byte) units */
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sh7091.DMAC.CHCR2 = chcr::dm::destination_address_fixed
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| chcr::sm::source_address_incremented
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| chcr::rs::resource_select(0b0010) /* external request, single address mode;
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external address space → external device */
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| chcr::tm::cycle_burst_mode /* transmit mode */
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| chcr::ts::_32_byte /* transfer size */
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| chcr::de::channel_operation_enabled;
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sh7091.DMAC.DMAOR = dmaor::ddt::on_demand_data_transfer_mode /* on-demand data transfer mode */
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| dmaor::pr::ch2_ch0_ch1_ch3 /* priority mode; CH2 > CH0 > CH1 > CH3 */
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| dmaor::dme::operation_enabled_on_all_channels; /* DMAC master enable */
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system.C2DSTAT = c2dstat::texture_memory_start_address(0x10000000); /* CH2-DMA destination address */
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system.C2DLEN = c2dlen::transfer_length(size); /* CH2-DMA length (must be a multiple of 32) */
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system.C2DST = 1; /* CH2-DMA start (an 'external' request from SH7091's perspective) */
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// wait for ch2-dma completion
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while ((system.ISTNRM & istnrm::end_of_dma_ch2_dma) == 0);
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// reset ch2-dma interrupt status
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system.ISTNRM = istnrm::end_of_dma_ch2_dma;
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}
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void ta_wait_opaque_list()
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{
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while ((system.ISTNRM & istnrm::end_of_transferring_opaque_list) == 0) {
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if (system.ISTERR) {
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//serial::string("ta ISTERR: ");
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//serial::integer<uint32_t>(system.ISTERR);
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}
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};
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system.ISTNRM = istnrm::end_of_transferring_opaque_list;
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}
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void ta_wait_opaque_modifier_volume_list()
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{
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while ((system.ISTNRM & istnrm::end_of_transferring_opaque_modifier_volume_list) == 0);
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system.ISTNRM = istnrm::end_of_transferring_opaque_modifier_volume_list;
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}
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void ta_wait_translucent_list()
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{
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while ((system.ISTNRM & istnrm::end_of_transferring_translucent_list) == 0);
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system.ISTNRM = istnrm::end_of_transferring_translucent_list;
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}
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void ta_wait_punch_through_list()
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{
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while ((system.ISTNRM & istnrm::end_of_transferring_punch_through_list) == 0);
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system.ISTNRM = istnrm::end_of_transferring_punch_through_list;
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}
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