112 lines
4.2 KiB
C++
112 lines
4.2 KiB
C++
#pragma once
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#include "sh7091/sh7091.hpp"
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#include "sh7091/sh7091_bits.hpp"
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/*
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(4) Channels 1 and 3 can be used in the following manner:
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The allowed transfer data length (8/16/32 bits, 32 bytes) depends on the
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transfer area. The 64-bit transfer data length specification is permitted only for
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system memory.
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Address mode: Only dual address mode is permitted.
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Transfer initiation request: SCIF interrupt and auto request are permitted.
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Bus mode: Only cycle steal mode is permitted.
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DMA end interrupt: Can be used.
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*/
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/*
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After the desired transfer conditions have been set in the DMA source address register (SAR),
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DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA
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channel control register (CHCR), and DMA operation register (DMAOR), the DMAC transfers
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data according to the following procedure:
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1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0).
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2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one
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transfer unit of data (determined by the setting of TS2–TS0). In auto-request mode, the transfer
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begins automatically when the DE bit and DME bit are set to 1. The DMATCR value is
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decremented by 1 for each transfer. The actual transfer flow depends on the address mode and
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bus mode.
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3. When the specified number of transfers have been completed (when the DMATCR value
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reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DMTE
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interrupt request is sent to the CPU.
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4. If a DMAC address error or NMI interrupt occurs, the transfer is suspended. Transfer is also
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suspended when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In the event
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of an address error, a DMAE interrupt request is forcibly sent to the CPU.
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*/
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namespace serial {
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static void recv_dma(uint32_t destination_address, uint32_t length)
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{
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using namespace dmac;
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/* Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) */
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// RS: SCFRDR2 (SCIF receive-data-full transfer request)
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// RS: 0b1011
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// SAR1 = SCFRDR2
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// DAR1 = (address)
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// DMATCR1 = (transfer count, 24 bit)
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sh7091.DMAC.CHCR1 = 0;
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sh7091.DMAC.SAR1 = reinterpret_cast<uint32_t>(&sh7091.SCIF.SCFRDR2);
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sh7091.DMAC.DAR1 = destination_address;
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sh7091.DMAC.DMATCR1 = length & 0x00ff'ffff;
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// SSA (only used for PCMCIA)
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// STC (only used for PCMCIA)
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// DSA (only used for PCMCIA)
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// DTC (only used for PCMCIA)
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// DS (only used for DREQ requests)
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// RL (only used for DRAK requests)
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// AM (only used for DACK requests)
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// AL (only used for DACK requests)
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// DM incremented
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// SM fixed
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// RS SCIF
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// TM cycle steal
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// TS byte?
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// IE interrupt enable
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// TE transfer end (status bit)
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// DE channel enable
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sh7091.DMAC.CHCR1 = chcr::dm::destination_address_incremented
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| chcr::sm::source_address_fixed
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| chcr::rs::resource_select(0b1011) /* SCFRDR2 → external address space */
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| chcr::tm::cycle_steal_mode /* transmit mode */
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| chcr::ts::_8_bit /* transfer size */
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//| chcr::ie::interrupt_request_generated
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| chcr::de::channel_operation_enabled;
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sh7091.DMAC.DMAOR = dmaor::ddt::on_demand_data_transfer_mode /* on-demand data transfer mode */
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| dmaor::pr::ch2_ch0_ch1_ch3 /* priority mode; CH2 > CH0 > CH1 > CH3 */
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| dmaor::dme::operation_enabled_on_all_channels; /* DMAC master enable */
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}
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static void send_dma(uint32_t source_address, uint32_t length)
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{
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using namespace dmac;
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sh7091.DMAC.CHCR1 = 0;
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sh7091.DMAC.SAR1 = source_address;
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sh7091.DMAC.DAR1 = reinterpret_cast<uint32_t>(&sh7091.SCIF.SCFTDR2);
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sh7091.DMAC.DMATCR1 = length & 0x00ff'ffff;
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sh7091.DMAC.CHCR1 = chcr::dm::destination_address_fixed
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| chcr::sm::source_address_incremented
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| chcr::rs::resource_select(0b1010) /* external address space → SCFTDR2 */
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| chcr::tm::cycle_steal_mode /* transmit mode */
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| chcr::ts::_8_bit /* transfer size */
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//| chcr::ie::interrupt_request_generated
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| chcr::de::channel_operation_enabled;
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}
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}
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