Zack Buhman
329ada55f1
This was used to troubleshoot video output and framebuffer configuration registers.
67 lines
1.5 KiB
C
67 lines
1.5 KiB
C
#include <stdint.h>
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#include "cache.h"
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#include "load.h"
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#include "sh7091.h"
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#include "sh7091_bits.h"
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extern uint32_t __bss_link_start __asm("__bss_link_start");
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extern uint32_t __bss_link_end __asm("__bss_link_end");
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void serial()
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{
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SH7091.SCIF.SCSCR2 = 0;
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SH7091.SCIF.SCSMR2 = 0;
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SH7091.SCIF.SCBRR2 = 12;
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#define SCFCR2__TFRST (1 << 2)
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#define SCFCR2__RFRST (1 << 1)
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SH7091.SCIF.SCFCR2 = SCFCR2__TFRST | SCFCR2__RFRST;
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// tx/rx trigger on 1 byte
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SH7091.SCIF.SCFCR2 = 0;
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SH7091.SCIF.SCSPTR2 = 0;
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SH7091.SCIF.SCLSR2 = 0;
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#define SCSCR2__TE (1 << 5)
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#define SCSCR2__RE (1 << 4)
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SH7091.SCIF.SCSCR2 = SCSCR2__TE | SCSCR2__RE;
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}
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void main()
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{
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cache_init();
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// clear BSS
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uint32_t * start = &__bss_link_start;
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uint32_t * end = &__bss_link_end;
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while (start < end) {
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*start++ = 0;
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}
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serial();
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load_init();
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while (1) {
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#define SCFSR2__ER (1 << 7) /* read error */
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#define SCFSR2__TEND (1 << 6) /* transmit end */
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#define SCFSR2__TFDE (1 << 5) /* transmit fifo data empty */
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#define SCFSR2__BRK (1 << 4) /* break detect */
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#define SCFSR2__FER (1 << 3) /* framing error */
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#define SCFSR2__PER (1 << 2) /* parity error */
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#define SCFSR2__RDF (1 << 1) /* receive FIFO data full */
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#define SCFSR2__DR (1 << 0) /* receive data ready */
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while ((SH7091.SCIF.SCFSR2 & SCFSR2__RDF) == 0) {
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// wait
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}
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while ((SH7091.SCIF.SCFDR2 & 0b11111) > 0) {
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uint8_t c = SH7091.SCIF.SCFRDR2;
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load_recv(c);
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}
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SH7091.SCIF.SCFSR2 = SH7091.SCIF.SCFSR2 & (~SCFSR2__RDF);
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}
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}
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