maple: add maple_bus_ft6

headers.mk

@@ -47,6 +47,15 @@ maple/maple_bus_commands.hpp: regs/maple_bus_commands.csv regs/gen/maple_bus_com
 maple/maple_bus_bits.hpp: regs/maple_bus_bits.csv regs/gen/core_bits.py
 	python regs/gen/core_bits.py $< > $@
 
+maple/maple_bus_ft0.hpp: regs/maple_bus_ft0.csv regs/gen/maple_data_format.py
+	python regs/gen/maple_data_format.py $< > $@
+
+maple/maple_bus_ft6.hpp: regs/maple_bus_ft6.csv regs/gen/maple_data_format.py
+	python regs/gen/maple_data_format.py $< > $@
+
+maple/maple_bus_ft8.hpp: regs/maple_bus_ft8.csv regs/gen/maple_data_format.py
+	python regs/gen/maple_data_format.py $< > $@
+
 # AICA
 
 aica/aica_channel.hpp: regs/aica_channel_data.csv regs/gen/aica.py

maple/maple_bus_ft0.hpp

@@ -62,5 +62,6 @@ namespace ft0 {
     };
     static_assert((sizeof (struct data_format)) == 8);
   }
+
 }
 

regs/gen/maple_data_format.py

@@ -109,8 +109,10 @@ def render_format(format):
             yield f"uint8_t {field_name};"
         elif len(subfields) == 2:
             yield f"uint16_t {field_name};"
+        elif len(subfields) == 6:
+            yield f"uint8_t {field_name}[6];"
         else:
-            assert False, len(subfields)
+            assert False, (len(subfields), field_name)
 
     yield "};"
     assert format.size % 4 == 0, format.size