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base: bilbo:1295eed1bb01e1dfbd70fb764656bfdc66b17c74
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bilbo:main
bilbo:long-samples
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compare: bilbo:5eedad7ff33920b77ed7bf6629f1c281de415f7a
Branches Tags
bilbo:main
bilbo:long-samples

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12 changed files with 63 additions and 88 deletions
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26
regs/isp_tsp.csv
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@ -106,21 +106,21 @@
,,,,,,
"texture_control_word",,30,"vq_compressed",1,,
,,,,,,
"texture_control_word","pixel_format","29-27",1555,0,,
"texture_control_word","pixel_format","29-27",565,1,,
"texture_control_word","pixel_format","29-27",4444,2,,
"texture_control_word","pixel_format","29-27","yuv422",3,,
"texture_control_word","pixel_format","29-27","bump_map",4,,
"texture_control_word","pixel_format","29-27","4bpp_palette",5,,
"texture_control_word","pixel_format","29-27","8bpp_palette",6,,
"tsp_instruction_word","pixel_format","29-27",1555,0,,
"tsp_instruction_word","pixel_format","29-27",565,1,,
"tsp_instruction_word","pixel_format","29-27",4444,2,,
"tsp_instruction_word","pixel_format","29-27","yuv422",3,,
"tsp_instruction_word","pixel_format","29-27","bump_map",4,,
"tsp_instruction_word","pixel_format","29-27","4bpp_palette",5,,
"tsp_instruction_word","pixel_format","29-27","8bpp_palette",6,,
,,,,,,
"texture_control_word","scan_order",26,"twiddled",0,,
"texture_control_word","scan_order",26,"non_twiddled",1,,
"tsp_instruction_word","scan_order",26,"twiddled",0,,
"tsp_instruction_word","scan_order",26,"non_twiddled",1,,
,,,,,,
"texture_control_word",,"26-21","palette_selector4",,"0x3f",
"tsp_instruction_word",,"26-21","palette_selector4",,"0x3f",
,,,,,,
"texture_control_word",,"26-25","palette_selector8",,"0x3",
"tsp_instruction_word",,"26-25","palette_selector8",,"0x3",
,,,,,,
"texture_control_word",,25,"stride_select",,,
"tsp_instruction_word",,25,"stride_select",,,
,,,,,,
"texture_control_word",,"20-0","texture_address",,"0x1fffff",
"tsp_instruction_word",,"20-0","texture_address",,"0x1fffff",

1 register_name enum_name bits bit_name value mask description
106
107 texture_control_word 30 vq_compressed 1
108
109 texture_control_word tsp_instruction_word pixel_format 29-27 1555 0
110 texture_control_word tsp_instruction_word pixel_format 29-27 565 1
111 texture_control_word tsp_instruction_word pixel_format 29-27 4444 2
112 texture_control_word tsp_instruction_word pixel_format 29-27 yuv422 3
113 texture_control_word tsp_instruction_word pixel_format 29-27 bump_map 4
114 texture_control_word tsp_instruction_word pixel_format 29-27 4bpp_palette 5
115 texture_control_word tsp_instruction_word pixel_format 29-27 8bpp_palette 6
116
117 texture_control_word tsp_instruction_word scan_order 26 twiddled 0
118 texture_control_word tsp_instruction_word scan_order 26 non_twiddled 1
119
120 texture_control_word tsp_instruction_word 26-21 palette_selector4 0x3f
121
122 texture_control_word tsp_instruction_word 26-25 palette_selector8 0x3
123
124 texture_control_word tsp_instruction_word 25 stride_select
125
126 texture_control_word tsp_instruction_word 20-0 texture_address 0x1fffff

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regs/isp_tsp.ods
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70
regs/systembus.csv
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@ -1,49 +1,49 @@
"block","address","size","name","r/w","description"
"SYSTEMBUS","000","4","C2DSTAT","RW","CH2-DMA destination address"
"SYSTEMBUS","004","4","C2DLEN","RW","CH2-DMA length"
"SYSTEMBUS","008","4","C2DST","RW","CH2-DMA start"
"SYSTEM","000","4","C2DSTAT","RW","CH2-DMA destination address"
"SYSTEM","004","4","C2DLEN","RW","CH2-DMA length"
"SYSTEM","008","4","C2DST","RW","CH2-DMA start"
,,,,,
"SYSTEMBUS","010","4","SDSTAW","RW","Sort-DMA start link table address"
"SYSTEMBUS","014","4","SDBAAW","RW","Sort-DMA link base address"
"SYSTEMBUS","018","4","SDWLT","RW","Sort-DMA link address bit width"
"SYSTEMBUS","01c","4","SDLAS","RW","Sort-DMA link address shift control"
"SYSTEMBUS","020","4","SDST","RW","Sort-DMA start"
"SYSTEM","010","4","SDSTAW","RW","Sort-DMA start link table address"
"SYSTEM","014","4","SDBAAW","RW","Sort-DMA link base address"
"SYSTEM","018","4","SDWLT","RW","Sort-DMA link address bit width"
"SYSTEM","01c","4","SDLAS","RW","Sort-DMA link address shift control"
"SYSTEM","020","4","SDST","RW","Sort-DMA start"
,,,,,
"SYSTEMBUS","040","4","DBREQM","RW","DBREQ# signal mask control"
"SYSTEMBUS","044","4","BAVLWC","RW","BAVL# signal wait count"
"SYSTEMBUS","048","4","C2DPYRC","RW","DMA (TA/Root Bus) priority count"
"SYSTEMBUS","04c","4","DMAXL","RW","CH2-DMA maximum burst length"
"SYSTEM","040","4","DBREQM","RW","DBREQ# signal mask control"
"SYSTEM","044","4","BAVLWC","RW","BAVL# signal wait count"
"SYSTEM","048","4","C2DPYRC","RW","DMA (TA/Root Bus) priority count"
"SYSTEM","04c","4","DMAXL","RW","CH2-DMA maximum burst length"
,,,,,
"SYSTEMBUS","080","4","TFREM","R","TA FIFO remaining amount"
"SYSTEMBUS","084","4","LMMODE0","RW","Via TA texture memory bus select 0"
"SYSTEMBUS","088","4","LMMODE1","RW","Via TA texture memory bus select 1"
"SYSTEMBUS","08c","4","FFST","R","FIFO status"
"SYSTEMBUS","090","4","SFRES","W","System reset"
"SYSTEM","080","4","TFREM","R","TA FIFO remaining amount"
"SYSTEM","084","4","LMMODE0","RW","Via TA texture memory bus select 0"
"SYSTEM","088","4","LMMODE1","RW","Via TA texture memory bus select 1"
"SYSTEM","08c","4","FFST","R","FIFO status"
"SYSTEM","090","4","SFRES","W","System reset"
,,,,,
"SYSTEMBUS","09c","4","SBREV","R","System bus revision number"
"SYSTEMBUS","0a0","4","RBSPLT","RW","SH4 Root Bus split enable"
"SYSTEM","09c","4","SBREV","R","System bus revision number"
"SYSTEM","0a0","4","RBSPLT","RW","SH4 Root Bus split enable"
,,,,,
"SYSTEMBUS","100","4","ISTNRM","RW","Normal interrupt status"
"SYSTEMBUS","104","4","ISTEXT","R","External interrupt status"
"SYSTEMBUS","108","4","ISTERR","RW","Error interrupt status"
"SYSTEM","100","4","ISTNRM","RW","Normal interrupt status"
"SYSTEM","104","4","ISTEXT","R","External interrupt status"
"SYSTEM","108","4","ISTERR","RW","Error interrupt status"
,,,,,
"SYSTEMBUS","110","4","IML2NRM","RW","Level 2 normal interrupt mask"
"SYSTEMBUS","114","4","IML2EXT","RW","Level 2 external interrupt mask"
"SYSTEMBUS","118","4","IML2ERR","RW","Level 2 error interrupt mask"
"SYSTEM","110","4","IML2NRM","RW","Level 2 normal interrupt mask"
"SYSTEM","114","4","IML2EXT","RW","Level 2 external interrupt mask"
"SYSTEM","118","4","IML2ERR","RW","Level 2 error interrupt mask"
,,,,,
"SYSTEMBUS","120","4","IML4NRM","RW","Level 4 normal interrupt mask"
"SYSTEMBUS","124","4","IML4EXT","RW","Level 4 external interrupt mask"
"SYSTEMBUS","128","4","IML4ERR","RW","Level 4 error interrupt mask"
"SYSTEM","120","4","IML4NRM","RW","Level 4 normal interrupt mask"
"SYSTEM","124","4","IML4EXT","RW","Level 4 external interrupt mask"
"SYSTEM","128","4","IML4ERR","RW","Level 4 error interrupt mask"
,,,,,
"SYSTEMBUS","130","4","IML6NRM","RW","Level 6 normal interrupt mask"
"SYSTEMBUS","134","4","IML6EXT","RW","Level 6 external interrupt mask"
"SYSTEMBUS","138","4","IML6ERR","RW","Level 6 error interrupt mask"
"SYSTEM","130","4","IML6NRM","RW","Level 6 normal interrupt mask"
"SYSTEM","134","4","IML6EXT","RW","Level 6 external interrupt mask"
"SYSTEM","138","4","IML6ERR","RW","Level 6 error interrupt mask"
,,,,,
"SYSTEMBUS","140","4","PDTNRM","RW","Normal interrupt PVR-DMA startup mask"
"SYSTEMBUS","144","4","PDTEXT","RW","External interrupt PVR-DMA startup mask"
"SYSTEM","140","4","PDTNRM","RW","Normal interrupt PVR-DMA startup mask"
"SYSTEM","144","4","PDTEXT","RW","External interrupt PVR-DMA startup mask"
,,,,,
"SYSTEMBUS","150","4","G2DTNRM","RW","Normal interrupt G2-DMA startup mask"
"SYSTEMBUS","154","4","G2DTEXT","RW","External interrupt G2-DMA startup mask"
"SYSTEM","150","4","G2DTNRM","RW","Normal interrupt G2-DMA startup mask"
"SYSTEM","154","4","G2DTEXT","RW","External interrupt G2-DMA startup mask"
,,,,,
"MAPLE_IF","04","4","MDSTAR","RW","Maple-DMA command table address"
,,,,,

1 block address size name r/w description
2 SYSTEMBUS SYSTEM 000 4 C2DSTAT RW CH2-DMA destination address
3 SYSTEMBUS SYSTEM 004 4 C2DLEN RW CH2-DMA length
4 SYSTEMBUS SYSTEM 008 4 C2DST RW CH2-DMA start
5
6 SYSTEMBUS SYSTEM 010 4 SDSTAW RW Sort-DMA start link table address
7 SYSTEMBUS SYSTEM 014 4 SDBAAW RW Sort-DMA link base address
8 SYSTEMBUS SYSTEM 018 4 SDWLT RW Sort-DMA link address bit width
9 SYSTEMBUS SYSTEM 01c 4 SDLAS RW Sort-DMA link address shift control
10 SYSTEMBUS SYSTEM 020 4 SDST RW Sort-DMA start
11
12 SYSTEMBUS SYSTEM 040 4 DBREQM RW DBREQ# signal mask control
13 SYSTEMBUS SYSTEM 044 4 BAVLWC RW BAVL# signal wait count
14 SYSTEMBUS SYSTEM 048 4 C2DPYRC RW DMA (TA/Root Bus) priority count
15 SYSTEMBUS SYSTEM 04c 4 DMAXL RW CH2-DMA maximum burst length
16
17 SYSTEMBUS SYSTEM 080 4 TFREM R TA FIFO remaining amount
18 SYSTEMBUS SYSTEM 084 4 LMMODE0 RW Via TA texture memory bus select 0
19 SYSTEMBUS SYSTEM 088 4 LMMODE1 RW Via TA texture memory bus select 1
20 SYSTEMBUS SYSTEM 08c 4 FFST R FIFO status
21 SYSTEMBUS SYSTEM 090 4 SFRES W System reset
22
23 SYSTEMBUS SYSTEM 09c 4 SBREV R System bus revision number
24 SYSTEMBUS SYSTEM 0a0 4 RBSPLT RW SH4 Root Bus split enable
25
26 SYSTEMBUS SYSTEM 100 4 ISTNRM RW Normal interrupt status
27 SYSTEMBUS SYSTEM 104 4 ISTEXT R External interrupt status
28 SYSTEMBUS SYSTEM 108 4 ISTERR RW Error interrupt status
29
30 SYSTEMBUS SYSTEM 110 4 IML2NRM RW Level 2 normal interrupt mask
31 SYSTEMBUS SYSTEM 114 4 IML2EXT RW Level 2 external interrupt mask
32 SYSTEMBUS SYSTEM 118 4 IML2ERR RW Level 2 error interrupt mask
33
34 SYSTEMBUS SYSTEM 120 4 IML4NRM RW Level 4 normal interrupt mask
35 SYSTEMBUS SYSTEM 124 4 IML4EXT RW Level 4 external interrupt mask
36 SYSTEMBUS SYSTEM 128 4 IML4ERR RW Level 4 error interrupt mask
37
38 SYSTEMBUS SYSTEM 130 4 IML6NRM RW Level 6 normal interrupt mask
39 SYSTEMBUS SYSTEM 134 4 IML6EXT RW Level 6 external interrupt mask
40 SYSTEMBUS SYSTEM 138 4 IML6ERR RW Level 6 error interrupt mask
41
42 SYSTEMBUS SYSTEM 140 4 PDTNRM RW Normal interrupt PVR-DMA startup mask
43 SYSTEMBUS SYSTEM 144 4 PDTEXT RW External interrupt PVR-DMA startup mask
44
45 SYSTEMBUS SYSTEM 150 4 G2DTNRM RW Normal interrupt G2-DMA startup mask
46 SYSTEMBUS SYSTEM 154 4 G2DTEXT RW External interrupt G2-DMA startup mask
47
48 MAPLE_IF 04 4 MDSTAR RW Maple-DMA command table address
49

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regs/systembus.ods
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24
serial_protocol.hpp
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@ -41,7 +41,7 @@ static inline uint32_t le_bswap(const uint32_t n)
return __builtin_bswap32(n);
}
union command_reply command_reply(uint32_t cmd, uint32_t arg0, uint32_t arg1)
constexpr union command_reply command_reply(uint32_t cmd, uint32_t arg0, uint32_t arg1)
{
union command_reply command = {
.cmd = le_bswap(cmd),
@ -67,27 +67,27 @@ namespace command {
static_assert(_maple_raw == 0xb62422e0);
union command_reply write(uint32_t dest, uint32_t size)
constexpr union command_reply write(uint32_t dest, uint32_t size)
{
return command_reply(_write, dest, size);
}
union command_reply read(uint32_t dest, uint32_t size)
constexpr union command_reply read(uint32_t dest, uint32_t size)
{
return command_reply(_read, dest, size);
}
union command_reply jump(uint32_t dest)
constexpr union command_reply jump(uint32_t dest)
{
return command_reply(_jump, dest, 0);
}
union command_reply speed(uint32_t speed)
constexpr union command_reply speed(uint32_t speed)
{
return command_reply(_speed, speed, 0);
}
union command_reply maple_raw(uint32_t send_size, uint32_t recv_size)
constexpr union command_reply maple_raw(uint32_t send_size, uint32_t recv_size)
{
return command_reply(_maple_raw, send_size, recv_size);
}
@ -112,32 +112,32 @@ namespace reply {
static_assert(_crc == 0xcc9aab7c);
union command_reply write(uint32_t dest, uint32_t size)
constexpr union command_reply write(uint32_t dest, uint32_t size)
{
return command_reply(_write, dest, size);
}
union command_reply read(uint32_t dest, uint32_t size)
constexpr union command_reply read(uint32_t dest, uint32_t size)
{
return command_reply(_read, dest, size);
}
union command_reply jump(uint32_t dest)
constexpr union command_reply jump(uint32_t dest)
{
return command_reply(_jump, dest, 0);
}
union command_reply speed(uint32_t speed)
constexpr union command_reply speed(uint32_t speed)
{
return command_reply(_speed, speed, 0);
}
union command_reply crc(uint32_t crc)
constexpr union command_reply crc(uint32_t crc)
{
return command_reply(_crc, crc, 0);
}
union command_reply maple_raw(uint32_t send_size, uint32_t recv_size)
constexpr union command_reply maple_raw(uint32_t send_size, uint32_t recv_size)
{
return command_reply(_maple_raw, send_size, recv_size);
}

7
tools/Makefile
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@ -2,19 +2,18 @@ CFLAGS = -Og -g -gdwarf-4 -Wall -Wextra -Werror -Wfatal-errors -ggdb -fstack-pro
CFLAGS += -Wno-error=unused-parameter
CFLAGS += -Wno-error=unused-variable
CFLAGS += -Wno-error=unused-but-set-variable
CFLAGS += -Wno-vla-cxx-extension
CXXFLAGS = -std=c++23
FREETYPE_CFLAGS = $(shell pkg-config --cflags freetype2)
FREETYPE_LDFLAGS = $(shell pkg-config --libs freetype2)
FTDI_CFLAGS = $(shell pkg-config --cflags libftdi1) -I.
FTDI_CFLAGS = $(shell pkg-config --cflags libftdi1) -I..
FTDI_LDFLAGS = $(shell pkg-config --libs libftdi1)
all: ttf_outline
crc32.o: crc32.c
$(CC) -std=gnu2x $(CFLAGS) -I. -c $< -o $@
crc32.o: ../crc32.c
$(CC) -std=gnu2x $(CFLAGS) -I.. -c $< -o $@
ttf_%.o: ttf_%.cpp
$(CXX) $(CFLAGS) $(CXXFLAGS) $(FREETYPE_CFLAGS) -c $< -o $@

1
tools/align.hpp
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@ -1 +0,0 @@
../align.hpp

1
tools/crc32.c
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@ -1 +0,0 @@
../crc32.c

1
tools/crc32.h
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@ -1 +0,0 @@
../crc32.h

1
tools/maple
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@ -1 +0,0 @@
../maple

1
tools/serial_protocol.hpp
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@ -1 +0,0 @@
../serial_protocol.hpp

19
tools/source_dist.sh
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@ -1,19 +0,0 @@
rm -rf ftdi_transfer_source
mkdir -p ftdi_transfer_source
cp -rL \
align.hpp \
crc32.c \
crc32.h \
ftdi_maple.cpp \
ftdi_maple.hpp \
ftdi_transfer.1 \
ftdi_transfer.cpp \
ftdi_transfer.hpp \
ftdi_transfer.sh \
Makefile \
maple \
serial_protocol.hpp \
ftdi_transfer_source/
#tar cvzf ftdi_transfer_source.tar.gz ftdi_transfer_source