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regs: add systembus and memorymap

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This commit is contained in:
Zack Buhman 2023-10-11 15:33:53 -07:00
parent 327e57a520
commit ee9e44e4a6
3 changed files with 162 additions and 0 deletions
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regs/memorymap.ods Normal file
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regs/systembus.csv Normal file
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"block","address","size","name","r/w","description"
"SYSTEM","000","4","C2DSTAT","RW","CH2-DMA destination address"
"SYSTEM","004","4","C2DLEN","RW","CH2-DMA length"
"SYSTEM","008","4","C2DST","RW","CH2-DMA start"
,,,,,
"SYSTEM","010","4","SDSTAW","RW","Sort-DMA start link table address"
"SYSTEM","014","4","SDBAAW","RW","Sort-DMA link base address"
"SYSTEM","018","4","SDWLT","RW","Sort-DMA link address bit width"
"SYSTEM","01c","4","SDLAS","RW","Sort-DMA link address shift control"
"SYSTEM","020","4","SDST","RW","Sort-DMA start"
,,,,,
"SYSTEM","040","4","DBREQM","RW","DBREQ# signal mask control"
"SYSTEM","044","4","BAVLWC","RW","BAVL# signal wait count"
"SYSTEM","048","4","C2DPYRC","RW","DMA (TA/Root Bus) priority count"
"SYSTEM","04c","4","DMAXL","RW","CH2-DMA maximum burst length"
,,,,,
"SYSTEM","080","4","TFREM","R","TA FIFO remaining amount"
"SYSTEM","084","4","LMMODE0","RW","Via TA texture memory bus select 0"
"SYSTEM","088","4","LMMODE1","RW","Via TA texture memory bus select 1"
"SYSTEM","08c","4","FFST","R","FIFO status"
"SYSTEM","090","4","SFRES","W","System reset"
,,,,,
"SYSTEM","09c","4","SBREV","R","System bus revision number"
"SYSTEM","0a0","4","RBSPLT","RW","SH4 Root Bus split enable"
,,,,,
"SYSTEM","100","4","ISTNRM","RW","Normal interrupt status"
"SYSTEM","104","4","ISTEXT","R","External interrupt status"
"SYSTEM","108","4","ISTERR","RW","Error interrupt status"
,,,,,
"SYSTEM","110","4","IML2NRM","RW","Level 2 normal interrupt mask"
"SYSTEM","114","4","IML2EXT","RW","Level 2 external interrupt mask"
"SYSTEM","118","4","IML2ERR","RW","Level 2 error interrupt mask"
,,,,,
"SYSTEM","120","4","IML4NRM","RW","Level 4 normal interrupt mask"
"SYSTEM","124","4","IML4EXT","RW","Level 4 external interrupt mask"
"SYSTEM","128","4","IML4ERR","RW","Level 4 error interrupt mask"
,,,,,
"SYSTEM","130","4","IML6NRM","RW","Level 6 normal interrupt mask"
"SYSTEM","134","4","IML6EXT","RW","Level 6 external interrupt mask"
"SYSTEM","138","4","IML6ERR","RW","Level 6 error interrupt mask"
,,,,,
"SYSTEM","140","4","PDTNRM","RW","Normal interrupt PVR-DMA startup mask"
"SYSTEM","144","4","PDTEXT","RW","External interrupt PVR-DMA startup mask"
,,,,,
"SYSTEM","150","4","G2DTNRM","RW","Normal interrupt G2-DMA startup mask"
"SYSTEM","154","4","G2DTEXT","RW","External interrupt G2-DMA startup mask"
,,,,,
"MAPLE","04","4","MDSTAR","RW","Maple-DMA command table address"
,,,,,
"MAPLE","10","4","MDTSEL","RW","Maple-DMA trigger select"
"MAPLE","14","4","MDEN","RW","Maple-DMA enable"
"MAPLE","18","4","MDST","RW","Maple-DMA start"
,,,,,
"MAPLE","80","4","MSYS","RW","Maple system control"
"MAPLE","84","4","MST","R","Maple status"
"MAPLE","88","4","MSHTCL","W","Maple-DMA hard trigger clear"
"MAPLE","8c","4","MDAPRO","W","Maple-DMA address range"
,,,,,
"MAPLE","e8","4","MMSEL","RW","Maple MSP selection"
,,,,,
"MAPLE","f4","4","MTXDAD","R","Maple TXD address counter"
"MAPLE","f8","4","MRXDAD","R","Maple RXD address counter"
"MAPLE","fc","4","MRXDBD","R","Maple RXD address base"
,,,,,
"G1","04","4","GDSTAR","RW","GD-DMA start address"
"G1","08","4","GDLEN","RW","GD-DMA length"
"G1","0c","4","GDDIR","RW","GD-DMA direction"
,,,,,
"G1","14","4","GDEN","RW","GD-DMA enable"
"G1","18","4","GDST","RW","GD-DMA start"
,,,,,
"G1","80","4","G1RRC","W","System ROM read access timing"
"G1","84","4","G1RWC","W","System ROM write access timing"
"G1","88","4","G1FRC","W","Flash ROM read access timing"
"G1","8c","4","G1FWC","W","Flash ROM write access timing"
"G1","90","4","G1CRC","W","GD PIO read access timing"
"G1","94","4","G1CWC","W","GD PIO write access timing"
,,,,,
"G1","a0","4","G1GDRC","W","GD-DMA read access timing"
"G1","a4","4","G1GDWC","W","GD-DMA write access timing"
,,,,,
"G1","b0","4","G1SYSM","R","System mode"
"G1","b4","4","G1CRDYC","W","G1IORDY signal control"
"G1","b8","4","GDAPRO","W","GD-DMA address range"
,,,,,
"G1","f4","4","GDSTARD","R","GD-DMA address count (on Root Bus)"
"G1","f8","4","GDLEND","R","GD-DMA transfer counter"
,,,,,
"G2","00","4","ADSTAG","RW","ACIA:G2-DMA G2 start address"
"G2","04","4","ADSTAR","RW","ACIA:G2-DMA system memory start address"
"G2","08","4","ADLEN","RW","ACIA:G2-DMA length"
"G2","0c","4","ADDIR","RW","ACIA:G2-DMA direction"
"G2","10","4","ADTSEL","RW","ACIA:G2-DMA trigger select"
"G2","14","4","ADEN","RW","ACIA:G2-DMA enable"
"G2","18","4","ADST","RW","ACIA:G2-DMA start"
"G2","1c","4","ADSUSP","RW","ACIA:G2-DMA suspend"
,,,,,
"G2","20","4","E1STAG","RW","Ext1:G2-DMA start address"
"G2","24","4","E1STAR","RW","Ext1:G2-DMA system memory start address"
"G2","28","4","E1LEN","RW","Ext1:G2-DMA length"
"G2","2c","4","E1DIR","RW","Ext1:G2-DMA direction"
"G2","30","4","E1TSEL","RW","Ext1:G2-DMA trigger select"
"G2","34","4","E1EN","RW","Ext1:G2-DMA enable"
"G2","38","4","E1ST","RW","Ext1:G2-DMA start"
"G2","3c","4","E1SUSP","RW","Ext1:G2-DMA suspend"
,,,,,
"G2","40","4","E2STAG","RW","Ext2:G2-DMA start address"
"G2","44","4","E2STAR","RW","Ext2:G2-DMA system memory start address"
"G2","48","4","E2LEN","RW","Ext2:G2-DMA length"
"G2","4c","4","E2DIR","RW","Ext2:G2-DMA direction"
"G2","50","4","E2TSEL","RW","Ext2:G2-DMA trigger select"
"G2","54","4","E2EN","RW","Ext2:G2-DMA enable"
"G2","58","4","E2ST","RW","Ext2:G2-DMA start"
"G2","5c","4","E2SUSP","RW","Ext2:G2-DMA suspend"
,,,,,
"G2","60","4","DDSTAG","RW","Dev:G2-DMA start address"
"G2","64","4","DDSTAR","RW","Dev:G2-DMA system memory start address"
"G2","68","4","DDLEN","RW","Dev:G2-DMA length"
"G2","6c","4","DDDIR","RW","Dev:G2-DMA direction"
"G2","70","4","DDTSEL","RW","Dev:G2-DMA trigger select"
"G2","74","4","DDEN","RW","Dev:G2-DMA enable"
"G2","78","4","DDST","RW","Dev:G2-DMA start"
"G2","7c","4","DDSUSP","RW","Dev:G2-DMA suspend"
,,,,,
"G2","80","4","G2ID","R","G2 bus version"
,,,,,
"G2","90","4","G2DSTO","RW","G2/DS timeout"
"G2","94","4","G2TRTO","RW","G2/TR timeout"
"G2","98","4","G2MDMTO","RW","Modem unit wait timeout"
"G2","9c","4","G2MDMW","RW","Modem unit wait time"
,,,,,
"G2","bc","4","G2APRO","W","G2-DMA address range"
,,,,,
"G2","c0","4","ADSTAGD","R","AICA-DMA address counter (on AICA)"
"G2","c4","4","ADSTARD","R","AICA-DMA address counter (on root bus)"
"G2","c8","4","ADLEND","R","AICA-DMA transfer counter"
,,,,,
"G2","d0","4","E1STAGD","R","Ext-DMA1 address counter (on Ext)"
"G2","d4","4","E1STARD","R","Ext-DMA1 address counter (on root bus)"
"G2","d8","4","E1LEND","R","Ext-DMA1 transfer counter"
,,,,,
"G2","e0","4","E2STAGD","R","Ext-DMA2 address counter (on Ext)"
"G2","e4","4","E2STARD","R","Ext-DMA2 address counter (on root bus)"
"G2","e8","4","E2LEND","R","Ext-DMA2 transfer counter"
,,,,,
"G2","f0","4","DDSTAGD","R","Dev-DMA address counter (on Dev)"
"G2","f4","4","DDSTARD","R","Dev-DMA address counter (on root bus)"
"G2","f8","4","DDLEND","R","Dev-DMA transfer counter"
,,,,,
"PVR","00","4","PDSTAP","RW","PVR-DMA start address"
"PVR","04","4","PDSTAR","RW","PVR-DMA system memory start address"
"PVR","08","4","PDLEN","RW","PVR-DMA length"
"PVR","0c","4","PDDIR","RW","PVR-DMA direction"
"PVR","10","4","PDTSEL","RW","PVR-DMA trigger select"
"PVR","14","4","PDEN","RW","PVR-DMA enable"
"PVR","18","4","PDST","RW","PVR-DMA start"
,,,,,
"PVR","80","4","PDAPRO","W","PVR-DMA address range"
,,,,,
"PVR","f0","4","PDSTAPD","R","PVR-DMA address counter (on Ext)"
"PVR","f4","4","PDSTARD","R","PVR-DMA address counter (on root bus)"
"PVR","f8","4","PDLEND","R","PVR-DMA transfer counter"
1 block address size name r/w description
2 SYSTEM 000 4 C2DSTAT RW CH2-DMA destination address
3 SYSTEM 004 4 C2DLEN RW CH2-DMA length
4 SYSTEM 008 4 C2DST RW CH2-DMA start
5
6 SYSTEM 010 4 SDSTAW RW Sort-DMA start link table address
7 SYSTEM 014 4 SDBAAW RW Sort-DMA link base address
8 SYSTEM 018 4 SDWLT RW Sort-DMA link address bit width
9 SYSTEM 01c 4 SDLAS RW Sort-DMA link address shift control
10 SYSTEM 020 4 SDST RW Sort-DMA start
11
12 SYSTEM 040 4 DBREQM RW DBREQ# signal mask control
13 SYSTEM 044 4 BAVLWC RW BAVL# signal wait count
14 SYSTEM 048 4 C2DPYRC RW DMA (TA/Root Bus) priority count
15 SYSTEM 04c 4 DMAXL RW CH2-DMA maximum burst length
16
17 SYSTEM 080 4 TFREM R TA FIFO remaining amount
18 SYSTEM 084 4 LMMODE0 RW Via TA texture memory bus select 0
19 SYSTEM 088 4 LMMODE1 RW Via TA texture memory bus select 1
20 SYSTEM 08c 4 FFST R FIFO status
21 SYSTEM 090 4 SFRES W System reset
22
23 SYSTEM 09c 4 SBREV R System bus revision number
24 SYSTEM 0a0 4 RBSPLT RW SH4 Root Bus split enable
25
26 SYSTEM 100 4 ISTNRM RW Normal interrupt status
27 SYSTEM 104 4 ISTEXT R External interrupt status
28 SYSTEM 108 4 ISTERR RW Error interrupt status
29
30 SYSTEM 110 4 IML2NRM RW Level 2 normal interrupt mask
31 SYSTEM 114 4 IML2EXT RW Level 2 external interrupt mask
32 SYSTEM 118 4 IML2ERR RW Level 2 error interrupt mask
33
34 SYSTEM 120 4 IML4NRM RW Level 4 normal interrupt mask
35 SYSTEM 124 4 IML4EXT RW Level 4 external interrupt mask
36 SYSTEM 128 4 IML4ERR RW Level 4 error interrupt mask
37
38 SYSTEM 130 4 IML6NRM RW Level 6 normal interrupt mask
39 SYSTEM 134 4 IML6EXT RW Level 6 external interrupt mask
40 SYSTEM 138 4 IML6ERR RW Level 6 error interrupt mask
41
42 SYSTEM 140 4 PDTNRM RW Normal interrupt PVR-DMA startup mask
43 SYSTEM 144 4 PDTEXT RW External interrupt PVR-DMA startup mask
44
45 SYSTEM 150 4 G2DTNRM RW Normal interrupt G2-DMA startup mask
46 SYSTEM 154 4 G2DTEXT RW External interrupt G2-DMA startup mask
47
48 MAPLE 04 4 MDSTAR RW Maple-DMA command table address
49
50 MAPLE 10 4 MDTSEL RW Maple-DMA trigger select
51 MAPLE 14 4 MDEN RW Maple-DMA enable
52 MAPLE 18 4 MDST RW Maple-DMA start
53
54 MAPLE 80 4 MSYS RW Maple system control
55 MAPLE 84 4 MST R Maple status
56 MAPLE 88 4 MSHTCL W Maple-DMA hard trigger clear
57 MAPLE 8c 4 MDAPRO W Maple-DMA address range
58
59 MAPLE e8 4 MMSEL RW Maple MSP selection
60
61 MAPLE f4 4 MTXDAD R Maple TXD address counter
62 MAPLE f8 4 MRXDAD R Maple RXD address counter
63 MAPLE fc 4 MRXDBD R Maple RXD address base
64
65 G1 04 4 GDSTAR RW GD-DMA start address
66 G1 08 4 GDLEN RW GD-DMA length
67 G1 0c 4 GDDIR RW GD-DMA direction
68
69 G1 14 4 GDEN RW GD-DMA enable
70 G1 18 4 GDST RW GD-DMA start
71
72 G1 80 4 G1RRC W System ROM read access timing
73 G1 84 4 G1RWC W System ROM write access timing
74 G1 88 4 G1FRC W Flash ROM read access timing
75 G1 8c 4 G1FWC W Flash ROM write access timing
76 G1 90 4 G1CRC W GD PIO read access timing
77 G1 94 4 G1CWC W GD PIO write access timing
78
79 G1 a0 4 G1GDRC W GD-DMA read access timing
80 G1 a4 4 G1GDWC W GD-DMA write access timing
81
82 G1 b0 4 G1SYSM R System mode
83 G1 b4 4 G1CRDYC W G1IORDY signal control
84 G1 b8 4 GDAPRO W GD-DMA address range
85
86 G1 f4 4 GDSTARD R GD-DMA address count (on Root Bus)
87 G1 f8 4 GDLEND R GD-DMA transfer counter
88
89 G2 00 4 ADSTAG RW ACIA:G2-DMA G2 start address
90 G2 04 4 ADSTAR RW ACIA:G2-DMA system memory start address
91 G2 08 4 ADLEN RW ACIA:G2-DMA length
92 G2 0c 4 ADDIR RW ACIA:G2-DMA direction
93 G2 10 4 ADTSEL RW ACIA:G2-DMA trigger select
94 G2 14 4 ADEN RW ACIA:G2-DMA enable
95 G2 18 4 ADST RW ACIA:G2-DMA start
96 G2 1c 4 ADSUSP RW ACIA:G2-DMA suspend
97
98 G2 20 4 E1STAG RW Ext1:G2-DMA start address
99 G2 24 4 E1STAR RW Ext1:G2-DMA system memory start address
100 G2 28 4 E1LEN RW Ext1:G2-DMA length
101 G2 2c 4 E1DIR RW Ext1:G2-DMA direction
102 G2 30 4 E1TSEL RW Ext1:G2-DMA trigger select
103 G2 34 4 E1EN RW Ext1:G2-DMA enable
104 G2 38 4 E1ST RW Ext1:G2-DMA start
105 G2 3c 4 E1SUSP RW Ext1:G2-DMA suspend
106
107 G2 40 4 E2STAG RW Ext2:G2-DMA start address
108 G2 44 4 E2STAR RW Ext2:G2-DMA system memory start address
109 G2 48 4 E2LEN RW Ext2:G2-DMA length
110 G2 4c 4 E2DIR RW Ext2:G2-DMA direction
111 G2 50 4 E2TSEL RW Ext2:G2-DMA trigger select
112 G2 54 4 E2EN RW Ext2:G2-DMA enable
113 G2 58 4 E2ST RW Ext2:G2-DMA start
114 G2 5c 4 E2SUSP RW Ext2:G2-DMA suspend
115
116 G2 60 4 DDSTAG RW Dev:G2-DMA start address
117 G2 64 4 DDSTAR RW Dev:G2-DMA system memory start address
118 G2 68 4 DDLEN RW Dev:G2-DMA length
119 G2 6c 4 DDDIR RW Dev:G2-DMA direction
120 G2 70 4 DDTSEL RW Dev:G2-DMA trigger select
121 G2 74 4 DDEN RW Dev:G2-DMA enable
122 G2 78 4 DDST RW Dev:G2-DMA start
123 G2 7c 4 DDSUSP RW Dev:G2-DMA suspend
124
125 G2 80 4 G2ID R G2 bus version
126
127 G2 90 4 G2DSTO RW G2/DS timeout
128 G2 94 4 G2TRTO RW G2/TR timeout
129 G2 98 4 G2MDMTO RW Modem unit wait timeout
130 G2 9c 4 G2MDMW RW Modem unit wait time
131
132 G2 bc 4 G2APRO W G2-DMA address range
133
134 G2 c0 4 ADSTAGD R AICA-DMA address counter (on AICA)
135 G2 c4 4 ADSTARD R AICA-DMA address counter (on root bus)
136 G2 c8 4 ADLEND R AICA-DMA transfer counter
137
138 G2 d0 4 E1STAGD R Ext-DMA1 address counter (on Ext)
139 G2 d4 4 E1STARD R Ext-DMA1 address counter (on root bus)
140 G2 d8 4 E1LEND R Ext-DMA1 transfer counter
141
142 G2 e0 4 E2STAGD R Ext-DMA2 address counter (on Ext)
143 G2 e4 4 E2STARD R Ext-DMA2 address counter (on root bus)
144 G2 e8 4 E2LEND R Ext-DMA2 transfer counter
145
146 G2 f0 4 DDSTAGD R Dev-DMA address counter (on Dev)
147 G2 f4 4 DDSTARD R Dev-DMA address counter (on root bus)
148 G2 f8 4 DDLEND R Dev-DMA transfer counter
149
150 PVR 00 4 PDSTAP RW PVR-DMA start address
151 PVR 04 4 PDSTAR RW PVR-DMA system memory start address
152 PVR 08 4 PDLEN RW PVR-DMA length
153 PVR 0c 4 PDDIR RW PVR-DMA direction
154 PVR 10 4 PDTSEL RW PVR-DMA trigger select
155 PVR 14 4 PDEN RW PVR-DMA enable
156 PVR 18 4 PDST RW PVR-DMA start
157
158 PVR 80 4 PDAPRO W PVR-DMA address range
159
160 PVR f0 4 PDSTAPD R PVR-DMA address counter (on Ext)
161 PVR f4 4 PDSTARD R PVR-DMA address counter (on root bus)
162 PVR f8 4 PDLEND R PVR-DMA transfer counter

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regs/systembus.ods Normal file
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