From b99d646365731d89a440f7df05f6fa8a21016e34 Mon Sep 17 00:00:00 2001 From: Zack Buhman Date: Sun, 24 Aug 2025 23:03:28 -0500 Subject: [PATCH] holly: add object_list_bits --- .gitignore | 2 +- dreamcast2/.gitignore | 1 + dreamcast2/holly/object_list_bits.hpp | 53 +++ dreamcast2/regs.mk | 3 + dreamcast2/regs/holly/holly.csv | 87 ----- dreamcast2/regs/holly/holly_bits.csv | 327 ----------------- dreamcast2/regs/holly/object_list_bits.ods | Bin 0 -> 15687 bytes dreamcast2/regs/holly/region_array_bits.csv | 10 - dreamcast2/regs/sh7091/sh7091.csv | 126 ------- dreamcast2/regs/sh7091/sh7091_bits.csv | 366 ------------------- dreamcast2/regs/systembus/systembus.csv | 163 --------- dreamcast2/regs/systembus/systembus_bits.csv | 67 ---- 12 files changed, 58 insertions(+), 1147 deletions(-) create mode 100644 dreamcast2/.gitignore create mode 100644 dreamcast2/holly/object_list_bits.hpp delete mode 100644 dreamcast2/regs/holly/holly.csv delete mode 100644 dreamcast2/regs/holly/holly_bits.csv create mode 100644 dreamcast2/regs/holly/object_list_bits.ods delete mode 100644 dreamcast2/regs/holly/region_array_bits.csv delete mode 100644 dreamcast2/regs/sh7091/sh7091.csv delete mode 100644 dreamcast2/regs/sh7091/sh7091_bits.csv delete mode 100644 dreamcast2/regs/systembus/systembus.csv delete mode 100644 dreamcast2/regs/systembus/systembus_bits.csv diff --git a/.gitignore b/.gitignore index 1b5aeb2..0fe8956 100644 --- a/.gitignore +++ b/.gitignore @@ -19,4 +19,4 @@ tools/ftdi_transfer k_means_vq *.blend1 *.scramble -*.FCStd1 \ No newline at end of file +*.FCStd1 diff --git a/dreamcast2/.gitignore b/dreamcast2/.gitignore new file mode 100644 index 0000000..16f2dc5 --- /dev/null +++ b/dreamcast2/.gitignore @@ -0,0 +1 @@ +*.csv \ No newline at end of file diff --git a/dreamcast2/holly/object_list_bits.hpp b/dreamcast2/holly/object_list_bits.hpp new file mode 100644 index 0000000..43d6474 --- /dev/null +++ b/dreamcast2/holly/object_list_bits.hpp @@ -0,0 +1,53 @@ +#pragma once + +#include + +namespace holly { + namespace object_list { + namespace pointer_type { + constexpr uint32_t triangle_strip = 0b000 << 29; + constexpr uint32_t triangle_array = 0b100 << 29; + constexpr uint32_t quad_array = 0b101 << 29; + constexpr uint32_t object_pointer_block_link = 0b111 << 29; + + constexpr uint32_t bit_mask = 0x7 << 29; + } + + namespace triangle_strip { + namespace mask { + constexpr uint32_t t0 = 0b100000 << 25; + constexpr uint32_t t1 = 0b010000 << 25; + constexpr uint32_t t2 = 0b001000 << 25; + constexpr uint32_t t3 = 0b000100 << 25; + constexpr uint32_t t4 = 0b000010 << 25; + constexpr uint32_t t5 = 0b000001 << 25; + + constexpr uint32_t bit_mask = 0x3f << 25; + } + + constexpr uint32_t shadow = 1 << 24; + constexpr uint32_t skip(uint32_t num) { return (num & 0x7) << 21; } + constexpr uint32_t start(uint32_t num) { return (num & 0x1fffff) << 0; } + } + + namespace triangle_array { + constexpr uint32_t number_of_triangles(uint32_t num) { return (num & 0xf) << 25; } + constexpr uint32_t shadow = 1 << 24; + constexpr uint32_t skip(uint32_t num) { return (num & 0x7) << 21; } + constexpr uint32_t start(uint32_t num) { return (num & 0x1fffff) << 0; } + } + + namespace quad_array { + constexpr uint32_t number_of_quads(uint32_t num) { return (num & 0xf) << 25; } + constexpr uint32_t shadow = 1 << 24; + constexpr uint32_t skip(uint32_t num) { return (num & 0x7) << 21; } + constexpr uint32_t start(uint32_t num) { return (num & 0x1fffff) << 0; } + } + + namespace object_pointer_block_link { + constexpr uint32_t end_of_list = 1 << 28; + constexpr uint32_t next_pointer_block(uint32_t num) { return (num & 0xfffffc) << 0; } + } + + } +} diff --git a/dreamcast2/regs.mk b/dreamcast2/regs.mk index 3d20b89..ffa2a84 100644 --- a/dreamcast2/regs.mk +++ b/dreamcast2/regs.mk @@ -13,6 +13,9 @@ holly/holly_bits.hpp: regs/holly/holly_bits.csv regs/render_bits.py holly/region_array_bits.hpp: regs/holly/region_array_bits.csv regs/render_bits.py python regs/render_bits.py $< holly region_array > $@ +holly/object_list_bits.hpp:regs/holly/object_list_bits.csv regs/render_bits.py + python regs/render_bits.py $< holly object_list > $@ + # SH7091 sh7091/sh7091.hpp: regs/sh7091/sh7091.csv regs/sh7091.py diff --git a/dreamcast2/regs/holly/holly.csv b/dreamcast2/regs/holly/holly.csv deleted file mode 100644 index 2e0a20e..0000000 --- a/dreamcast2/regs/holly/holly.csv +++ /dev/null @@ -1,87 +0,0 @@ -"block","address","size","name","r/w","description" -"holly","0000","4","ID","R","Device ID" -"holly","0004","4","REVISION","R","Revision Number" -"holly","0008","4","SOFTRESET","RW","CORE & TA software reset" -,,,,, -"holly","0014","4","STARTRENDER","RW","Drawing start" -"holly","0018","4","TEST_SELECT","RW","Test (writing this register is prohibited)" -,,,,, -"holly","0020","4","PARAM_BASE","RW","Base address for ISP parameters" -,,,,, -"holly","002c","4","REGION_BASE","RW","Base address for Region Array" -"holly","0030","4","SPAN_SORT_CFG","RW","Span Sorter control" -,,,,, -"holly","0040","4","VO_BORDER_COL","RW","Border area color" -"holly","0044","4","FB_R_CTRL","RW","Frame buffer read control" -"holly","0048","4","FB_W_CTRL","RW","Frame buffer write control" -"holly","004c","4","FB_W_LINESTRIDE","RW","Frame buffer line stride" -"holly","0050","4","FB_R_SOF1","RW","Read start address for field - 1/strip - 1" -"holly","0054","4","FB_R_SOF2","RW","Read start address for field - 2/strip - 2" -,,,,, -"holly","005c","4","FB_R_SIZE","RW","Frame buffer XY size" -"holly","0060","4","FB_W_SOF1","RW","Write start address for field - 1/strip - 1" -"holly","0064","4","FB_W_SOF2","RW","Write start address for field - 2/strip - 2" -"holly","0068","4","FB_X_CLIP","RW","Pixel clip X coordinate" -"holly","006c","4","FB_Y_CLIP","RW","Pixel clip Y coordinate" -,,,,, -"holly","0074","4","FPU_SHAD_SCALE","RW","Intensity Volume mode" -"holly","0078","4f","FPU_CULL_VAL","RW","Comparison value for culling" -"holly","007c","4","FPU_PARAM_CFG","RW","Parameter read control" -"holly","0080","4","HALF_OFFSET","RW","Pixel sampling control" -"holly","0084","4f","FPU_PERP_VAL","RW","Comparison value for perpendicular polygons" -"holly","0088","4f","ISP_BACKGND_D","RW","Background surface depth" -"holly","008c","4","ISP_BACKGND_T","RW","Background surface tag" -,,,,, -"holly","0098","4","ISP_FEED_CFG","RW","Translucent polygon sort mode" -,,,,, -"holly","00a0","4","SDRAM_REFRESH","RW","Texture memory refresh counter" -"holly","00a4","4","SDRAM_ARB_CFG","RW","Texture memory arbiter control" -"holly","00a8","4","SDRAM_CFG","RW","Texture memory control" -,,,,, -"holly","00b0","4","FOG_COL_RAM","RW","Color for Look Up table Fog" -"holly","00b4","4","FOG_COL_VERT","RW","Color for vertex Fog" -"holly","00b8","4","FOG_DENSITY","RW","Fog scale value" -"holly","00bc","4","FOG_CLAMP_MAX","RW","Color clamping maximum value" -"holly","00c0","4","FOG_CLAMP_MIN","RW","Color clamping minimum value" -"holly","00c4","4","SPG_TRIGGER_POS","RW","External trigger signal HV counter value" -"holly","00c8","4","SPG_HBLANK_INT","RW","H-blank interrupt control" -"holly","00cc","4","SPG_VBLANK_INT","RW","V-blank interrupt control" -"holly","00d0","4","SPG_CONTROL","RW","Sync pulse generator control" -"holly","00d4","4","SPG_HBLANK","RW","H-blank control" -"holly","00d8","4","SPG_LOAD","RW","HV counter load value" -"holly","00dc","4","SPG_VBLANK","RW","V-blank control" -"holly","00e0","4","SPG_WIDTH","RW","Sync width control" -"holly","00e4","4","TEXT_CONTROL","RW","Texturing control" -"holly","00e8","4","VO_CONTROL","RW","Video output control" -"holly","00ec","4","VO_STARTX","RW","Video output start X position" -"holly","00f0","4","VO_STARTY","RW","Video output start Y position" -"holly","00f4","4","SCALER_CTL","RW","X & Y scaler control" -,,,,, -"holly","0108","4","PAL_RAM_CTRL","RW","Palette RAM control" -"holly","010c","4","SPG_STATUS","R","Sync pulse generator status" -"holly","0110","4","FB_BURSTCTRL","RW","Frame buffer burst control" -"holly","0114","4","FB_C_SOF","R","Current frame buffer start address" -"holly","0118","4","Y_COEFF","RW","Y scaling coefficent" -"holly","011c","4","PT_ALPHA_REF","RW","Alpha value for Punch Through polygon comparison" -,,,,, -"holly","0124","4","TA_OL_BASE","RW","Object List write start address" -"holly","0128","4","TA_ISP_BASE","RW","ISP/TSP Parameter write start address" -"holly","012c","4","TA_OL_LIMIT","RW","Object List write limit address" -"holly","0130","4","TA_ISP_LIMIT","RW","ISP/TSP Parameter limit address" -"holly","0134","4","TA_NEXT_OPB","R","Start address for the Object Pointer Block" -"holly","0138","4","TA_ITP_CURRENT","R","Starting address where the next ISP/TSP Parameters are stored" -"holly","013c","4","TA_GLOB_TILE_CLIP","RW","Global Tile Clip control" -"holly","0140","4","TA_ALLOC_CTRL","RW","Object list control" -"holly","0144","4","TA_LIST_INIT","RW","TA initialization" -"holly","0148","4","TA_YUV_TEX_BASE","RW","YUV422 texture write start address" -"holly","014c","4","TA_YUV_TEX_CTRL","RW","YUV converter control" -"holly","0150","4","TA_YUV_TEX_CNT","R","YUV converter macro block counter value" -,,,,, -"holly","0160","4","TA_LIST_CONT","RW","TA continuation processing" -"holly","0164","4","TA_NEXT_OPB_INIT","RW","Additional OPB starting address" -,,,,, -"holly","0200","512","FOG_TABLE","RW","Look-up table fog data" -,,,,, -"holly","0600","2400","TA_OL_POINTERS","R","TA Object List Pointer data" -,,,,, -"holly","1000","4096","PALETTE_RAM","RW","Palette RAM" diff --git a/dreamcast2/regs/holly/holly_bits.csv b/dreamcast2/regs/holly/holly_bits.csv deleted file mode 100644 index e9ad7ce..0000000 --- a/dreamcast2/regs/holly/holly_bits.csv +++ /dev/null @@ -1,327 +0,0 @@ -"register_name","enum_name","bits","bit_name","value","mask","description",,,,, -"ID",,"31-16","device_id",,,,,,,, -"ID",,"15-0","vendor_id",,,,,,,, -,,,,,,,,,,, -"REVISION",,"15-0","chip_revision",,,,,,,, -,,,,,,,,,,, -"SOFTRESET",,2,"sdram_if_soft_reset",1,,,,,,, -"SOFTRESET",,1,"pipeline_soft_reset",1,,,,,,, -"SOFTRESET",,0,"ta_soft_reset",1,,,,,,, -,,,,,,,,,,, -"STARTRENDER",,0,"start_render",1,,,,,,, -,,,,,,,,,,, -"TEST_SELECT",,"9-5","diagdb_data",,,,,,,, -"TEST_SELECT",,"4-0","diagda_data",,,,,,,, -,,,,,,,,,,, -"PARAM_BASE",,"23-0","base_address",,"0xf00000",,,,,, -,,,,,,,,,,, -"REGION_BASE",,"23-0","base_address",,"0xfffffc",,,,,, -,,,,,,,,,,, -"SPAN_SORT_CFG",,16,"cache_bypass",1,,,,,,, -"SPAN_SORT_CFG",,8,"offset_sort_enable",1,,,,,,, -"SPAN_SORT_CFG",,0,"span_sort_enable",1,,,,,,, -,,,,,,,,,,, -"VO_BORDER_COL",,24,"chroma",,"0b1",,,,,, -"VO_BORDER_COL",,"23-16","red",,"0xff",,,,,, -"VO_BORDER_COL",,"15-8","green",,"0xff",,,,,, -"VO_BORDER_COL",,"7-0","blue",,"0xff",,,,,, -,,,,,,,,,,, -"FB_R_CTRL","vclk_div",23,"pclk_vclk_2",0,,,,,,, -"FB_R_CTRL","vclk_div",23,"pclk_vclk_1",1,,,,,,, -"FB_R_CTRL",,22,"fb_strip_buf_en",1,,,,,,, -"FB_R_CTRL",,"21-16","fb_stripsize",,"0b111_110","In units of 16 lines, in multiples of 32 lines. 0x02 is 32 lines, 0x04 is 64 lines, 0x03 is an illegal value",,,,, -"FB_R_CTRL",,"15-8","fb_chroma_threshold",,"0xff",,,,,, -"FB_R_CTRL",,"6-4","fb_concat",,"0b11",,,,,, -"FB_R_CTRL","fb_depth","3-2","xrgb0555",0,,,,,,, -"FB_R_CTRL","fb_depth","3-2","rgb565",1,,,,,,, -"FB_R_CTRL","fb_depth","3-2","rgb888",2,,,,,,, -"FB_R_CTRL","fb_depth","3-2","xrgb0888",3,,,,,,, -"FB_R_CTRL",,1,"fb_line_double",1,,,,,,, -"FB_R_CTRL",,0,"fb_enable",1,,,,,,, -,,,,,,,,,,, -"FB_W_CTRL",,"23-16","fb_alpha_threshold",,"0xff",,,,,, -"FB_W_CTRL",,"15-8","fb_kval",,"0xff",,,,,, -"FB_W_CTRL",,3,"fb_dither",1,,,,,,, -"FB_W_CTRL","fb_packmode","2-0","krgb0555",0,,,,,,, -"FB_W_CTRL","fb_packmode","2-0","rgb565",1,,,,,,, -"FB_W_CTRL","fb_packmode","2-0","argb4444",2,,,,,,, -"FB_W_CTRL","fb_packmode","2-0","argb1555",3,,,,,,, -"FB_W_CTRL","fb_packmode","2-0","rgb888",4,,,,,,, -"FB_W_CTRL","fb_packmode","2-0","krgb0888",5,,,,,,, -"FB_W_CTRL","fb_packmode","2-0","argb8888",6,,,,,,, -,,,,,,,,,,, -"FB_W_LINESTRIDE",,"8-0","fb_line_stride",,"0xff","In 8-byte units",,,,, -,,,,,,,,,,, -"FB_R_SOF1",,"23-0","frame_buffer_read_address_frame_1",,"0xfffffc",,,,,, -,,,,,,,,,,, -"FB_R_SOF2",,"23-0","frame_buffer_read_address_frame_2",,"0xfffffc",,,,,, -,,,,,,,,,,, -"FB_R_SIZE",,"29-20","fb_modulus",,"0x3ff","In 4-byte units",,,,, -"FB_R_SIZE",,"19-10","fb_y_size",,"0x3ff",,,,,, -"FB_R_SIZE",,"9-0","fb_x_size",,"0x3ff",,,,,, -,,,,,,,,,,, -"FB_W_SOF1",,"24-0","frame_buffer_write_address_frame_1",,"0x1fffffc",,,,,, -,,,,,,,,,,, -"FB_W_SOF2",,"24-0","frame_buffer_write_address_frame_2",,"0x1fffffc",,,,,, -,,,,,,,,,,, -"FB_X_CLIP",,"26-16","fb_x_clip_max",,"0x7ff",,,,,, -"FB_X_CLIP",,"10-0","fb_x_clip_min",,"0x7ff",,,,,, -,,,,,,,,,,, -"FB_Y_CLIP",,"25-16","fb_y_clip_max",,"0x3ff",,,,,, -"FB_Y_CLIP",,"9-0","fb_y_clip_min",,"0x3ff",,,,,, -,,,,,,,,,,, -"FPU_SHAD_SCALE","simple_shadow_enable",8,"parameter_selection_volume_mode",0,,,,,,, -"FPU_SHAD_SCALE","simple_shadow_enable",8,"intensity_volume_mode",1,,,,,,, -"FPU_SHAD_SCALE",,"7-0","scale_factor_for_shadows",,"0xff",,,,,, -,,,,,,,,,,, -"FPU_CULL_VAL",,"30-0","culling_comparison_value",,"float_0_8_23",,,,,, -,,,,,,,,,,, -"FPU_PARAM_CFG","region_header_type",21,"type_1",0,,,,,,, -"FPU_PARAM_CFG","region_header_type",21,"type_2",1,,,,,,, -"FPU_PARAM_CFG",,"19-14","tsp_parameter_burst_threshold",,"0x3f",,,,,, -"FPU_PARAM_CFG",,"13-8","isp_parameter_burst_threshold",,"0x3f",,,,,, -"FPU_PARAM_CFG",,"7-4","pointer_burst_size",,"0xf",,,,,, -"FPU_PARAM_CFG",,"3-0","pointer_first_burst_size",,"0xf",,,,,, -,,,,,,,,,,, -"HALF_OFFSET","tsp_texel_sampling_position",2,"top_left",1,,,,,,, -"HALF_OFFSET","tsp_texel_sampling_position",2,"center",1,,,,,,, -"HALF_OFFSET","tsp_pixel_sampling_position",1,"top_left",1,,,,,,, -"HALF_OFFSET","tsp_pixel_sampling_position",1,"center",1,,,,,,, -"HALF_OFFSET","fpu_pixel_sampling_position",0,"top_left",1,,,,,,, -"HALF_OFFSET","fpu_pixel_sampling_position",0,"center",1,,,,,,, -,,,,,,,,,,, -"FPU_PERP_VAL",,"30-0","perpendicular_triangle_compare",,"float_0_8_23",,,,,, -,,,,,,,,,,, -"ISP_BACKGND_D",,"31-4","background_plane_depth",,"float_1_8_19",,,,,, -,,,,,,,,,,, -"ISP_BACKGND_T",,28,"cache_bypass",1,,,,,,, -"ISP_BACKGND_T",,27,"shadow",1,,,,,,, -"ISP_BACKGND_T",,"26-24","skip",,"0b111",,,,,, -"ISP_BACKGND_T",,"23-3","tag_address",,"0x1fffff","In 32-bit units",,,,, -"ISP_BACKGND_T",,"2-0","tag_offset",,"0b111",,,,,, -,,,,,,,,,,, -"ISP_FEED_CFG",,"23-14","cache_size_for_translucency",,"0x3ff","Must be between 0x020 and 0x200",,,,, -"ISP_FEED_CFG",,"13-4","punch_through_chunk_size",,"0x3ff","Must be between 0x020 and 0x200, must be larger than cache_size_for_translucency",,,,, -"ISP_FEED_CFG",,3,"discard_mode",1,,,,,,, -"ISP_FEED_CFG",,0,"pre_sort_mode",1,,,,,,, -,,,,,,,,,,, -"SDRAM_REFRESH",,"7-0","refresh_counter_value",,"0xff",,,,,, -,,,,,,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","priority_only","0x0",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","rendered_data","0x1",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","texture_vq_index","0x2",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","texture_normal_data_and_vq_codebook","0x3",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","tile_accelerator_isp_tsp_data","0x4",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","tile_accelerator_pointers","0x5",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","sh4","0x6",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","tsp_parameters","0x7",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","tsp_region_data","0x8",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","isp_pointer_data","0x9",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","isp_parameters","0xa",,,,,,, -"SDRAM_ARB_CFG","override_value","21-18","crt_controller","0xb",,,,,,, -"SDRAM_ARB_CFG","arbiter_priority_control","17-16","priority_arbitration_only","0x0",,,,,,, -"SDRAM_ARB_CFG","arbiter_priority_control","17-16","override_value_field","0x1",,,,,,, -"SDRAM_ARB_CFG","arbiter_priority_control","17-16","round_robin_counter","0x2",,,,,,, -"SDRAM_ARB_CFG",,"15-8","arbiter_crt_page_break_latency_count_value",,"0xff",,,,,, -"SDRAM_ARB_CFG",,"7-0","arbiter_page_break_latency_count_value",,"0xff",,,,,, -,,,,,,,,,,, -"SDRAM_CFG",,"28-26","read_command_to_returned_data_delay",,"0b111",,,,,, -"SDRAM_CFG",,"25-23","cas_latency_value",,"0b111",,,,,, -"SDRAM_CFG",,"22-21","activate_to_activate_period",,"0b11",,,,,, -"SDRAM_CFG",,"20-18","read_to_write_period",,"0b111",,,,,, -"SDRAM_CFG",,"17-14","refresh_to_activate_period",,"0b1111",,,,,, -"SDRAM_CFG",,"11-10","pre_charge_to_activate_period",,"0b11",,,,,, -"SDRAM_CFG",,"9-6","activate_to_pre_charge_period",,"0b1111",,,,,, -"SDRAM_CFG",,"5-4","activate_to_read_write_command_period",,"0b11",,,,,, -"SDRAM_CFG",,"3-2","write_to_pre_charge_period",,"0b11",,,,,, -"SDRAM_CFG",,"1-0","read_to_pre_charge_period",,"0b11",,,,,, -,,,,,,,,,,, -"FOG_COL_RAM",,"23-16","red",,"0xff",,,,,, -"FOG_COL_RAM",,"15-8","green",,"0xff",,,,,, -"FOG_COL_RAM",,"7-0","blue",,"0xff",,,,,, -,,,,,,,,,,, -"FOG_COL_VERT",,"23-16","red",,"0xff",,,,,, -"FOG_COL_VERT",,"15-8","green",,"0xff",,,,,, -"FOG_COL_VERT",,"7-0","blue",,"0xff",,,,,, -,,,,,,,,,,, -"FOG_DENSITY",,"15-8","fog_scale_mantissa",,"0xff",,,,,, -"FOG_DENSITY",,"7-0","fog_scale_exponent",,"0xff",,,,,, -,,,,,,,,,,, -"FOG_CLAMP_MAX",,"31-24","alpha",,"0xff",,,,,, -"FOG_CLAMP_MAX",,"23-16","red",,"0xff",,,,,, -"FOG_CLAMP_MAX",,"15-8","green",,"0xff",,,,,, -"FOG_CLAMP_MAX",,"7-0","blue",,"0xff",,,,,, -,,,,,,,,,,, -"FOG_CLAMP_MIN",,"31-24","alpha",,"0xff",,,,,, -"FOG_CLAMP_MIN",,"23-16","red",,"0xff",,,,,, -"FOG_CLAMP_MIN",,"15-8","green",,"0xff",,,,,, -"FOG_CLAMP_MIN",,"7-0","blue",,"0xff",,,,,, -,,,,,,,,,,, -"SPG_TRIGGER_POS",,"25-16","trigger_v_count",,,,,,,, -"SPG_TRIGGER_POS",,"9-0","trigger_h_count",,,,,,,, -,,,,,,,,,,, -"SPG_HBLANK_INT",,"25-16","hblank_in_interrupt",,,,,,,, -"SPG_HBLANK_INT","hblank_int_mode","13-12","output_equal_line_comp_val","0x0",,,,,,, -"SPG_HBLANK_INT","hblank_int_mode","13-12","output_every_line_comp_val","0x1",,,,,,, -"SPG_HBLANK_INT","hblank_int_mode","13-12","output_every_line","0x2",,,,,,, -"SPG_HBLANK_INT",,"9-0","line_comp_val",,"0x3ff",,,,,, -,,,,,,,,,,, -"SPG_VBLANK_INT",,"25-16","vblank_out_interrupt_line_number",,"0x3ff",,,,,, -"SPG_VBLANK_INT",,"9-0","vblank_in_interrupt_line_number",,"0x3ff",,,,,, -,,,,,,,,,,, -"SPG_CONTROL","csync_on_h",9,"hsync",0,,,,,,, -"SPG_CONTROL","csync_on_h",9,"csync",1,,,,,,, -"SPG_CONTROL","sync_direction",8,"input",0,,,,,,, -"SPG_CONTROL","sync_direction",8,"output",1,,,,,,, -"SPG_CONTROL",,7,"pal",1,,,,,,, -"SPG_CONTROL",,6,"ntsc",1,,,,,,, -"SPG_CONTROL",,5,"force_field2",1,,,,,,, -"SPG_CONTROL",,4,"interlace",1,,,,,,, -"SPG_CONTROL",,3,"spg_lock",1,,,,,,, -"SPG_CONTROL","mcsync_pol",2,"active_low",0,,,,,,, -"SPG_CONTROL","mcsync_pol",2,"active_high",1,,,,,,, -"SPG_CONTROL","mvsync_pol",1,"active_low",0,,,,,,, -"SPG_CONTROL","mvsync_pol",1,"active_high",1,,,,,,, -"SPG_CONTROL","mhsync_pol",0,"active_low",0,,,,,,, -"SPG_CONTROL","mhsync_pol",0,"active_high",1,,,,,,, -,,,,,,,,,,, -"SPG_HBLANK",,"25-16","hbend",,"0x3ff",,,,,, -"SPG_HBLANK",,"9-0","hbstart",,"0x3ff",,,,,, -,,,,,,,,,,, -"SPG_LOAD",,"25-16","vcount",,"0x3ff",,,,,, -"SPG_LOAD",,"9-0","hcount",,"0x3ff",,,,,, -,,,,,,,,,,, -"SPG_VBLANK",,"25-16","vbend",,"0x3ff",,,,,, -"SPG_VBLANK",,"9-0","vbstart",,"0x3ff",,,,,, -,,,,,,,,,,, -"SPG_WIDTH",,"31-22","eqwidth",,"0x3ff",,,,,, -"SPG_WIDTH",,"21-12","bpwidth",,"0x3ff",,,,,, -"SPG_WIDTH",,"11-8","vswidth",,"0b1111",,,,,, -"SPG_WIDTH",,"6-0","hswidth",,"0x7f",,,,,, -,,,,,,,,,,, -"TEXT_CONTROL","code_book_endian",17,"little_endian",0,,,,,,, -"TEXT_CONTROL","code_book_endian",17,"big_endian",1,,,,,,, -"TEXT_CONTROL","index_endian",16,"little_endian",0,,,,,,, -"TEXT_CONTROL","index_endian",16,"big_endian",1,,,,,,, -"TEXT_CONTROL",,"12-8","bank_bit",,"0x1f",,,,,, -"TEXT_CONTROL",,"4-0","stride",,"0x1f",,,,,, -,,,,,,,,,,, -"VO_CONTROL",,21,"pclk_delay_reset",1,,,,,,, -"VO_CONTROL",,"20-16","pclk_delay",,"0b11111",,,,,, -"VO_CONTROL",,8,"pixel_double",1,,,,,,, -"VO_CONTROL","field_mode","7-4","use_field_flag_from_spg","0x0",,,,,,, -"VO_CONTROL","field_mode","7-4","use_inverse_of_field_flag_from_spg","0x1",,,,,,, -"VO_CONTROL","field_mode","7-4","field_1_fixed","0x2",,,,,,, -"VO_CONTROL","field_mode","7-4","field_2_fixed","0x3",,,,,,, -"VO_CONTROL","field_mode","7-4","field_1_when_the_active_edges_of_hsync_and_vsync_match","0x4",,,,,,, -"VO_CONTROL","field_mode","7-4","field_2_when_the_active_edges_of_hsync_and_vsync_match","0x5",,,,,,, -"VO_CONTROL","field_mode","7-4","field_1_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge","0x6",,,,,,, -"VO_CONTROL","field_mode","7-4","field_2_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge","0x7",,,,,,, -"VO_CONTROL","field_mode","7-4","inverted_at_the_active_edge_of_vsync","0x8",,,,,,, -"VO_CONTROL",,3,"blank_video",1,,,,,,, -"VO_CONTROL","blank_pol",2,"active_low",0,,,,,,, -"VO_CONTROL","blank_pol",2,"active_high",1,,,,,,, -"VO_CONTROL","vsync_pol",1,"active_low",0,,,,,,, -"VO_CONTROL","vsync_pol",1,"active_high",1,,,,,,, -"VO_CONTROL","hsync_pol",0,"active_low",0,,,,,,, -"VO_CONTROL","hsync_pol",0,"active_high",1,,,,,,, -,,,,,,,,,,, -"VO_STARTX",,"9-0","horizontal_start_position",,"0x3ff",,,,,, -,,,,,,,,,,, -"VO_STARTY",,"25-16","vertical_start_position_on_field_2",,"0x3ff",,,,,, -"VO_STARTY",,"9-0","vertical_start_position_on_field_1",,"0x3ff",,,,,, -,,,,,,,,,,, -"SCALER_CTL","field_select",18,"field_1",0,,,,,,, -"SCALER_CTL","field_select",18,"field_2",1,,,,,,, -"SCALER_CTL",,17,"interlace",1,,,,,,, -"SCALER_CTL",,16,"horizontal_scaling_enable",1,,,,,,, -"SCALER_CTL",,"15-0","vertical_scale_factor",,"0xffff",,,,,, -,,,,,,,,,,, -"PAL_RAM_CTRL","pixel_format","1-0","argb1555",0,,,,,,, -"PAL_RAM_CTRL","pixel_format","1-0","rgb565",1,,,,,,, -"PAL_RAM_CTRL","pixel_format","1-0","argb4444",2,,,,,,, -"PAL_RAM_CTRL","pixel_format","1-0","argb8888",3,,,,,,, -,,,,,,,,,,, -"SPG_STATUS",,13,"vsync",,,,,,,, -"SPG_STATUS",,12,"hsync",,,,,,,, -"SPG_STATUS",,11,"blank",,,,,,,, -"SPG_STATUS",,10,"fieldnum",,,,,,,, -"SPG_STATUS",,"9-0","scanline",,,,,,,, -,,,,,,,,,,, -"FB_BURSTCTRL",,"19-16","wr_burst",,"0b1111",,,,,, -"FB_BURSTCTRL",,"14-8","vid_lat",,"0x7f",,,,,, -"FB_BURSTCTRL",,"5-0","vid_burst",,"0x3f",,,,,," >" -,,,,,,,,,,, -"FB_C_SOF",,"23-0","frame_buffer_current_read_address",,,,,,,, -,,,,,,,,,,, -"Y_COEFF",,"15-8","coefficient_1",,"0xff",,,,,, -"Y_COEFF",,"7-0","coefficient_0_2",,"0xff",,,,,, -,,,,,,,,,,, -"PT_ALPHA_REF",,"7-0","alpha_reference_for_punch_through",,"0xff",,,,,, -,,,,,,,,,,, -"FOG_TABLE",,"15-0","fog_table_data",,"0xffff",,,,,, -,,,,,,,,,,, -"PALETTE_RAM",,"31-0","palette_data",,"0xffff_ffff",,,,,, -,,,,,,,,,,, -"TA_OL_BASE",,"23-0","base_address",,"0xffffe0","in 32-byte units",,,,, -,,,,,,,,,,, -"TA_ISP_BASE",,"23-0","base_address",,"0xfffffc","in 4-byte units",,,,, -,,,,,,,,,,, -"TA_OL_LIMIT",,"23-0","limit_address",,"0xffffe0","in 32-byte units",,,,, -,,,,,,,,,,, -"TA_ISP_LIMIT",,"23-0","limit_address",,"0xfffffc","in 4-byte units",,,,, -,,,,,,,,,,, -"TA_NEXT_OPB",,"23-0","address",,"0xffffe0","in 32-byte units",,,,, -,,,,,,,,,,, -"TA_ITP_CURRENT",,"23-0","address",,,,,,,, -,,,,,,,,,,, -"TA_GLOB_TILE_CLIP",,"19-16","tile_y_num",,"0xf",,,,,, -"TA_GLOB_TILE_CLIP",,"5-0","tile_x_num",,"0x1f",,,,,, -,,,,,,,,,,, -"TA_ALLOC_CTRL","opb_mode",20,"increasing_addresses",0,,,,,,, -"TA_ALLOC_CTRL","opb_mode",20,"decreasing_addresses",1,,,,,,, -"TA_ALLOC_CTRL","pt_opb","17-16","no_list",0,,,,,,, -"TA_ALLOC_CTRL","pt_opb","17-16","8x4byte",1,,,,,,, -"TA_ALLOC_CTRL","pt_opb","17-16","16x4byte",2,,,,,,, -"TA_ALLOC_CTRL","pt_opb","17-16","32x4byte",3,,,,,,, -"TA_ALLOC_CTRL","tm_opb","13-12","no_list",0,,,,,,, -"TA_ALLOC_CTRL","tm_opb","13-12","8x4byte",1,,,,,,, -"TA_ALLOC_CTRL","tm_opb","13-12","16x4byte",2,,,,,,, -"TA_ALLOC_CTRL","tm_opb","13-12","32x4byte",3,,,,,,, -"TA_ALLOC_CTRL","t_opb","9-8","no_list",0,,,,,,, -"TA_ALLOC_CTRL","t_opb","9-8","8x4byte",1,,,,,,, -"TA_ALLOC_CTRL","t_opb","9-8","16x4byte",2,,,,,,, -"TA_ALLOC_CTRL","t_opb","9-8","32x4byte",3,,,,,,, -"TA_ALLOC_CTRL","om_opb","5-4","no_list",0,,,,,,, -"TA_ALLOC_CTRL","om_opb","5-4","8x4byte",1,,,,,,, -"TA_ALLOC_CTRL","om_opb","5-4","16x4byte",2,,,,,,, -"TA_ALLOC_CTRL","om_opb","5-4","32x4byte",3,,,,,,, -"TA_ALLOC_CTRL","o_opb","1-0","no_list",0,,,,,,, -"TA_ALLOC_CTRL","o_opb","1-0","8x4byte",1,,,,,,, -"TA_ALLOC_CTRL","o_opb","1-0","16x4byte",2,,,,,,, -"TA_ALLOC_CTRL","o_opb","1-0","32x4byte",3,,,,,,, -,,,,,,,,,,, -"TA_LIST_INIT",,31,"list_init",1,,,,,,, -,,,,,,,,,,, -"TA_YUV_TEX_BASE",,"23-0","base_address",,"0xfffff8","in 8-byte units",,,,, -,,,,,,,,,,, -"TA_YUV_TEX_CTRL","yuv_form",24,"yuv420",0,,,,,,, -"TA_YUV_TEX_CTRL","yuv_form",24,"yuv422",1,,,,,,, -"TA_YUV_TEX_CTRL","yuv_tex",16,"one_texture",0,,,,,,, -"TA_YUV_TEX_CTRL","yuv_tex",16,"multiple_textures",1,,,,,,, -"TA_YUV_TEX_CTRL",,"13-8","yuv_v_size",,"0x3f",,,,,, -"TA_YUV_TEX_CTRL",,"5-0","yuv_u_size",,"0x3f",,,,,, -,,,,,,,,,,, -"TA_YUV_TEX_CNT",,"12-0","yuv_num",,,,,,,, -,,,,,,,,,,, -"TA_LIST_CONT",,31,"list_cont",1,,,,,,, -,,,,,,,,,,, -"TA_NEXT_OPB_INIT",,"23-0","address",,"0xffffe0","in 32-byte units",,,,, -,,,,,,,,,,, -"TA_OL_POINTERS",,31,"entry",,,,,,,, -"TA_OL_POINTERS",,30,"sprite",,,,,,,, -"TA_OL_POINTERS",,29,"triangle",,,,,,,, -"TA_OL_POINTERS",,"28-25","number_of_triangles_quads",,,,,,,, -"TA_OL_POINTERS",,24,"shadow",,,,,,,, -"TA_OL_POINTERS",,"23-2","pointer_address",,,,,,,, -"TA_OL_POINTERS",,"1-0","skip",,,,,,,, diff --git a/dreamcast2/regs/holly/object_list_bits.ods b/dreamcast2/regs/holly/object_list_bits.ods new file mode 100644 index 0000000000000000000000000000000000000000..b3408e6909c51995077f63763e2652c7d1f0dfe4 GIT binary patch literal 15687 zcmb7r1zc2H*EfoYv`9({$N0R$qs5};s$ke;C$s^&f#d{3U%dhbh2;lkWgW0Tg*AFPeRxu5uGt}zm(sRIA9 zkv6hi{DOBrvOH;! z;hC^eY!JI3uH8UcCbMVaff%HozGYO%Spm1BJn{h+O@uV`XvLR8xPJ-DQcJ~cGyS92 z$rJJLS&{toQf!k-)rOGDC!gL(MqnxRymJerss$^y^Tr;i2)ATxFLfF>3Hu-twsws6An*%y9l*jhiR^d z^(UNP8NDQ2c=qKSuTPt;X7Dq+Jm^y2X zZi=4c3kF7Ra&lQbFpQXUCVc4lq@r83Uzi3$_QlnK5noNoD~=o&a@0dpa1+6`>wwE0 z(4;3M_p@}C&Q|9`Sa!&>!w=Q-G|`W{wUtVRvM!==UfwgoTKlk)%&ob=`d%97EZ0-{ z7V!?wmrL2>^@eO}1^Z>l^^)1>`8TaI_cRCEvdihMy@50N1mBqZiJ!09Qy0VZ0)q^< ze9zLOXi_^?Jd^AmrJ4&8OjX9UMonLSEL*2ubUNN4>v}D?vZ`1R@xE+wrD%R6z%K)| zE^qfXb|^Gt!}>{VaYe?wNTMWGMM`S{tSRfGI3fYz~sZjFoF8= zUan2kuDhJ>9p~B-%CW(T=)cQJt3^nEvN;t++ffJc07=A5?1R|MMF_RI`GL;Tqp~4H zpN7g8QtS?t3Jt4hp7Dr^q*gJOTJl0zgG^|%rH-INWzyl0KHS0jh!CU^dc%;!{cr|Y;4ZCI{N7< zwYxB?sfXY3UV=_Gzn@F!J-x`T*h&3yVNp)Z67!?i$4}AI`#lYiE+u2x=7~K#qsiGP zea*ae7MYBOJMJvM#AVdJJ)N-yhI(mZ8^J7by4eY_#C!6c^}Sl;lw;!-16_Js8JA1% z$eMn7q*ce^?-rxd{eyHh*1nW3gF-Ny)@xH=Z|PZ;;k4^VopHYKJn^>Ij_Mn2AJ4DI z>-O1H_yg_TAM09IX~=|8!H&1gRDZ@K%$cqEKoCj_21WZC#b2Jz#i-FKg%dt~8;qGp zsw0Ce2&r~=pj`?^V6SOc_Lnlwy$W{uR1gAf9=)L&;4Q~mdasE-G~io zQ*fhs+Xp~Pd&tQ(qhb*{iO=z4!HpiFo2C8z4f1JowFS8L7;a$97Y&DAwtklIwJBx- ziTLI%LC*~4M+uf#t9d;|Ki^hX=`GK`A`8blTsPO&XmgUV$)nJdQm zGJYDS$h%CQT*gdz@2PXxq209lxWo3!>q@+9iqmT+7;_WWV=29QpF!EAbg(ezD;~B! zgIOfj>RMfd=n}7Gc+LF(~Vw-`9&Tc*%OV)rrkn zpyZA(J8@!2hh@*}(R;n|*`dQ-&6|0NSs?y#j+f8%pVW7xCOH1M=cS)k?G(}>+s86m zHI9F3Ib-PLbDvJGqQysr$Topc5o^iwMa?s@9;lLzB1Pc6Fk_zAthK`H9xCjQndo9= zi)`oYr{;w-dOK3MxtQY%ym*e9TH;RnsNu(UUE$Lf<3C-srW(e0y=wW-6lISGLu3eT8r>u8I1Bo2{B)HVx$ze}WB$#O74pMpd+ zRE}Ri3;i*`nz=4HFFG!`*LkzH!zk%9c{H)Q&qp#;9@^%d=INa;a7uc<5H9tFcKZC= zHruq;^U9;`e|>0|x@aTNYxwr5Pd0;gyr1IbRo+;Xjn#PRId_qx+EwUSlr<;z#IUc+ znH-=JJfx^*YRTU};!N&eJSXTEpUPR?K`q!xd~MgUSRu1eVwZ(mw-KE*h*66-lPbkD zOR{WlctL`ViF@H*WilEg9Y^@`ixHmk+1>bv5(Z|{Su#>$$k8rA{T2SLH^b1T$%?s; zhW1+dpSCC1C~xNK=4EH$dh5()b@d#l1&ICUOCG8lPrUAq-iAjsw6%;C)m5|%mQR?q zC`2noKf?GN3A;Yud$#E?2^@9@f0Pv)k6NSJ|JZZ()8IwDUYk(PS<1L0hR@e=LspZ?vue3v`A44XQkR|D-$71 zme7pXE$lC*t-wnT?4{r^r0F-b#0_n;#G|~_yWNE8dRVVT9cZ}qL%;pP^C0n*))COu z-P5$-WgZic?{B6Ajy#{Me{~5+G%K2%(ArXYsp$H$*{OO`_|B?Vh+Sc}DERHW`-FYi z3FLxssGF#@d+%4tLR`L|R=WNYr?x@#rE%8ItD)l-}6}6xrOolM) zo364*4X<%?a7j@ceyq^==28sar`_xogY==?WL#QFK0?CnXAT`B zOEa;<{>M)Zr127#A)m$Ya56d{{20bl`uVWuNb>2X78i2=!nP@2;3GfQL4Vg4dCZ+o z>mTHqWh>TcW09sHk?*|)l_nK#kKD!+zTpis+UD+kuI&IFFe0N^sV^h*iu?N>S!jLH z&9g@Y`v-QHK_2%X*}z`bkmqVUAu|O=GKSl0>=($Eqvq3$(~V9&?v3ggOHQ!D%EZX; zxwrbUDwfw=yQ)A~(H;Ly+2p)IQtI2q}17gj}e>vi>`$bJB zgR&?xL(k*!HO)3-gHb?tCi|9)HAKN)UE;@g0t<=W9?l2#1U6K2hk0E!c?7b>wS39^ zi&{9fuxeIeIf?rxcH}2pEKUQ#P9Bdus;xp6{F$yim9g;EtMwCyRB9{Kek#R0ia4u% zGt?QKPs-`kp4tT=-d@5~OO$yu^HGvZgH70G=-tyezU-J%?IXX%m7qfLD7Cj{yOTP3 zjprxzJ#Tr()Ak5Ghu|;$Qu%}P_8qjcVQlX&Dp00IQ>XZ9aT*IAB z7(9>`vUu8ED^1z*YD$(ACdMDe(&dUpWfZn)b4WP+oiwZ$CW=Wc{LRYB=mVC{6sFY zd1km?_ebYZF+sDhe-XkGc~iwBP+3wRiOm5nY4ysDcf^acH!kJS10kq<@ZPC zop(gJZ1*f>yidLFQjkH9Ro?WaH>)f>@F_8{^c&~ke*aah7?TIc(DoBKS7O+Ot47dR z%rZg(E4*Jz$bT|NJUOy!Y-6;TKW^yaL%>6!DE$4db6LSkh1j3~XzH76s`W~VH_bC# z+oZdT=9NMzX0F|FQn4>7q{1>sFcW^3M9nGFjZls_J>uvG|Im24e$rEWz$ivizV24G z^T@j0R2J9jri@&3U~ae@xwCFi)68mYckL(nGKez={3VMLXH-jAh6G>7gvI8kBF^^s zC*_+V;pw#5bPwl>cewkia%ZZo_|HHx)QJtE(%<)z%^f+&M4?w8*1z8#W4G% zL{<3!8H9c$UEZwpRniJVHZl5dAJ2E%Cp>2{2$0zHt2(TMXnr*Ai~90P`)*ouFqVmcZ3 zuxG+uv7?|0hgx~w?L|}-jPB$@TsS03?mCy>%NFiY%=Maaij?$TcNK1O+hG!{;9YY) ziNi_mtHz|JZD2-&+E9GR;5ZKrR-D~a?ia!fjox}Ptncv@N7CcNc+10;SK4b{yI>nO zTOBM8TF#UpZj)TYsO3{33E>y~C4vJ31DnWcdo5Ytjd)|L)a(?!h!=IK;?Ix3X~*t% zyuBme`fdiKU6&Sf`|x9r*icGlJn_>zY|!VUGC;1*{b>&t-UF%^u(yy`{u<=uql65j@3F|9Lg% zt?xW*XVNJL^n2n^arsTILE4Nf@8PMaDHmPzC8H?X;hQjPGIyC57G}+>ABj&2)^izK zW-&UNSQ>jN)nxA|i5O(jGwV-m#iIUaQSPEMZ1zVCJ-=^eo$liUCy%c*7uu!hMK^c-P} zPBL54j&znP>}>C{qx`3n+uzqVkI)xqtv3!B$AfmX?xpVfPL6ah_^=kw@q@7Xc`T@irl9n>zwkOgT7AKgH zE-(c80mP=d|b^VqHn3voB^yzRyVeKW(dh6>Et`tYhbnBBE8a&qe zoyQxSeLw3INgROFei)3yr8IH~UX`8!P27fXHh<0<69Xbxp=UjT-xTMyWYgkO8%ON)GG}XBDIsZt4BY?{E z_|4688dLqscir^ZIiHv_4?OZwCey?&kIaq}$gXQtCDQ@@nct8bN zRW!6aYN(^{0V=SC7JX*zj{0Y*tfVf7j*gClgF{3_L`g}>z`(%D%F4&bCnhE)BO{}z zsHmof_@R7#J8H9u9-Sl9H0Lva$*a3d+mN>+9=VTU&d2dPYV@ zrl+TumzTG;whj&suCK3A?cChl2w%kSqM^}z0?JCMdrobqgn4I);08^e_!(`V1oVEw zHMd1rHkZ?V+D$28$GV4K${m3J`Fno112#}Hkw$a4_%wQ%^Tl44oyS=8-gg6k+6@NQ z4u9{~Jb|U$xV_@Dl*R#1WTSgL&oR~7=#ogO@47&~SqOt&M)^!*c}nELSVeXh}P*E9fLD)?Q4_bSJ)*3x%4)8o#_`P;@ zBTbg3y|DD|fW$|6>=`GehE>0@DPn>a-C~EkTZKl+9n1Gr)u`yvpGw#743KeN*v3XDEn-68@8_oJ8PfCN9>i0p7_q$&m@}eTt zo0T+iKf|e#K%YGK{?3CB*9I80I2R1({zG8~A&s2xg2(GAL5o|bc+Uwm(=Sb)uLFrOdqca_4Pr8SSQ@)LpVqh6z4-)7smrzgBu5U z`CpEZmuNK>ECcZ>gob2NS@!l5*HW~GbA^r$+i*sys<=8?c(+F;*Cdu#8<9W(`Hlq+~wGPjz<;gclwRc)a z6801zwlA3v`^gnea=07rbGuL|_Zq(AP&9d_9DDleQn0y+8)w+yX^=R!S!lzTb`I>6 zyArwP43`4ZTM@aZX6;Xo-4!xp$w;;s$!?r(5L|VdxN{#uUQ<#pzdQN%A*CtdAlC_c z$X;s^mk)KMh#m5)`KIT;O*ORTJB*i6uh-X$5h1>EoP&PmJ^EemI78-VnP6#3zRMw~yv9a?l3Nmy!#&?KT$t!e> zd}jZ+mVnog%-`2$-pVpS@MBtnWt7biUG~)oDCgIYZ_=sRT#8J%zMqUm2UR$>D>*rx zsywal!k#X!DG|Xd(HC9!qFfuJDi6#KW|`^O7ZE8+5PpDD>@7T}b;dCxuW?TA%Jbew zkHoR$@MO$wq_9-gta`hIkSjz05?zhQm&*Fs7BDlzJcnH69o*0jdhiOp7;FouULAK- zxKHium|+C=S-7U%Kh148zAZ{RnAbsXtQW97=;3h%Js`8N#347YO ztk6uJV4$Ndv-GNT6L}F~(=>n zDoM?6tLYT67GGw!i%cxwrxpMkiYZbs)4ik(+*a(0>%L_-%^a!b=gIu-LMhI!epxKT zBDB&Zb=-ydF)|*!uBH=JuJ&QW^dP-{HY*DBsXZ4T$Nc=}PEx@I`TYG&p%f=xM+d$j z+X!*}B4K@qtt}PT9%}&$SnhxcoZKwR`Dst@*l+f|SvH#ZvMgwif&`SvGio1#B`CNN zmbw2D%V%!U*vpVtsXWOxx@w^4^c!d&$NNTKZdKU_wVO|Shn4gjgT+8)vXZ;z)B&Q(^W&P; zk4+VmBUZIe4i%iI*vjOO7yR85fe*C+_-v1X{fXhJ4MbdJEKwd$?e*b~(?3EIgp)f!dS693*0ZCq!|H z@orZ^z|OZo)|+;?l%^?S<0}^ueDxh3uA$`p6mW$HJ09bP5`J%khXHQ_=5JzwwhlH4 zWX`n_z&fy`5{0FtN&mZmbE>?}1h>RTF#m~rFv~VLZ3ps1$s3x13+R)OK}9TT832BV zFA_iJz>$#=@#R}yB;3dp3;>`(w{|z7eE9(&rPmB`)X587gcWOqDb)f1e&b9arSp)C zT`NGuBq0a??02}2DWVNNZv9e8*MC0XEl^N3!EJrxD#`Y@3rv6pndC>X*tt+(fD;1< zsD^Ose4(U!T>n1)u>UR*%#fX$8%e!-*#^(w z`*|8$x7ST>r?TBMBA-rT@yI0pqSYR>v02c!ZbsLV(X!m;{A*QJ6R_SiXduV$a-x3Ikm| zI!X$NE+8?=MLpHV`Aq z!?$kTh|kO$kv*l%%FRmL)GUsO$TZZ!Khy#7=Yol=UdBWwIcPEC3AS={y7=H#)gMvP z942S5y1xdoi;sP%A!##g)Es`9_Ws;`qnUfG;;n7IkjDK>1(MXwQ_Qs&m0Lk?`#FLo z;L>+8RE8f=fABdMCr|dyY2jGUX2v!H==bK%S_d9|#!lm#VrOciczyvtda4;%k!Yht z&OYRroLHIlI>#wHifS)QlN)^NpUa)W>>8k^5Tfbyxg}!P9^Y3HtT>|mAc4fSZ}BV&=d_{9yr?qVTq{Y3Tu5}V6mX+S(PZSa`>RWMO|xL~2?!~z`{k5~F+zoZS?tamc$U>5wEE zcao~&`)KpR48(Gu1#Bcg9HLa~V-M)7#_$Q;YfhAaexU zAfAWBB@s*@6j-7sXj(*S#0yQs0&E}Km&E|fe3V3lxS?zKu*yV50QHtPyH7JbJONlz z_wz9V2T+uf;I`nzG&y)e2AK65fY)iE3{e}L5~`#t&I?uKf>vo4u<$_V6Hk$T0Q(s$ z#Ih*LKF)^&aX5~MV49HmK_w-Mrmy<(eEY+#yhwq{{u)sM9%$t+RL7_GIz*LpMR}ns zmrVok$?x#-ND*AoRYq9jkJ)cwz_Or&fB|@~V|@8>m6EPOFMJdwGSvaUVoEp!4krLN zUzKq|4;e?gTtr7>;9|~-ekU5J5ik7s& z6P}tMe+2UCB+mVqD^75eQA*UF-?Vwjt>Anvl1LK+OuORVeAwf!L?OKKt75oG1Qt9C zTZH-30Sua?wOR|m6^v_`jph4rLvNS>SD6w>=~Rd}CLlrrdL=1=)cp*p73^2?PFU(P zMlhxEiPFGm7%$+$ux;3@)Dxf)4^nUsh%)8j5O4hf_)R~PfvbBU`fe8mg97ER-0NIP8P zChnl+f)24KN9_ZNV1Ticy+l=9)#S#=oE4Y^3*8WtpCsx5@$xQ-KeXS8jIu=Nxp-`K z!?n)fB?*UV=kTAaJEx3*t4ax^B7l9G$xj_{^`%C%Ujn-3>W7#T_6X5WMxTO(^62^?jl*qSP0W?2Fj zv+x3?503t|%c$+2N;R910Nu}nih^Qtkt+MZ-Qm4uEJ@xSSxZh% zFac^fO~LP2-Cuw*b1+d|o}P^tdS(By0LhKIb5#G{Ah;j1#@Rd67aBv zpzxRTEe=4<&1l8zOM3$!h+qjeXXX7xC^hh7TJQFS{2p+3=%J)lm~j&&yY#@^E)gs? z6N$MBySC?$Q_^kB897Eon|@q6bmzM=2lO$gmA3(J+Tik9f?L<7g#8B8Ruwt4eeeon zS+#Qes6cy&GaM35F)T1<<4v4)C_!x$pJ|XP{eg6t5-kG z2&D(kFU=Yn;=29EVOgl=vr?3XK*XAH;Vy(g+)!cMpF(GFi~d}i7QqgS+ii-e zpZsrwS08&=XD~c)3^a0Ce`6mxEVBli6G5iMA6iHt=L8NtvvS(tB`zLL(`M|J_b1Z- zM|V~LzfX`_qNta8(@Td>&fp%hYFJIE2fGWH?>PM1g}Ua}Zznyd6+n)(v7gELmnI)d zo~-#IDxTQqbyo_B%Ss>{L>i3|Yctda1uf329UYAUA8w~B3~02vV@wVNe+3N_oB(kE zv#G8gzm)J&Km&)LAl|085`${3=EH>_;}1Exq6d1J*x9kVV5r4Y?hDHQlykeMiuk+j z6`Y0tx4l<>H{vh@Qp-87^QN6i+*hYuZWsnR-^pp*12#z|`5^*rb+u|lzjkDtk@4ft zr}tst8H6|w)atHy`3*Z1ISbA8&MwX$0i!bPt&**(HPv;gA@-u?Sp-)h7_*;5Bvw&7 zpkk|B;s?F-Oml-LyQlDgE~Y+%f})Y+i|W`7IGb9*7;ZJ8qnpDuh}Vo}`fB06mEe08 z8!GQJT~NR=a8pnMx+vl-{%Oxl`AKnziV!33#CtL-#X;nRyqe&lzYcwF$6~-a+_v}C z!a+_&ddW%T&-I)Kf{P^4U{P+z_t{%y$Ke@Li4l2e@EJ5Ppd(!2=>5XrxpLF+uOg72u ziy9HFPPP%PH;2Fz=aGX#ov|f0JX^yS4Hp@yndi`4Uqn@ns9{FOq8PKae4X?aw#->& zM+UnuLR;r@=P92uV)@x#MaQDbSA zOvwBs{*a(Xbk6v-XAMP&MjZugbzs`JrJ^_3N$a28`v{bg^jRF*Nxe(t-N@0@u_&BYex)RVoGNYPf|^+( z`dTv8(X7w-@i`BG&tY|D)tzu|g{V$=?hLi)h>$tX+D$4j&Beo*C&9x6aaVGHA0HE% zcpV^ttTIJ?JfOCr5_lBvrb7h-;-Fo<=f_`@dK1rgV+8Q)ncdS=O583&_IV!I?L;DH z+u&(~(Nl(~cb^;~KWfnPB;c;f^2d@q=hOS>ZK}(I+=t`0_3hG*MYhE)Sgi8$;7u5C z+OZezXhYS}q_zAtKo8KM7SRfWB>K_AR@EY8UNu;wbWsMG^6F>00xNlcah?!TwWZ>a zK<=p}9OCoilcn(m@T471qh4BUsIDC)kSAscpAjLu=PAG@(}-3t4Mhm_9UZKxWhrcnySynuTYJLd)D zLA;|VLKNbj#{+j&mw#=+UP%lvH7G{3Dxy540)QPg;VZBmrZl&MHxjpfK)D9g{p&Cq zh*E8VMC8AF(YJd69}r&-^hI!LFFSb){>!ob;>Gb9H*kFIm1^#+ zE{FjK@AGy#IFa-#-6`?mC;1Je@9Hn8cMIO>mh>AB;s(z+3_@Fr&e-xnZ;8ZUubu$x za7i3RcWOqXd=_tZ`J$E)>Ucd1TmuN6(7O!_>5u&$;@Of-yV3q8{$#pWM`ohlsufad zp2OY}1Iu}LfNE~X%UtnAMbsgQJno1QaP8>mnqH zDi3s5c0#E!iytnsm}-p+9a4`JQag!_@^BYY+_}8Z@Dn&Z(ws||zB`bZsg{^zosByq z^ZaLAXh^FiD0h*UWE_+9c&#+#rU+VOUXjbEk29qWta&t^0gcSiB!!8spBmNL`OwR;SG;gfvQgPd6d(nW-M$ypP#N(s>Iedz2b z^Ass!x%1XNjlb@7Y;wK-b%RM%!L2;JY}-u3VXDU`K0eXlVE=aDA-p@#*c^H#Fw}0| z$x<=Ds5+uB{CxKS0!0N35_59H=SZGgT%;{Dg(A8tnUqy8npAhqhl$2Jtt)l1-%4=H zeA0^cUla{e8Vw;@*dRv<8^^#{Db7Ot~hqs z249v}5`l6dAFbkwpk7{hi~KMFv&=x!0u@fsFeRX}-aVTg4PwpwaSHD`sOL%ob}Ay+5?ehWZ09_T<= zn}txc_PDUS783=fbH?M z+qFeMt-SmT6*dB%7D3M60&!Sp^thnb8SbdyL*=Nj&m7ZL46rF2l33O(6vGtni%8no zo8>`v?T!2jh(Dw}g`3!g7asO7HRQjV5eIBP?}N{OXA)n0Vj*+^pR8mIE-_&ePMel$d{OqI$%mU( zn{Jjqjhha6&I(Gp*9}NN)XN4B5~Lr5+M#$$74F7W6Z0d~!MRqY9d}F-O+>kA>#%-% z+k}>{6E0t7mkxPdJklW|S_i60Y431xwbdO*4k^jRFud;#2j&^$AeT!I`>}^a?i4F9tzJH;DS=|&c_2?dBr0#&^IWn zr}?f>PQzd)^28YN#uyQlNT$sk2Xf7qwXcMpr$BUlvEL#E`)BEV5kbta#rfk89KYMQ z!9D5({nlal^mZ#SLs!RhaoF{{8R`oj;{RLR>tDtiI2`5Zv$7N4M7f>j|HJ08`$fZP zVUzFX)accTV53(2A@vAfr!J6%B1o^3)?t*)v*kSwBQakK26Q zkQi`FE%0BmX49AnP6As_I@wTJsjzCzwhcYj#h~UrC{Jb5U6R(q1Q}dV<(id9o_H)S z+m7%J`5$=26;Onf@4xFJ*!a@+qz5e348dqM}`0jjK|)kqy<$ z!I2iu@8Z}q%A9wO} zpW;zuJ7sq}&nMN(^;!F{@i4bFUFq17X(c$fqDdsv5T%NOd{kIb4SlIx3qj9GaUXl> zlir#waqwg7_XwUMj>B$VJQKW&pHmj8ajj0y?S$igGdx66RP2ez@7rp4>1T1 zYX#7&+lXTlou+j}7>4`44AFaL*xBppXXP{wR9LT%=7IRuJK_?94Ki`pZN{(gMH3uH zSf*xtXi~icau@ht7GgSM$8||-Heb#(jtE8b$JvNY@18vzrST4uQVZra9+8a?p=3># zcg?ZNAbCR?v@FX|lGV*iUFjs(>$xfHbVM8I%<-YiGo_i*R-!p`u9J*gzN7v%#%TR0 zoiW2T!Dco_CsKdkHfId=D4$f%-#8$OXhj?^)3}I*RI+@m)RC{I}rSW^WTgpRMu<}Ov<74$wRpl z;h^?P9{6^Sv~y|R2oW4J-O}mfuh+(*pQp+6oR_}5Csv$%^SJ56>S5AszQ-t`X(QJK#pFKN*#99;<% z_8l9jK;yG)&7yVbDIvpc5h=-%9abanUmnTb%S9W)m+t{Oez2G7e~<;O`{KY(zM0PP zbI%vYxYX5M+08n>I%!kj-k|2F8~z{{$=kARas?`t1Lym`b0QGBw+JMfq!L@$K5}S+ zqw`bhTw5Ta>I*|abJ@@B7cB5=PohY-?JHS_47yho!j`|Qh(fmhIUH;{G+I&s{h1Z{B!Gn$f2R#@)!RoA5hi* z#`#}t#=i%<<>38Mx>42t2KzI+@$ZrTJUn#NH2yE7|6n`*JM<-A8g6LNBOg^Nbdgc8U8bS@?S{569E5{ z8hD#P_(y@Dkp68uP;AQIAL8F7|C57uOC9{9M52;+P^8}9h=l(w^`E)^xBRp}iV?=2 z*lPbR_@6nDx9LKE6n0d<{~!kZx7>f`DE)bWV4^?gOa3nTcR5Udw75$4_ZdyUqx?Qi k|7ksL?eZT*TkvnJw6Y=wD%leajS%%`figNjgl<3m9}N literal 0 HcmV?d00001 diff --git a/dreamcast2/regs/holly/region_array_bits.csv b/dreamcast2/regs/holly/region_array_bits.csv deleted file mode 100644 index 8ac03fa..0000000 --- a/dreamcast2/regs/holly/region_array_bits.csv +++ /dev/null @@ -1,10 +0,0 @@ -"register_name","enum_name","bits","bit_name","value","mask","description" -"tile",,31,"last_region",1,, -"tile",,30,"z_clear",1,, -"tile",,29,"pre_sort",1,, -"tile",,28,"flush_accumulate",1,, -"tile",,"13-8","y_position",,"0x3f", -"tile",,"7-2","x_position",,"0x3f", -,,,,,, -"list_pointer",,31,"empty",1,, -"list_pointer",,"23-0","object_list",,"0xfffffc", diff --git a/dreamcast2/regs/sh7091/sh7091.csv b/dreamcast2/regs/sh7091/sh7091.csv deleted file mode 100644 index c5e7eae..0000000 --- a/dreamcast2/regs/sh7091/sh7091.csv +++ /dev/null @@ -1,126 +0,0 @@ -"block","offset","address","size","name","r/w","description" -"CCN","00","0000",4,"PTEH","RW","Page table entry high register" -"CCN","00","0004",4,"PTEL","RW","Page table entry low register" -"CCN","00","0008",4,"TTB","RW","Translation table base register" -"CCN","00","000c",4,"TEA","RW","TLB exception address register" -"CCN","00","0010",4,"MMUCR","RW","MMU control register" -"CCN","00","0014",1,"BASRA","RW","Break ASID register A" -"CCN","00","0018",1,"BASRB","RW","Break ASID register B" -"CCN","00","001c",4,"CCR","RW","Cache control register" -"CCN","00","0020",4,"TRA","RW","TRAPA exception register" -"CCN","00","0024",4,"EXPEVT","RW","Exception event register" -"CCN","00","0028",4,"INTEVT","RW","Interrupt event register" -"CCN","00","0034",4,"PTEA","RW","Page table entry assistance register" -"CCN","00","0038",4,"QACR0","RW","Queue address control register 0" -"CCN","00","003c",4,"QACR1","RW","Queue address control register 1" -,,,,,, -"UBC","20","0000",4,"BARA","RW","Break address register A" -"UBC","20","0004",1,"BAMRA","RW","Break address mask register A" -"UBC","20","0008",2,"BBRA","RW","Break bus cycle register A" -"UBC","20","000c",4,"BARB","RW","Break address register B" -"UBC","20","0010",1,"BAMRB","RW","Break address mask register B" -"UBC","20","0014",2,"BBRB","RW","Break bus cycle register B" -"UBC","20","0018",4,"BDRB","RW","Break data register B" -"UBC","20","001c",4,"BDMRB","RW","Break data mask register B" -"UBC","20","0020",2,"BRCR","RW","Break control register" -,,,,,, -"BSC","80","0000",4,"BCR1","RW","Bus control register 1" -"BSC","80","0004",2,"BCR2","RW","Bus control register 2" -"BSC","80","0008",4,"WCR1","RW","Wait state control register 1" -"BSC","80","000c",4,"WCR2","RW","Wait state control register 2" -"BSC","80","0010",4,"WCR3","RW","Wait state control register 3" -"BSC","80","0014",4,"MCR","RW","Memory control register" -"BSC","80","0018",2,"PCR","RW","PCMCIA control register" -"BSC","80","001c",2,"RTCSR","RW","Refresh timer control/status register" -"BSC","80","0020",2,"RTCNT","RW","Refresh timer counter" -"BSC","80","0024",2,"RTCOR","RW","Refresh timer constant counter" -"BSC","80","0028",2,"RFCR","RW","Refresh count register" -"BSC","80","002c",4,"PCTRA","RW","Port control register A" -"BSC","80","0030",2,"PDTRA","RW","Port data register A" -"BSC","80","0040",4,"PCTRB","RW","Port control register B" -"BSC","80","0044",2,"PDTRB","RW","Port data register B" -"BSC","80","0048",2,"GPIOIC","RW","GPIO interrupt control register" -"BSC","90","0000",65536,"SDMR2","W","Synchronous DRAM mode registers" -"BSC","94","0000",65536,"SDMR3","W","Synchronous DRAM mode registers" -,,,,,, -"DMAC","a0","0000",4,"SAR0","RW","DMA source address register 0" -"DMAC","a0","0004",4,"DAR0","RW","DMA destination address register 0" -"DMAC","a0","0008",4,"DMATCR0","RW","DMA transfer count register 0" -"DMAC","a0","000c",4,"CHCR0","RW","DMA control register 0" -"DMAC","a0","0010",4,"SAR1","RW","DMA source address register 1" -"DMAC","a0","0014",4,"DAR1","RW","DMA destination address register 1" -"DMAC","a0","0018",4,"DMATCR1","RW","DMA transfer count register 1" -"DMAC","a0","001c",4,"CHCR1","RW","DMA control register 1" -"DMAC","a0","0020",4,"SAR2","RW","DMA source address register 2" -"DMAC","a0","0024",4,"DAR2","RW","DMA destination address register 2" -"DMAC","a0","0028",4,"DMATCR2","RW","DMA transfer count register 2" -"DMAC","a0","002c",4,"CHCR2","RW","DMA control register 2" -"DMAC","a0","0030",4,"SAR3","RW","DMA source address register 3" -"DMAC","a0","0034",4,"DAR3","RW","DMA destination address register 3" -"DMAC","a0","0038",4,"DMATCR3","RW","DMA transfer count register 3" -"DMAC","a0","003c",4,"CHCR3","RW","DMA control register 3" -"DMAC","a0","0040",4,"DMAOR","RW","DMA operation register" -,,,,,, -"CPG","c0","0000",2,"FRQCR","RW","Frequency control register" -"CPG","c0","0004",1,"STBCR","RW","Standby control register" -"CPG","c0","0008",2,"WTCNT","RW","Watchdog timer counter" -"CPG","c0","000c",2,"WTCSR","RW","Watchdog timer control/status register" -"CPG","c0","0010",1,"STBCR2","RW","Standby control register 2" -,,,,,, -"RTC","c8","0000",1,"R64CNT","R","64 Hz counter" -"RTC","c8","0004",1,"RSECCNT","RW","Second counter" -"RTC","c8","0008",1,"RMINCNT","RW","Minute counter" -"RTC","c8","000c",1,"RHRCNT","RW","Hour counter" -"RTC","c8","0010",1,"RWKCNT","RW","Day-of-week counter" -"RTC","c8","0014",1,"RDAYCNT","RW","Day counter" -"RTC","c8","0018",1,"RMONCNT","RW","Month counter" -"RTC","c8","001c",2,"RYRCNT","RW","Year counter" -"RTC","c8","0020",1,"RSECAR","RW","Second alarm register" -"RTC","c8","0024",1,"RMINAR","RW","Minute alarm register" -"RTC","c8","0028",1,"RHRAR","RW","Hour alarm register" -"RTC","c8","002c",1,"RWKAR","RW","Day-of-week alarm register" -"RTC","c8","0030",1,"RDAYAR","RW","Day alarm register" -"RTC","c8","0034",1,"RMONAR","RW","Month alarm register" -"RTC","c8","0038",1,"RCR1","RW","RTC control register 1" -"RTC","c8","003c",1,"RCR2","RW","RTC control register 2" -,,,,,, -"INTC","d0","0000",2,"ICR","RW","Interrupt control register" -"INTC","d0","0004",2,"IPRA","RW","Interrupt priority register A" -"INTC","d0","0008",2,"IPRB","RW","Interrupt priority register B" -"INTC","d0","000c",2,"IPRC","RW","Interrupt priority register C" -,,,,,, -"TMU","d8","0000",1,"TOCR","RW","Timer output control register" -"TMU","d8","0004",1,"TSTR","RW","Timer start register" -"TMU","d8","0008",4,"TCOR0","RW","Timer constant register 0" -"TMU","d8","000c",4,"TCNT0","RW","Timer counter 0" -"TMU","d8","0010",2,"TCR0","RW","Timer control register 0" -"TMU","d8","0014",4,"TCOR1","RW","Timer constant register 1" -"TMU","d8","0018",4,"TCNT1","RW","Timer counter 1" -"TMU","d8","001c",2,"TCR1","RW","Timer control register 1" -"TMU","d8","0020",4,"TCOR2","RW","Timer constant register 2" -"TMU","d8","0024",4,"TCNT2","RW","Timer counter 2" -"TMU","d8","0028",2,"TCR2","RW","Timer control register 2" -"TMU","d8","002c",4,"TCPR2","R","Timer input capture register 2" -,,,,,, -"SCI","e0","0000",1,"SCSMR1","RW","Serial mode register 1" -"SCI","e0","0004",1,"SCBRR1","RW","Bit rate register 1" -"SCI","e0","0008",1,"SCSCR1","RW","Serial control register 1" -"SCI","e0","000c",1,"SCTDR1","RW","Transmit data register 1" -"SCI","e0","0010",1,"SCSSR1","RW","Serial status register 1" -"SCI","e0","0014",1,"SCRDR1","R","Receive data register 1" -"SCI","e0","0018",1,"SCSCMR1","RW","Smart card mode register 1" -"SCI","e0","001c",1,"SCSPTR1","RW","Serial port register" -,,,,,, -"SCIF","e8","0000",2,"SCSMR2","RW","Serial mode register 2" -"SCIF","e8","0004",1,"SCBRR2","RW","Bit rate register 2" -"SCIF","e8","0008",2,"SCSCR2","RW","Serial control register 2" -"SCIF","e8","000c",1,"SCFTDR2","W","Transmit FIFO data register 2" -"SCIF","e8","0010",2,"SCFSR2","RW","Serial status register 2" -"SCIF","e8","0014",1,"SCFRDR2","R","Receive FIFO data register 2" -"SCIF","e8","0018",2,"SCFCR2","RW","FIFO control register" -"SCIF","e8","001c",2,"SCFDR2","R","FIFO data count register" -"SCIF","e8","0020",2,"SCSPTR2","RW","Serial port register 2" -"SCIF","e8","0024",2,"SCLSR2","RW","Line status register 2" -,,,,,, -"UDI","f0","0000",2,"SDIR","R","Instruction register" -"UDI","f0","0008",4,"SDDR","R","Data register" diff --git a/dreamcast2/regs/sh7091/sh7091_bits.csv b/dreamcast2/regs/sh7091/sh7091_bits.csv deleted file mode 100644 index 59efd22..0000000 --- a/dreamcast2/regs/sh7091/sh7091_bits.csv +++ /dev/null @@ -1,366 +0,0 @@ -"block","register_name","enum_name","bits","bit_name","value","mask","description" -"CCN","PTEH",,"31-10","VPN",,,"Virtual Page Number" -"CCN","PTEH",,"7-0","ASID",,,"Address space identifier" -,,,,,,, -"CCN","PTEL",,"28-10","PPN",,,"Physical page number" -"CCN","PTEL","V","8","invalid","0",,"Validity" -"CCN","PTEL","V","8","valid","1",,"Validity" -"CCN","PTEL","SZ","7,4","1_kbyte_page","0b0000",,"Page size" -"CCN","PTEL","SZ","7,4","4_kbyte_page","0b0001",,"Page size" -"CCN","PTEL","SZ","7,4","64_kbyte_page","0b1000",,"Page size" -"CCN","PTEL","SZ","7,4","1_mbyte_page","0b1001",,"Page size" -"CCN","PTEL","PR","6-5","read_only_in_privileged_mode","0b00",,"Protection key data" -"CCN","PTEL","PR","6-5","read_write_in_privileged_mode","0b01",,"Protection key data" -"CCN","PTEL","PR","6-5","read_only_in_privileged_and_user_mode","0b10",,"Protection key data" -"CCN","PTEL","PR","6-5","read_write_in_privileged_and_user_mode","0b11",,"Protection key data" -"CCN","PTEL","C","3","not_cacheable","0",,"Cacheability bit" -"CCN","PTEL","C","3","cacheable","1",,"Cacheability bit" -"CCN","PTEL","D","2","write_has_not_been_performed","0",,"Dirty bit" -"CCN","PTEL","D","2","write_has_been_performed","1",,"Dirty bit" -"CCN","PTEL","SH","1","pages_are_shared_by_processes","0",,"Share status bit" -"CCN","PTEL","SH","1","pages_are_not_shared_by_processes","1",,"Share status bit" -"CCN","PTEL","WT","0","copy_back_mode","0",,"Write-through bit" -"CCN","PTEL","WT","0","write_through_mode","1",,"Write-through bit" -,,,,,,, -"CCN","MMUCR",,"31-26","LRUI",,,"Least recently used ITLB" -"CCN","MMUCR",,"23-18","URB",,,"UTLB replace boundary" -"CCN","MMUCR",,"15-10","URC",,,"UTLB replace counter" -"CCN","MMUCR","SQMD","9","user_privileged_access_possible","0",,"Store queue mode bit" -"CCN","MMUCR","SQMD","9","privileged_access_possible","1",,"Store queue mode bit" -"CCN","MMUCR","SV","8","multiple_virtual_memory_mode","0",,"Single virtual mode bit" -"CCN","MMUCR","SV","8","single_virtual_memory_mode","1",,"Single virtual mode bit" -"CCN","MMUCR","TI","2","invalidate_all_utlb_itlb_bits","1",,"TLB invalidate" -"CCN","MMUCR","AT","0","mmu_disabled","0",,"Address translation bit" -"CCN","MMUCR","AT","0","mmu_enabled","1",,"Address translation bit" -,,,,,,, -"CCN","BASRA",,"7-0","basa",,"0xff", -,,,,,,, -"CCN","BASRB",,"7-0","basa",,"0xff", -,,,,,,, -"CCN","CCR","IIX","15","address_bits_12_5_used_for_ic_entry_selection","0",,"IC index enable" -"CCN","CCR","IIX","15","address_bits_25_and_11_5_used_for_ic_entry_selection","1",,"IC index enable" -"CCN","CCR","ICI","11","clear_v_bits_of_all_ic_entries","1",,"IC invalidation" -"CCN","CCR","ICE","8","ic_not_used","0",,"IC enable" -"CCN","CCR","ICE","8","ic_used","1",,"IC enable" -"CCN","CCR","OIX","7","address_bits_13_5_used_for_oc_entry_selection","0",,"OC index enable" -"CCN","CCR","OIX","7","address_bits_25_and_12_5_used_for_oc_entry_selection","1",,"OC index enable" -"CCN","CCR","ORA","5","16_kbytes_used_as_cache","0",,"OC RAM enable" -"CCN","CCR","ORA","5","8_kbytes_used_as_cache_8_kbytes_used_as_ram","1",,"OC RAM enable" -"CCN","CCR","OCI","3","clear_v_and_u_bits_of_all_oc_entries","1",,"OC invalidation" -"CCN","CCR","CB","2","write_through_mode","0",,"Copy-back enable" -"CCN","CCR","CB","2","copy_back_mode","1",,"Copy-back enable" -"CCN","CCR","WT","1","copy_back_mode","0",,"Write-through enable" -"CCN","CCR","WT","1","write_through_mode","1",,"Write-through enable" -"CCN","CCR","OCE","0","oc_not_used","0",,"OC enable" -"CCN","CCR","OCE","0","oc_used","1",,"OC enable" -,,,,,,, -"CCN","TRA",,"9-2","imm",,, -,,,,,,, -"CCN","EXPEVT",,"11-0","exception_code",,, -,,,,,,, -"CCN","INTEVT",,"11-0","exception_code",,, -,,,,,,, -"CCN","PTEA","TC","3","area_5_is_used","0",,"Timing control bit" -"CCN","PTEA","TC","3","area_6_is_used","1",,"Timing control bit" -"CCN","PTEA","SA","2-0","undefined","0b000",,"Space attribute bits" -"CCN","PTEA","SA","2-0","variable_size_io_space","0b001",,"Space attribute bits" -"CCN","PTEA","SA","2-0","8_bit_io_space","0b010",,"Space attribute bits" -"CCN","PTEA","SA","2-0","16_bit_io_space","0b011",,"Space attribute bits" -"CCN","PTEA","SA","2-0","8_bit_common_memory_space","0b100",,"Space attribute bits" -"CCN","PTEA","SA","2-0","16_bit_common_memory_space","0b101",,"Space attribute bits" -"CCN","PTEA","SA","2-0","8_bit_attribute_memory_space","0b110",,"Space attribute bits" -"CCN","PTEA","SA","2-0","16_bit_attribute_memory_space","0b111",,"Space attribute bits" -,,,,,,, -"CCN","QACR0",,"4-2","area",,"0b111", -,,,,,,, -"CCN","QACR1",,"4-2","area",,"0b111", -,,,,,,, -"DMAC","DMATCR",,"23-0","transfer_count",,"0xffffff", -,,,,,,, -"DMAC","CHCR","SSA","31-29","reserved_in_pcmcia_access","0b000",, -"DMAC","CHCR","SSA","31-29","dynamic_bus_sizing_io_space","0b001",, -"DMAC","CHCR","SSA","31-29","8_bit_io_space","0b010",, -"DMAC","CHCR","SSA","31-29","16_bit_io_space","0b011",, -"DMAC","CHCR","SSA","31-29","8_bit_common_memory_space","0b100",, -"DMAC","CHCR","SSA","31-29","16_bit_common_memory_space","0b101",, -"DMAC","CHCR","SSA","31-29","8_bit_attribute_memory_space","0b110",, -"DMAC","CHCR","SSA","31-29","16_bit_attribute_memory_space","0b111",, -"DMAC","CHCR","STC","28","c5_space_wait_cycle_selection","0",, -"DMAC","CHCR","STC","28","c6_space_wait_cycle_selection","1",, -"DMAC","CHCR","DSA","27-25","reserved_in_pcmcia_access","0b000",, -"DMAC","CHCR","DSA","27-25","dynamic_bus_sizing_io_space","0b001",, -"DMAC","CHCR","DSA","27-25","8_bit_io_space","0b010",, -"DMAC","CHCR","DSA","27-25","16_bit_io_space","0b011",, -"DMAC","CHCR","DSA","27-25","8_bit_common_memory_space","0b100",, -"DMAC","CHCR","DSA","27-25","16_bit_common_memory_space","0b101",, -"DMAC","CHCR","DSA","27-25","8_bit_attribute_memory_space","0b110",, -"DMAC","CHCR","DSA","27-25","16_bit_attribute_memory_space","0b111",, -"DMAC","CHCR","DTC","24","c5_space_wait_cycle_selection","0",, -"DMAC","CHCR","DTC","24","c6_space_wait_cycle_selection","1",, -"DMAC","CHCR","DS","19","low_level_detection","0",, -"DMAC","CHCR","DS","19","falling_edge_detection","1",, -"DMAC","CHCR","RL","18","drak_is_an_active_high","0",, -"DMAC","CHCR","RL","18","drak_is_an_active_low","1",, -"DMAC","CHCR","AM","17","dack_is_output_in_read_cycle","0",, -"DMAC","CHCR","AM","17","dack_is_output_in_write_cycle","1",, -"DMAC","CHCR","AL","16","active_high_output","0",, -"DMAC","CHCR","AL","16","active_low_output","1",, -"DMAC","CHCR","DM","15-14","destination_address_fixed","0b00",, -"DMAC","CHCR","DM","15-14","destination_address_incremented","0b01",, -"DMAC","CHCR","DM","15-14","destination_address_decremented","0b10",, -"DMAC","CHCR","SM","13-12","source_address_fixed","0b00",, -"DMAC","CHCR","SM","13-12","source_address_incremented","0b01",, -"DMAC","CHCR","SM","13-12","source_address_decremented","0b10",, -"DMAC","CHCR","RS","11-8","resource_select",,"0b1111", -"DMAC","CHCR","TM","7","cycle_steal_mode","0",, -"DMAC","CHCR","TM","7","cycle_burst_mode","1",, -"DMAC","CHCR","TS","6-4","64_bit","0b000",, -"DMAC","CHCR","TS","6-4","8_bit","0b001",, -"DMAC","CHCR","TS","6-4","16_bit","0b010",, -"DMAC","CHCR","TS","6-4","32_bit","0b011",, -"DMAC","CHCR","TS","6-4","32_byte","0b100",, -"DMAC","CHCR","IE","2","interrupt_request_not_generated","0",, -"DMAC","CHCR","IE","2","interrupt_request_generated","1",, -"DMAC","CHCR","TE","1","transfers_not_completed","0",, -"DMAC","CHCR","TE","1","transfers_completed","1",, -"DMAC","CHCR","DE","0","channel_operation_disabled","0",, -"DMAC","CHCR","DE","0","channel_operation_enabled","1",, -,,,,,,, -"DMAC","DMAOR","DDT","15","normal_dma_mode","0",, -"DMAC","DMAOR","DDT","15","on_demand_data_transfer_mode","1",, -"DMAC","DMAOR","PR","9-8","ch0_ch1_ch2_ch3","0b00",, -"DMAC","DMAOR","PR","9-8","ch0_ch2_ch3_ch1","0b01",, -"DMAC","DMAOR","PR","9-8","ch2_ch0_ch1_ch3","0b10",, -"DMAC","DMAOR","PR","9-8","round_robin","0b11",, -"DMAC","DMAOR","AE","2","no_address_error__dma_transfer_enabled","0",, -"DMAC","DMAOR","AE","2","address_error__dma_transfer_disabled","1",, -"DMAC","DMAOR","NMIF","1","no_nmi__dma_transfer_enabled","0",, -"DMAC","DMAOR","NMIF","1","nmi__dma_transfer_disabled","1",, -"DMAC","DMAOR","DME","0","operation_disabled_on_all_channels","0",, -"DMAC","DMAOR","DME","0","operation_enabled_on_all_channels","1",, -,,,,,,, -"INTC","ICR","NMIL","15","pin_input_level_is_low","0",, -"INTC","ICR","NMIL","15","pin_input_level_is_high","1",, -"INTC","ICR","MAI","14","interrupts_enabled_while_nmi_pin_is_low","0",, -"INTC","ICR","MAI","14","interrupts_disabled_while_nmi_pin_is_low","1",, -"INTC","ICR","NMIB","9","interrupt_requests_witheld","0",, -"INTC","ICR","NMIB","9","interrupt_requests_detected","1",, -"INTC","ICR","NMIE","8","interrupt_on_falling_edge_of_nmi","0",, -"INTC","ICR","NMIE","8","interrupt_on_rising_edge_of_nmi","1",, -"INTC","ICR","IRLM","7","level_encoded_interrupt_requests","0",, -"INTC","ICR","IRLM","7","independent_interrupt_request","1",, -,,,,,,, -"INTC","IPRA",,"15-12","TMU0",,"0b1111", -"INTC","IPRA",,"11-8","TMU1",,"0b1111", -"INTC","IPRA",,"7-4","TMU2",,"0b1111", -"INTC","IPRA",,"3-0","RTC",,"0b1111", -,,,,,,, -"INTC","IPRB",,"15-12","WDT",,"0b1111", -"INTC","IPRB",,"11-8","REF",,"0b1111", -"INTC","IPRB",,"7-4","SCI1",,"0b1111", -,,,,,,, -"INTC","IPRC",,"15-12","GPIO",,"0b1111", -"INTC","IPRC",,"11-8","DMAC",,"0b1111", -"INTC","IPRC",,"7-4","SCIF",,"0b1111", -"INTC","IPRC",,"3-0","UDI",,"0b1111", -,,,,,,, -"TMU","TOCR","TCOE","0","tclk_is_external_clock_or_input_capture","0",,"Timer Clock Pin Control" -"TMU","TOCR","TCOE","0","tclk_is_on_chip_rtc","1",,"Timer Clock Pin Control" -,,,,,,, -"TMU","TSTR","STR2","2","counter_start","1",,"Counter Start 2" -"TMU","TSTR","STR1","1","counter_start","1",,"Counter Start 1" -"TMU","TSTR","STR0","0","counter_start","1",,"Counter Start 0" -,,,,,,, -"TMU","TCR0",,"8","UNF","1",,"Underflow Flag" -"TMU","TCR0",,"5","UNIE","1",,"Underflow Interrupt Control" -"TMU","TCR0","CKEG","4-3","rising","0b00",,"Clock Edge" -"TMU","TCR0","CKEG","4-3","falling","0b01",,"Clock Edge" -"TMU","TCR0","CKEG","4-3","rising_falling","0b10",,"Clock Edge" -"TMU","TCR0","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler" -"TMU","TCR0","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler" -"TMU","TCR0","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler" -"TMU","TCR0","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler" -"TMU","TCR0","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler" -"TMU","TCR0","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler" -"TMU","TCR0","TPSC","2-0","external","0b111",,"Timer Prescaler" -,,,,,,, -"TMU","TCR1",,"8","UNF","1",,"Underflow Flag" -"TMU","TCR1",,"5","UNIE","1",,"Underflow Interrupt Control" -"TMU","TCR1","CKEG","4-3","rising","0b00",,"Clock Edge" -"TMU","TCR1","CKEG","4-3","falling","0b01",,"Clock Edge" -"TMU","TCR1","CKEG","4-3","rising_falling","0b10",,"Clock Edge" -"TMU","TCR1","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler" -"TMU","TCR1","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler" -"TMU","TCR1","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler" -"TMU","TCR1","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler" -"TMU","TCR1","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler" -"TMU","TCR1","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler" -"TMU","TCR1","TPSC","2-0","external","0b111",,"Timer Prescaler" -,,,,,,, -"TMU","TCR2",,"9","ICPF","1",,"Input Capture Interrupt Flag" -"TMU","TCR2",,"8","UNF","1",,"Underflow Flag" -"TMU","TCR2","ICPE","7-6","disabled","0b00",,"Input Capture Control" -"TMU","TCR2","ICPE","7-6","enabled","0b10",,"Input Capture Control" -"TMU","TCR2","ICPE","7-6","enabled_with_interrupts","0b11",,"Input Capture Control" -"TMU","TCR2",,"5","UNIE","1",,"Underflow Interrupt Control" -"TMU","TCR2","CKEG","4-3","rising","0b00",,"Clock Edge" -"TMU","TCR2","CKEG","4-3","falling","0b01",,"Clock Edge" -"TMU","TCR2","CKEG","4-3","rising_falling","0b10",,"Clock Edge" -"TMU","TCR2","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler" -"TMU","TCR2","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler" -"TMU","TCR2","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler" -"TMU","TCR2","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler" -"TMU","TCR2","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler" -"TMU","TCR2","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler" -"TMU","TCR2","TPSC","2-0","external","0b111",,"Timer Prescaler" -,,,,,,, -"SCIF","SCSMR2","CHR","6","8_bit_data","0",, -"SCIF","SCSMR2","CHR","6","7_bit_data","1",, -"SCIF","SCSMR2","PE","5","parity_disabled","0",, -"SCIF","SCSMR2","PE","5","parity_enabled","1",, -"SCIF","SCSMR2","OE","4","even_parity","0",, -"SCIF","SCSMR2","OE","4","odd_parity","1",, -"SCIF","SCSMR2","STOP","3","1_stop_bit","0",, -"SCIF","SCSMR2","STOP","3","2_stop_bits","1",, -"SCIF","SCSMR2","CKS","1-0","p_phi_clock","0b00",, -"SCIF","SCSMR2","CKS","1-0","p_phi_4_clock","0b01",, -"SCIF","SCSMR2","CKS","1-0","p_phi_16_clock","0b10",, -"SCIF","SCSMR2","CKS","1-0","p_phi_64_clock","0b11",, -,,,,,,, -"SCIF","SCSCR2","TIE","7","transmit_fifo_data_empty_interrupt_disabled","0",, -"SCIF","SCSCR2","TIE","7","transmit_fifo_data_empty_interrupt_enabled","1",, -"SCIF","SCSCR2","RIE","6","request_disabled","0",, -"SCIF","SCSCR2","RIE","6","request_enabled","1",, -"SCIF","SCSCR2","TE","5","transmission_disabled","0",, -"SCIF","SCSCR2","TE","5","transmission_enabled","1",, -"SCIF","SCSCR2","RE","4","reception_disabled","0",, -"SCIF","SCSCR2","RE","4","reception_enabled","1",, -"SCIF","SCSCR2","REIE","3","requests_disabled","0",, -"SCIF","SCSCR2","REIE","3","requests_enabled","1",, -"SCIF","SCSCR2","CKE1","1","sck2_pin_functions_as_input_pin","0",, -"SCIF","SCSCR2","CKE1","1","sck2_pin_functions_as_clock_input","1",, -,,,,,,, -"SCIF","SCFSR2","PER3_0","15-12","number_of_parity_errors",,, -"SCIF","SCFSR2","FER3_0","11-8","number_of_framing_errors",,, -"SCIF","SCFSR2","ER","7","no_framing_error_or_parity_error","0",, -"SCIF","SCFSR2","ER","7","framing_error_or_parity_error","1",, -"SCIF","SCFSR2","TEND","6","transmission_in_progress","0",, -"SCIF","SCFSR2","TEND","6","transmission_has_ended","1",, -"SCIF","SCFSR2","TDFE","5","transmit_data_bytes_does_exceed_trigger","0",, -"SCIF","SCFSR2","TDFE","5","transmit_data_bytes_does_not_exceed_trigger","1",, -"SCIF","SCFSR2","BRK","4","break_not_received","0",, -"SCIF","SCFSR2","BRK","4","break_received","1",, -"SCIF","SCFSR2","FER","3","no_framing_error","0",, -"SCIF","SCFSR2","FER","3","framing_error","1",, -"SCIF","SCFSR2","PER","2","parity_error","0",, -"SCIF","SCFSR2","PER","2","no_parity_error","1",, -"SCIF","SCFSR2","RDF","1","receive_data_bytes_less_than_receive_trigger","0",, -"SCIF","SCFSR2","RDF","1","receive_data_bytes_greater_than_or_equal_receive_trigger","1",, -"SCIF","SCFSR2","DR","0","reception_is_in_progress","0",, -"SCIF","SCFSR2","DR","0","no_further_data_has_arrived","1",, -,,,,,,, -"SCIF","SCFCR2","RTRG","7-6","trigger_on_1_byte","0b00",, -"SCIF","SCFCR2","RTRG","7-6","trigger_on_4_bytes","0b01",, -"SCIF","SCFCR2","RTRG","7-6","trigger_on_8_bytes","0b10",, -"SCIF","SCFCR2","RTRG","7-6","trigger_on_14_byte","0b11",, -"SCIF","SCFCR2","TTRG","5-4","trigger_on_8_bytes","0b00",, -"SCIF","SCFCR2","TTRG","5-4","trigger_on_4_bytes","0b01",, -"SCIF","SCFCR2","TTRG","5-4","trigger_on_2_bytes","0b10",, -"SCIF","SCFCR2","TTRG","5-4","trigger_on_1_bytes","0b11",, -"SCIF","SCFCR2","MCE","3","modem_signals_disabled","0",, -"SCIF","SCFCR2","MCE","3","modem_signals_enabled","1",, -"SCIF","SCFCR2","TFRST","2","reset_operation_disabled","0",, -"SCIF","SCFCR2","TFRST","2","reset_operation_enabled","1",, -"SCIF","SCFCR2","RFRST","1","reset_operation_disabled","0",, -"SCIF","SCFCR2","RFRST","1","reset_operation_enabled","1",, -"SCIF","SCFCR2","LOOP","0","loopback_test_disabled","0",, -"SCIF","SCFCR2","LOOP","0","loopback_test_enabled","1",, -,,,,,,, -"SCIF","SCFDR2",,"12-8","transmit_data_bytes",,, -"SCIF","SCFDR2",,"4-0","receive_data_bytes",,, -,,,,,,, -"SCIF","SCSPTR2","RTSIO","7","rtsdt_not_output_to_rts2","0",, -"SCIF","SCSPTR2","RTSIO","7","rtsdt_output_to_rts2","1",, -"SCIF","SCSPTR2","RTSDT","6","input_output_data_is_low_level","0",, -"SCIF","SCSPTR2","RTSDT","6","input_output_data_is_high_level","1",, -"SCIF","SCSPTR2","CTSIO","5","ctsdt_is_not_output_to_cts2","0",, -"SCIF","SCSPTR2","CTSIO","5","ctsdt_is_output_to_cts2","1",, -"SCIF","SCSPTR2","CTSDT","4","input_output_data_is_low_level","0",, -"SCIF","SCSPTR2","CTSDT","4","input_output_data_is_high_level","1",, -"SCIF","SCSPTR2","SPB2IO","1","spb2dt_is_not_output_to_txd2","0",, -"SCIF","SCSPTR2","SPB2IO","1","spb2dt_is_output_to_txd2","1",, -"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_low_level","0",, -"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_high_level","1",, -,,,,,,, -"SCIF","SCLSR2","ORER","0","overrun_error_occured","1",, -,,,,,,, -"SH","SR",,"30","md","1",, -"SH","SR",,"29","rb","1",, -"SH","SR",,"28","bl","1",, -"SH","SR",,"15","fd","1",, -"SH","SR",,"9","m","1",, -"SH","SR",,"8","q","1",, -"SH","SR",,"7-4","imask",,"0b1111", -"SH","SR",,"1","s","1",, -"SH","SR",,"0","t","1",, -,,,,,,, -"SH","FPSCR",,"21","fr","1",, -"SH","FPSCR",,"20","sz","1",, -"SH","FPSCR",,"19","pr","1",, -"SH","FPSCR",,"18","dn","1",, -"SH","FPSCR","CAUSE","17-12","fpu_error","0b100000",, -"SH","FPSCR","CAUSE","17-12","invalid_operation","0b010000",, -"SH","FPSCR","CAUSE","17-12","division_by_zero","0b001000",, -"SH","FPSCR","CAUSE","17-12","overflow","0b000100",, -"SH","FPSCR","CAUSE","17-12","underflow","0b000010",, -"SH","FPSCR","CAUSE","17-12","inexact","0b000001",, -"SH","FPSCR","ENABLED","11-7","invalid_operation","0b10000",, -"SH","FPSCR","ENABLED","11-7","division_by_zero","0b01000",, -"SH","FPSCR","ENABLED","11-7","overflow","0b00100",, -"SH","FPSCR","ENABLED","11-7","underflow","0b00010",, -"SH","FPSCR","ENABLED","11-7","inexact","0b00001",, -"SH","FPSCR","FLAG","6-2","invalid_operation","0b10000",, -"SH","FPSCR","FLAG","6-2","division_by_zero","0b01000",, -"SH","FPSCR","FLAG","6-2","overflow","0b00100",, -"SH","FPSCR","FLAG","6-2","underflow","0b00010",, -"SH","FPSCR","FLAG","6-2","inexact","0b00001",, -"SH","FPSCR","RM","1-0","round_to_nearest","0b00",, -"SH","FPSCR","RM","1-0","round_to_zero","0b01",, -,,,,,,, -"UBC","BAMRA","BAMA","3,1,0","all_bara_bits_are_included_in_break_conditions","0b0000",, -"UBC","BAMRA","BAMA","3,1,0","lower_10_bits_of_bara_are_not_included_in_break_conditions","0b0001",, -"UBC","BAMRA","BAMA","3,1,0","lower_12_bits_of_bara_are_not_included_in_break_conditions","0b0010",, -"UBC","BAMRA","BAMA","3,1,0","all_bara_bits_are_not_included_in_break_conditions","0b0011",, -"UBC","BAMRA","BAMA","3,1,0","lower_16_bits_of_bara_are_not_included_in_break_conditions","0b1000",, -"UBC","BAMRA","BAMA","3,1,0","lower_20_bits_of_bara_are_not_included_in_break_conditions","0b1001",, -"UBC","BAMRA","BASMA","2","all_basra_bits_are_included_in_break_conditions","0",, -"UBC","BAMRA","BASMA","2","no_basra_bits_are_included_in_break_conditions","1",, -,,,,,,, -"UBC","BBRA","SZA","6,1,0","operand_size_is_not_included_in_break_conditions","0b00",, -"UBC","BBRA","SZA","6,1,0","byte_access_is_used_as_break_condition","0b01",, -"UBC","BBRA","SZA","6,1,0","word_access_is_used_as_break_condition","0b10",, -"UBC","BBRA","SZA","6,1,0","longword_access_is_used_as_break_condition","0b11",, -"UBC","BBRA","SZA","6,1,0","quadword_access_is_used_as_break_condition","0b1000000",, -"UBC","BBRA","IDA","5-4","condition_comparison_is_not_performed","0b00",, -"UBC","BBRA","IDA","5-4","instruction_access_cycle_is_used_as_break_condition","0b01",, -"UBC","BBRA","IDA","5-4","operand_access_cycle_is_used_as_break_condition","0b10",, -"UBC","BBRA","IDA","5-4","instruction_access_cycle_or_operand_access_cycle_is_used_as_break_condition","0b11",, -"UBC","BBRA","RWA","3-2","condition_comparison_is_not_performed","0b00",, -"UBC","BBRA","RWA","3-2","read_cycle_is_used_as_break_condition","0b01",, -"UBC","BBRA","RWA","3-2","write_cycle_is_used_as_break_condition","0b10",, -"UBC","BBRA","RWA","3-2","read_cycle_or_write_cycle_is_used_as_break_condition","0b11",, -,,,,,,, -"UBC","BRCR","CMFA","15","channel_a_break_condition_is_not_matched","0",, -"UBC","BRCR","CMFA","15","channel_a_break_condition_match_has_occured","1",, -"UBC","BRCR","CMFB","14","channel_b_break_condition_is_not_matched","0",, -"UBC","BRCR","CMFB","14","channel_b_break_condition_match_has_occured","1",, -"UBC","BRCR","PCBA","10","channel_a_pc_break_is_effected_before_instruction_execution","0",, -"UBC","BRCR","PCBA","10","channel_a_pc_break_is_effected_after_instruction_execution","1",, -"UBC","BRCR","DBEB","7","data_bus_condition_is_not_included_in_channel_b_conditions","0",, -"UBC","BRCR","DBEB","7","data_bus_condition_is_included_in_channel_b_conditions","1",, -"UBC","BRCR","PCBB","6","channel_b_pc_break_is_effected_before_instruction_execution","0",, -"UBC","BRCR","PCBB","6","channel_b_pc_break_is_effected_after_instruction_execution","1",, -"UBC","BRCR","SEQ","3","channel_a_and_b_comparison_are_performed_as_independent_condition","0",, -"UBC","BRCR","SEQ","3","channel_a_and_b_comparison_are_performed_as_sequential_condition","1",, -"UBC","BRCR","UBDE","0","user_break_debug_function_is_not_used","0",, -"UBC","BRCR","UBDE","0","user_break_debug_function_is_used","1",, diff --git a/dreamcast2/regs/systembus/systembus.csv b/dreamcast2/regs/systembus/systembus.csv deleted file mode 100644 index 6e8983e..0000000 --- a/dreamcast2/regs/systembus/systembus.csv +++ /dev/null @@ -1,163 +0,0 @@ -"block","address","size","name","r/w","description" -"SYSTEMBUS","000","4","C2DSTAT","RW","CH2-DMA destination address" -"SYSTEMBUS","004","4","C2DLEN","RW","CH2-DMA length" -"SYSTEMBUS","008","4","C2DST","RW","CH2-DMA start" -,,,,, -"SYSTEMBUS","010","4","SDSTAW","RW","Sort-DMA start link table address" -"SYSTEMBUS","014","4","SDBAAW","RW","Sort-DMA link base address" -"SYSTEMBUS","018","4","SDWLT","RW","Sort-DMA link address bit width" -"SYSTEMBUS","01c","4","SDLAS","RW","Sort-DMA link address shift control" -"SYSTEMBUS","020","4","SDST","RW","Sort-DMA start" -,,,,, -"SYSTEMBUS","040","4","DBREQM","RW","DBREQ# signal mask control" -"SYSTEMBUS","044","4","BAVLWC","RW","BAVL# signal wait count" -"SYSTEMBUS","048","4","C2DPYRC","RW","DMA (TA/Root Bus) priority count" -"SYSTEMBUS","04c","4","DMAXL","RW","CH2-DMA maximum burst length" -,,,,, -"SYSTEMBUS","080","4","TFREM","R","TA FIFO remaining amount" -"SYSTEMBUS","084","4","LMMODE0","RW","Via TA texture memory bus select 0" -"SYSTEMBUS","088","4","LMMODE1","RW","Via TA texture memory bus select 1" -"SYSTEMBUS","08c","4","FFST","R","FIFO status" -"SYSTEMBUS","090","4","SFRES","W","System reset" -,,,,, -"SYSTEMBUS","09c","4","SBREV","R","System bus revision number" -"SYSTEMBUS","0a0","4","RBSPLT","RW","SH4 Root Bus split enable" -,,,,, -"SYSTEMBUS","100","4","ISTNRM","RW","Normal interrupt status" -"SYSTEMBUS","104","4","ISTEXT","R","External interrupt status" -"SYSTEMBUS","108","4","ISTERR","RW","Error interrupt status" -,,,,, -"SYSTEMBUS","110","4","IML2NRM","RW","Level 2 normal interrupt mask" -"SYSTEMBUS","114","4","IML2EXT","RW","Level 2 external interrupt mask" -"SYSTEMBUS","118","4","IML2ERR","RW","Level 2 error interrupt mask" -,,,,, -"SYSTEMBUS","120","4","IML4NRM","RW","Level 4 normal interrupt mask" -"SYSTEMBUS","124","4","IML4EXT","RW","Level 4 external interrupt mask" -"SYSTEMBUS","128","4","IML4ERR","RW","Level 4 error interrupt mask" -,,,,, -"SYSTEMBUS","130","4","IML6NRM","RW","Level 6 normal interrupt mask" -"SYSTEMBUS","134","4","IML6EXT","RW","Level 6 external interrupt mask" -"SYSTEMBUS","138","4","IML6ERR","RW","Level 6 error interrupt mask" -,,,,, -"SYSTEMBUS","140","4","PDTNRM","RW","Normal interrupt PVR-DMA startup mask" -"SYSTEMBUS","144","4","PDTEXT","RW","External interrupt PVR-DMA startup mask" -,,,,, -"SYSTEMBUS","150","4","G2DTNRM","RW","Normal interrupt G2-DMA startup mask" -"SYSTEMBUS","154","4","G2DTEXT","RW","External interrupt G2-DMA startup mask" -,,,,, -"MAPLE_IF","04","4","MDSTAR","RW","Maple-DMA command table address" -,,,,, -"MAPLE_IF","10","4","MDTSEL","RW","Maple-DMA trigger select" -"MAPLE_IF","14","4","MDEN","RW","Maple-DMA enable" -"MAPLE_IF","18","4","MDST","RW","Maple-DMA start" -,,,,, -"MAPLE_IF","80","4","MSYS","RW","Maple system control" -"MAPLE_IF","84","4","MST","R","Maple status" -"MAPLE_IF","88","4","MSHTCL","W","Maple-DMA hard trigger clear" -"MAPLE_IF","8c","4","MDAPRO","W","Maple-DMA address range" -,,,,, -"MAPLE_IF","e8","4","MMSEL","RW","Maple MSP selection" -,,,,, -"MAPLE_IF","f4","4","MTXDAD","R","Maple TXD address counter" -"MAPLE_IF","f8","4","MRXDAD","R","Maple RXD address counter" -"MAPLE_IF","fc","4","MRXDBD","R","Maple RXD address base" -,,,,, -"G1_IF","04","4","GDSTAR","RW","GD-DMA start address" -"G1_IF","08","4","GDLEN","RW","GD-DMA length" -"G1_IF","0c","4","GDDIR","RW","GD-DMA direction" -,,,,, -"G1_IF","14","4","GDEN","RW","GD-DMA enable" -"G1_IF","18","4","GDST","RW","GD-DMA start" -,,,,, -"G1_IF","80","4","G1RRC","W","System ROM read access timing" -"G1_IF","84","4","G1RWC","W","System ROM write access timing" -"G1_IF","88","4","G1FRC","W","Flash ROM read access timing" -"G1_IF","8c","4","G1FWC","W","Flash ROM write access timing" -"G1_IF","90","4","G1CRC","W","GD PIO read access timing" -"G1_IF","94","4","G1CWC","W","GD PIO write access timing" -,,,,, -"G1_IF","a0","4","G1GDRC","W","GD-DMA read access timing" -"G1_IF","a4","4","G1GDWC","W","GD-DMA write access timing" -,,,,, -"G1_IF","b0","4","G1SYSM","R","System mode" -"G1_IF","b4","4","G1CRDYC","W","G1IORDY signal control" -"G1_IF","b8","4","GDAPRO","W","GD-DMA address range" -,,,,, -"G1_IF","e4","4","GDUNLOCK","W","(undocumented unlock register)" -"G1_IF","f4","4","GDSTARD","R","GD-DMA address count (on Root Bus)" -"G1_IF","f8","4","GDLEND","R","GD-DMA transfer counter" -,,,,, -"G2_IF","00","4","ADSTAG","RW","ACIA:G2-DMA G2 start address" -"G2_IF","04","4","ADSTAR","RW","ACIA:G2-DMA system memory start address" -"G2_IF","08","4","ADLEN","RW","ACIA:G2-DMA length" -"G2_IF","0c","4","ADDIR","RW","ACIA:G2-DMA direction" -"G2_IF","10","4","ADTSEL","RW","ACIA:G2-DMA trigger select" -"G2_IF","14","4","ADEN","RW","ACIA:G2-DMA enable" -"G2_IF","18","4","ADST","RW","ACIA:G2-DMA start" -"G2_IF","1c","4","ADSUSP","RW","ACIA:G2-DMA suspend" -,,,,, -"G2_IF","20","4","E1STAG","RW","Ext1:G2-DMA start address" -"G2_IF","24","4","E1STAR","RW","Ext1:G2-DMA system memory start address" -"G2_IF","28","4","E1LEN","RW","Ext1:G2-DMA length" -"G2_IF","2c","4","E1DIR","RW","Ext1:G2-DMA direction" -"G2_IF","30","4","E1TSEL","RW","Ext1:G2-DMA trigger select" -"G2_IF","34","4","E1EN","RW","Ext1:G2-DMA enable" -"G2_IF","38","4","E1ST","RW","Ext1:G2-DMA start" -"G2_IF","3c","4","E1SUSP","RW","Ext1:G2-DMA suspend" -,,,,, -"G2_IF","40","4","E2STAG","RW","Ext2:G2-DMA start address" -"G2_IF","44","4","E2STAR","RW","Ext2:G2-DMA system memory start address" -"G2_IF","48","4","E2LEN","RW","Ext2:G2-DMA length" -"G2_IF","4c","4","E2DIR","RW","Ext2:G2-DMA direction" -"G2_IF","50","4","E2TSEL","RW","Ext2:G2-DMA trigger select" -"G2_IF","54","4","E2EN","RW","Ext2:G2-DMA enable" -"G2_IF","58","4","E2ST","RW","Ext2:G2-DMA start" -"G2_IF","5c","4","E2SUSP","RW","Ext2:G2-DMA suspend" -,,,,, -"G2_IF","60","4","DDSTAG","RW","Dev:G2-DMA start address" -"G2_IF","64","4","DDSTAR","RW","Dev:G2-DMA system memory start address" -"G2_IF","68","4","DDLEN","RW","Dev:G2-DMA length" -"G2_IF","6c","4","DDDIR","RW","Dev:G2-DMA direction" -"G2_IF","70","4","DDTSEL","RW","Dev:G2-DMA trigger select" -"G2_IF","74","4","DDEN","RW","Dev:G2-DMA enable" -"G2_IF","78","4","DDST","RW","Dev:G2-DMA start" -"G2_IF","7c","4","DDSUSP","RW","Dev:G2-DMA suspend" -,,,,, -"G2_IF","80","4","G2ID","R","G2 bus version" -,,,,, -"G2_IF","90","4","G2DSTO","RW","G2/DS timeout" -"G2_IF","94","4","G2TRTO","RW","G2/TR timeout" -"G2_IF","98","4","G2MDMTO","RW","Modem unit wait timeout" -"G2_IF","9c","4","G2MDMW","RW","Modem unit wait time" -,,,,, -"G2_IF","bc","4","G2APRO","W","G2-DMA address range" -,,,,, -"G2_IF","c0","4","ADSTAGD","R","AICA-DMA address counter (on AICA)" -"G2_IF","c4","4","ADSTARD","R","AICA-DMA address counter (on root bus)" -"G2_IF","c8","4","ADLEND","R","AICA-DMA transfer counter" -,,,,, -"G2_IF","d0","4","E1STAGD","R","Ext-DMA1 address counter (on Ext)" -"G2_IF","d4","4","E1STARD","R","Ext-DMA1 address counter (on root bus)" -"G2_IF","d8","4","E1LEND","R","Ext-DMA1 transfer counter" -,,,,, -"G2_IF","e0","4","E2STAGD","R","Ext-DMA2 address counter (on Ext)" -"G2_IF","e4","4","E2STARD","R","Ext-DMA2 address counter (on root bus)" -"G2_IF","e8","4","E2LEND","R","Ext-DMA2 transfer counter" -,,,,, -"G2_IF","f0","4","DDSTAGD","R","Dev-DMA address counter (on Dev)" -"G2_IF","f4","4","DDSTARD","R","Dev-DMA address counter (on root bus)" -"G2_IF","f8","4","DDLEND","R","Dev-DMA transfer counter" -,,,,, -"PVR_IF","00","4","PDSTAP","RW","PVR-DMA start address" -"PVR_IF","04","4","PDSTAR","RW","PVR-DMA system memory start address" -"PVR_IF","08","4","PDLEN","RW","PVR-DMA length" -"PVR_IF","0c","4","PDDIR","RW","PVR-DMA direction" -"PVR_IF","10","4","PDTSEL","RW","PVR-DMA trigger select" -"PVR_IF","14","4","PDEN","RW","PVR-DMA enable" -"PVR_IF","18","4","PDST","RW","PVR-DMA start" -,,,,, -"PVR_IF","80","4","PDAPRO","W","PVR-DMA address range" -,,,,, -"PVR_IF","f0","4","PDSTAPD","R","PVR-DMA address counter (on Ext)" -"PVR_IF","f4","4","PDSTARD","R","PVR-DMA address counter (on root bus)" -"PVR_IF","f8","4","PDLEND","R","PVR-DMA transfer counter" diff --git a/dreamcast2/regs/systembus/systembus_bits.csv b/dreamcast2/regs/systembus/systembus_bits.csv deleted file mode 100644 index 310596b..0000000 --- a/dreamcast2/regs/systembus/systembus_bits.csv +++ /dev/null @@ -1,67 +0,0 @@ -"register_name","enum_name","bits","bit_name","value","mask","description" -"C2DSTAT",,"31-0","texture_memory_start_address",,"0x13ffffe0", -"C2DLEN",,"23-0","transfer_length",,"0xffffe0", -"C2DST",,"0","start","1",, -,,,,,, -"ISTNRM",,"21","end_of_transferring_punch_through_list","1",, -"ISTNRM",,"20","end_of_dma_sort_dma","1",, -"ISTNRM",,"19","end_of_dma_ch2_dma","1",, -"ISTNRM",,"18","end_of_dma_dev_dma","1",, -"ISTNRM",,"17","end_of_dma_ext_dma2","1",, -"ISTNRM",,"16","end_of_dma_ext_dma1","1",, -"ISTNRM",,"15","end_of_dma_aica_dma","1",, -"ISTNRM",,"14","end_of_dma_gd_dma","1",, -"ISTNRM",,"13","maple_v_blank_over","1",, -"ISTNRM",,"12","end_of_dma_maple_dma","1",, -"ISTNRM",,"11","end_of_dma_pvr_dma","1",, -"ISTNRM",,"10","end_of_transferring_translucent_modifier_volume_list","1",, -"ISTNRM",,"9","end_of_transferring_translucent_list","1",, -"ISTNRM",,"8","end_of_transferring_opaque_modifier_volume_list","1",, -"ISTNRM",,"7","end_of_transferring_opaque_list","1",, -"ISTNRM",,"6","end_of_transferring_yuv","1",, -"ISTNRM",,"5","h_blank_in","1",, -"ISTNRM",,"4","v_blank_out","1",, -"ISTNRM",,"3","v_blank_in","1",, -"ISTNRM",,"2","end_of_render_tsp","1",, -"ISTNRM",,"1","end_of_render_isp","1",, -"ISTNRM",,"0","end_of_render_video","1",, -,,,,,, -"ISTERR",,"31","sh4__if_access_inhibited_area","1",, -"ISTERR",,"28","ddt__if_sort_dma_command_error","1",, -"ISTERR",,"27","g2__time_out_in_cpu_access","1",, -"ISTERR",,"26","g2__dev_dma_time_out","1",, -"ISTERR",,"25","g2__ext_dma2_time_out","1",, -"ISTERR",,"24","g2__ext_dma1_time_out","1",, -"ISTERR",,"23","g2__aica_dma_time_out","1",, -"ISTERR",,"22","g2__dev_dma_over_run","1",, -"ISTERR",,"21","g2__ext_dma2_over_run","1",, -"ISTERR",,"20","g2__ext_dma1_over_run","1",, -"ISTERR",,"19","g2__aica_dma_over_run","1",, -"ISTERR",,"18","g2__dev_dma_illegal_address_set","1",, -"ISTERR",,"17","g2__ext_dma2_illegal_address_set","1",, -"ISTERR",,"16","g2__ext_dma1_illegal_address_set","1",, -"ISTERR",,"15","g2__aica_dma_illegal_address_set","1",, -"ISTERR",,"14","g1__rom_flash_access_at_gd_dma","1",, -"ISTERR",,"13","g1__gd_dma_over_run","1",, -"ISTERR",,"12","g1__illegal_address_set","1",, -"ISTERR",,"11","maple__illegal_command","1",, -"ISTERR",,"10","maple__write_fifo_over_flow","1",, -"ISTERR",,"9","maple__dma_over_run","1",, -"ISTERR",,"8","maple__illegal_address_set","1",, -"ISTERR",,"7","pvrif__dma_over_run","1",, -"ISTERR",,"6","pvrif__illegal_address_set","1",, -"ISTERR",,"5","ta__fifo_overflow","1",, -"ISTERR",,"4","ta__illegal_parameter","1",, -"ISTERR",,"3","ta__object_list_pointer_overflow","1",, -"ISTERR",,"2","ta__isp_tsp_parameter_overflow","1",, -"ISTERR",,"1","render__hazard_processing_of_strip_buffer","1",, -"ISTERR",,"0","render__isp_out_of_cache","1",, -,,,,,, -"FFST",,"5","holly_cpu_if_block_internal_write_buffer",,, -"FFST",,"4","holly_g2_if_block_internal_write_buffer",,, -"FFST",,"0","aica_internal_write_buffer",,, -,,,,,, -"ISTEXT",,3,"external_device",1,, -"ISTEXT",,2,"modem",1,, -"ISTEXT",,1,"aica",1,, -"ISTEXT",,0,"gdrom",1,,