dreamcast2: initial

dreamcast2/Makefile

@@ -0,0 +1,30 @@
+%.csv: %.ods
+	libreoffice --headless --convert-to csv:"Text - txt - csv (StarCalc)":44,34,76,,,,true --outdir $(dir $@) $<
+
+
+# HOLLY
+
+holly/holly.hpp: regs/holly/holly.csv regs/holly.py
+	python regs/holly.py $< > $@
+
+holly/holly_bits.hpp: regs/holly/holly_bits.csv regs/holly_bits.py
+	python regs/holly_bits.py $< holly > $@
+
+holly/region_array_bits.hpp: regs/holly/region_array_bits.csv regs/holly_bits.py
+	python regs/holly_bits.py $< holly region_array > $@
+
+# SH7091
+
+sh7091/sh7091.hpp: regs/sh7091/sh7091.csv regs/sh7091.py
+	python regs/sh7091.py $< > $@
+
+sh7091/sh7091_bits.hpp: regs/sh7091/sh7091_bits.csv regs/holly_bits.py
+	python regs/holly_bits.py $< sh7091 > $@
+
+# SYSTEMBUS
+
+systembus/systembus.hpp: regs/systembus/systembus.csv regs/holly.py
+	python regs/holly.py $< > $@
+
+systembus/systembus_bits.hpp: regs/systembus/systembus_bits.csv regs/holly_bits.py
+	python regs/holly_bits.py $< system > $@

dreamcast2/holly/holly.hpp

@@ -0,0 +1,166 @@
+#pragma once
+
+#include "reg.hpp"
+
+struct holly_reg {
+  reg32 ID;                  /* Device ID */
+  reg32 REVISION;            /* Revision Number */
+  reg32 SOFTRESET;           /* CORE & TA software reset */
+  reg8  _pad0[8];
+  reg32 STARTRENDER;         /* Drawing start */
+  reg32 TEST_SELECT;         /* Test (writing this register is prohibited) */
+  reg8  _pad1[4];
+  reg32 PARAM_BASE;          /* Base address for ISP parameters */
+  reg8  _pad2[8];
+  reg32 REGION_BASE;         /* Base address for Region Array */
+  reg32 SPAN_SORT_CFG;       /* Span Sorter control */
+  reg8  _pad3[12];
+  reg32 VO_BORDER_COL;       /* Border area color */
+  reg32 FB_R_CTRL;           /* Frame buffer read control */
+  reg32 FB_W_CTRL;           /* Frame buffer write control */
+  reg32 FB_W_LINESTRIDE;     /* Frame buffer line stride */
+  reg32 FB_R_SOF1;           /* Read start address for field - 1/strip - 1 */
+  reg32 FB_R_SOF2;           /* Read start address for field - 2/strip - 2 */
+  reg8  _pad4[4];
+  reg32 FB_R_SIZE;           /* Frame buffer XY size */
+  reg32 FB_W_SOF1;           /* Write start address for field - 1/strip - 1 */
+  reg32 FB_W_SOF2;           /* Write start address for field - 2/strip - 2 */
+  reg32 FB_X_CLIP;           /* Pixel clip X coordinate */
+  reg32 FB_Y_CLIP;           /* Pixel clip Y coordinate */
+  reg8  _pad5[4];
+  reg32 FPU_SHAD_SCALE;      /* Intensity Volume mode */
+  reg32 FPU_CULL_VAL;        /* Comparison value for culling */
+  reg32 FPU_PARAM_CFG;       /* Parameter read control */
+  reg32 HALF_OFFSET;         /* Pixel sampling control */
+  reg32 FPU_PERP_VAL;        /* Comparison value for perpendicular polygons */
+  reg32 ISP_BACKGND_D;       /* Background surface depth */
+  reg32 ISP_BACKGND_T;       /* Background surface tag */
+  reg8  _pad6[8];
+  reg32 ISP_FEED_CFG;        /* Translucent polygon sort mode */
+  reg8  _pad7[4];
+  reg32 SDRAM_REFRESH;       /* Texture memory refresh counter */
+  reg32 SDRAM_ARB_CFG;       /* Texture memory arbiter control */
+  reg32 SDRAM_CFG;           /* Texture memory control */
+  reg8  _pad8[4];
+  reg32 FOG_COL_RAM;         /* Color for Look Up table Fog */
+  reg32 FOG_COL_VERT;        /* Color for vertex Fog */
+  reg32 FOG_DENSITY;         /* Fog scale value */
+  reg32 FOG_CLAMP_MAX;       /* Color clamping maximum value */
+  reg32 FOG_CLAMP_MIN;       /* Color clamping minimum value */
+  reg32 SPG_TRIGGER_POS;     /* External trigger signal HV counter value */
+  reg32 SPG_HBLANK_INT;      /* H-blank interrupt control */
+  reg32 SPG_VBLANK_INT;      /* V-blank interrupt control */
+  reg32 SPG_CONTROL;         /* Sync pulse generator control */
+  reg32 SPG_HBLANK;          /* H-blank control */
+  reg32 SPG_LOAD;            /* HV counter load value */
+  reg32 SPG_VBLANK;          /* V-blank control */
+  reg32 SPG_WIDTH;           /* Sync width control */
+  reg32 TEXT_CONTROL;        /* Texturing control */
+  reg32 VO_CONTROL;          /* Video output control */
+  reg32 VO_STARTX;           /* Video output start X position */
+  reg32 VO_STARTY;           /* Video output start Y position */
+  reg32 SCALER_CTL;          /* X & Y scaler control */
+  reg8  _pad9[16];
+  reg32 PAL_RAM_CTRL;        /* Palette RAM control */
+  reg32 SPG_STATUS;          /* Sync pulse generator status */
+  reg32 FB_BURSTCTRL;        /* Frame buffer burst control */
+  reg32 FB_C_SOF;            /* Current frame buffer start address */
+  reg32 Y_COEFF;             /* Y scaling coefficent */
+  reg32 PT_ALPHA_REF;        /* Alpha value for Punch Through polygon comparison */
+  reg8  _pad10[4];
+  reg32 TA_OL_BASE;          /* Object List write start address */
+  reg32 TA_ISP_BASE;         /* ISP/TSP Parameter write start address */
+  reg32 TA_OL_LIMIT;         /* Object List write limit address */
+  reg32 TA_ISP_LIMIT;        /* ISP/TSP Parameter limit address */
+  reg32 TA_NEXT_OPB;         /* Start address for the Object Pointer Block */
+  reg32 TA_ITP_CURRENT;      /* Starting address where the next ISP/TSP Parameters are stored */
+  reg32 TA_GLOB_TILE_CLIP;   /* Global Tile Clip control */
+  reg32 TA_ALLOC_CTRL;       /* Object list control */
+  reg32 TA_LIST_INIT;        /* TA initialization */
+  reg32 TA_YUV_TEX_BASE;     /* YUV422 texture write start address */
+  reg32 TA_YUV_TEX_CTRL;     /* YUV converter control */
+  reg32 TA_YUV_TEX_CNT;      /* YUV converter macro block counter value */
+  reg8  _pad11[12];
+  reg32 TA_LIST_CONT;        /* TA continuation processing */
+  reg32 TA_NEXT_OPB_INIT;    /* Additional OPB starting address */
+  reg8  _pad12[152];
+  reg32 FOG_TABLE[128];      /* Look-up table fog data */
+  reg8  _pad13[512];
+  reg32 TA_OL_POINTERS[600]; /* TA Object List Pointer data */
+  reg8  _pad14[160];
+  reg32 PALETTE_RAM[1024];   /* Palette RAM */
+};
+
+static_assert((offsetof (struct holly_reg, ID)) == 0x0);
+static_assert((offsetof (struct holly_reg, REVISION)) == 0x4);
+static_assert((offsetof (struct holly_reg, SOFTRESET)) == 0x8);
+static_assert((offsetof (struct holly_reg, STARTRENDER)) == 0x14);
+static_assert((offsetof (struct holly_reg, TEST_SELECT)) == 0x18);
+static_assert((offsetof (struct holly_reg, PARAM_BASE)) == 0x20);
+static_assert((offsetof (struct holly_reg, REGION_BASE)) == 0x2c);
+static_assert((offsetof (struct holly_reg, SPAN_SORT_CFG)) == 0x30);
+static_assert((offsetof (struct holly_reg, VO_BORDER_COL)) == 0x40);
+static_assert((offsetof (struct holly_reg, FB_R_CTRL)) == 0x44);
+static_assert((offsetof (struct holly_reg, FB_W_CTRL)) == 0x48);
+static_assert((offsetof (struct holly_reg, FB_W_LINESTRIDE)) == 0x4c);
+static_assert((offsetof (struct holly_reg, FB_R_SOF1)) == 0x50);
+static_assert((offsetof (struct holly_reg, FB_R_SOF2)) == 0x54);
+static_assert((offsetof (struct holly_reg, FB_R_SIZE)) == 0x5c);
+static_assert((offsetof (struct holly_reg, FB_W_SOF1)) == 0x60);
+static_assert((offsetof (struct holly_reg, FB_W_SOF2)) == 0x64);
+static_assert((offsetof (struct holly_reg, FB_X_CLIP)) == 0x68);
+static_assert((offsetof (struct holly_reg, FB_Y_CLIP)) == 0x6c);
+static_assert((offsetof (struct holly_reg, FPU_SHAD_SCALE)) == 0x74);
+static_assert((offsetof (struct holly_reg, FPU_CULL_VAL)) == 0x78);
+static_assert((offsetof (struct holly_reg, FPU_PARAM_CFG)) == 0x7c);
+static_assert((offsetof (struct holly_reg, HALF_OFFSET)) == 0x80);
+static_assert((offsetof (struct holly_reg, FPU_PERP_VAL)) == 0x84);
+static_assert((offsetof (struct holly_reg, ISP_BACKGND_D)) == 0x88);
+static_assert((offsetof (struct holly_reg, ISP_BACKGND_T)) == 0x8c);
+static_assert((offsetof (struct holly_reg, ISP_FEED_CFG)) == 0x98);
+static_assert((offsetof (struct holly_reg, SDRAM_REFRESH)) == 0xa0);
+static_assert((offsetof (struct holly_reg, SDRAM_ARB_CFG)) == 0xa4);
+static_assert((offsetof (struct holly_reg, SDRAM_CFG)) == 0xa8);
+static_assert((offsetof (struct holly_reg, FOG_COL_RAM)) == 0xb0);
+static_assert((offsetof (struct holly_reg, FOG_COL_VERT)) == 0xb4);
+static_assert((offsetof (struct holly_reg, FOG_DENSITY)) == 0xb8);
+static_assert((offsetof (struct holly_reg, FOG_CLAMP_MAX)) == 0xbc);
+static_assert((offsetof (struct holly_reg, FOG_CLAMP_MIN)) == 0xc0);
+static_assert((offsetof (struct holly_reg, SPG_TRIGGER_POS)) == 0xc4);
+static_assert((offsetof (struct holly_reg, SPG_HBLANK_INT)) == 0xc8);
+static_assert((offsetof (struct holly_reg, SPG_VBLANK_INT)) == 0xcc);
+static_assert((offsetof (struct holly_reg, SPG_CONTROL)) == 0xd0);
+static_assert((offsetof (struct holly_reg, SPG_HBLANK)) == 0xd4);
+static_assert((offsetof (struct holly_reg, SPG_LOAD)) == 0xd8);
+static_assert((offsetof (struct holly_reg, SPG_VBLANK)) == 0xdc);
+static_assert((offsetof (struct holly_reg, SPG_WIDTH)) == 0xe0);
+static_assert((offsetof (struct holly_reg, TEXT_CONTROL)) == 0xe4);
+static_assert((offsetof (struct holly_reg, VO_CONTROL)) == 0xe8);
+static_assert((offsetof (struct holly_reg, VO_STARTX)) == 0xec);
+static_assert((offsetof (struct holly_reg, VO_STARTY)) == 0xf0);
+static_assert((offsetof (struct holly_reg, SCALER_CTL)) == 0xf4);
+static_assert((offsetof (struct holly_reg, PAL_RAM_CTRL)) == 0x108);
+static_assert((offsetof (struct holly_reg, SPG_STATUS)) == 0x10c);
+static_assert((offsetof (struct holly_reg, FB_BURSTCTRL)) == 0x110);
+static_assert((offsetof (struct holly_reg, FB_C_SOF)) == 0x114);
+static_assert((offsetof (struct holly_reg, Y_COEFF)) == 0x118);
+static_assert((offsetof (struct holly_reg, PT_ALPHA_REF)) == 0x11c);
+static_assert((offsetof (struct holly_reg, TA_OL_BASE)) == 0x124);
+static_assert((offsetof (struct holly_reg, TA_ISP_BASE)) == 0x128);
+static_assert((offsetof (struct holly_reg, TA_OL_LIMIT)) == 0x12c);
+static_assert((offsetof (struct holly_reg, TA_ISP_LIMIT)) == 0x130);
+static_assert((offsetof (struct holly_reg, TA_NEXT_OPB)) == 0x134);
+static_assert((offsetof (struct holly_reg, TA_ITP_CURRENT)) == 0x138);
+static_assert((offsetof (struct holly_reg, TA_GLOB_TILE_CLIP)) == 0x13c);
+static_assert((offsetof (struct holly_reg, TA_ALLOC_CTRL)) == 0x140);
+static_assert((offsetof (struct holly_reg, TA_LIST_INIT)) == 0x144);
+static_assert((offsetof (struct holly_reg, TA_YUV_TEX_BASE)) == 0x148);
+static_assert((offsetof (struct holly_reg, TA_YUV_TEX_CTRL)) == 0x14c);
+static_assert((offsetof (struct holly_reg, TA_YUV_TEX_CNT)) == 0x150);
+static_assert((offsetof (struct holly_reg, TA_LIST_CONT)) == 0x160);
+static_assert((offsetof (struct holly_reg, TA_NEXT_OPB_INIT)) == 0x164);
+static_assert((offsetof (struct holly_reg, FOG_TABLE)) == 0x200);
+static_assert((offsetof (struct holly_reg, TA_OL_POINTERS)) == 0x600);
+static_assert((offsetof (struct holly_reg, PALETTE_RAM)) == 0x1000);
+
+extern struct holly_reg holly __asm("holly");

dreamcast2/holly/holly_bits.hpp

@@ -0,0 +1,635 @@
+#pragma once
+
+#include <cstdint>
+
+namespace holly {
+  namespace id {
+    constexpr uint32_t device_id(uint32_t reg) { return (reg >> 16) & 0xffff; }
+    constexpr uint32_t vendor_id(uint32_t reg) { return (reg >> 0) & 0xffff; }
+  }
+
+  namespace revision {
+    constexpr uint32_t chip_revision(uint32_t reg) { return (reg >> 0) & 0xffff; }
+  }
+
+  namespace softreset {
+    constexpr uint32_t sdram_if_soft_reset = 1 << 2;
+    constexpr uint32_t pipeline_soft_reset = 1 << 1;
+    constexpr uint32_t ta_soft_reset = 1 << 0;
+  }
+
+  namespace startrender {
+    constexpr uint32_t start_render = 1 << 0;
+  }
+
+  namespace test_select {
+    constexpr uint32_t diagdb_data(uint32_t reg) { return (reg >> 5) & 0x1f; }
+    constexpr uint32_t diagda_data(uint32_t reg) { return (reg >> 0) & 0x1f; }
+  }
+
+  namespace param_base {
+    constexpr uint32_t base_address(uint32_t num) { return (num & 0xf00000) << 0; }
+  }
+
+  namespace region_base {
+    constexpr uint32_t base_address(uint32_t num) { return (num & 0xfffffc) << 0; }
+  }
+
+  namespace span_sort_cfg {
+    constexpr uint32_t cache_bypass = 1 << 16;
+    constexpr uint32_t offset_sort_enable = 1 << 8;
+    constexpr uint32_t span_sort_enable = 1 << 0;
+  }
+
+  namespace vo_border_col {
+    constexpr uint32_t chroma(uint32_t num) { return (num & 0x1) << 24; }
+    constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+    constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace fb_r_ctrl {
+    namespace vclk_div {
+      constexpr uint32_t pclk_vclk_2 = 0 << 23;
+      constexpr uint32_t pclk_vclk_1 = 1 << 23;
+
+      constexpr uint32_t bit_mask = 0x1 << 23;
+    }
+
+    constexpr uint32_t fb_strip_buf_en = 1 << 22;
+    constexpr uint32_t fb_stripsize(uint32_t num) { return (num & 0x3e) << 16; }
+    constexpr uint32_t fb_chroma_threshold(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t fb_concat(uint32_t num) { return (num & 0x3) << 4; }
+
+    namespace fb_depth {
+      constexpr uint32_t xrgb0555 = 0 << 2;
+      constexpr uint32_t rgb565 = 1 << 2;
+      constexpr uint32_t rgb888 = 2 << 2;
+      constexpr uint32_t xrgb0888 = 3 << 2;
+
+      constexpr uint32_t bit_mask = 0x3 << 2;
+    }
+
+    constexpr uint32_t fb_line_double = 1 << 1;
+    constexpr uint32_t fb_enable = 1 << 0;
+  }
+
+  namespace fb_w_ctrl {
+    constexpr uint32_t fb_alpha_threshold(uint32_t num) { return (num & 0xff) << 16; }
+    constexpr uint32_t fb_kval(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t fb_dither = 1 << 3;
+
+    namespace fb_packmode {
+      constexpr uint32_t krgb0555 = 0 << 0;
+      constexpr uint32_t rgb565 = 1 << 0;
+      constexpr uint32_t argb4444 = 2 << 0;
+      constexpr uint32_t argb1555 = 3 << 0;
+      constexpr uint32_t rgb888 = 4 << 0;
+      constexpr uint32_t krgb0888 = 5 << 0;
+      constexpr uint32_t argb8888 = 6 << 0;
+
+      constexpr uint32_t bit_mask = 0x7 << 0;
+    }
+  }
+
+  namespace fb_w_linestride {
+    constexpr uint32_t fb_line_stride(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace fb_r_sof1 {
+    constexpr uint32_t frame_buffer_read_address_frame_1(uint32_t num) { return (num & 0xfffffc) << 0; }
+  }
+
+  namespace fb_r_sof2 {
+    constexpr uint32_t frame_buffer_read_address_frame_2(uint32_t num) { return (num & 0xfffffc) << 0; }
+  }
+
+  namespace fb_r_size {
+    constexpr uint32_t fb_modulus(uint32_t num) { return (num & 0x3ff) << 20; }
+    constexpr uint32_t fb_y_size(uint32_t num) { return (num & 0x3ff) << 10; }
+    constexpr uint32_t fb_x_size(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace fb_w_sof1 {
+    constexpr uint32_t frame_buffer_write_address_frame_1(uint32_t num) { return (num & 0x1fffffc) << 0; }
+  }
+
+  namespace fb_w_sof2 {
+    constexpr uint32_t frame_buffer_write_address_frame_2(uint32_t num) { return (num & 0x1fffffc) << 0; }
+  }
+
+  namespace fb_x_clip {
+    constexpr uint32_t fb_x_clip_max(uint32_t num) { return (num & 0x7ff) << 16; }
+    constexpr uint32_t fb_x_clip_min(uint32_t num) { return (num & 0x7ff) << 0; }
+  }
+
+  namespace fb_y_clip {
+    constexpr uint32_t fb_y_clip_max(uint32_t num) { return (num & 0x3ff) << 16; }
+    constexpr uint32_t fb_y_clip_min(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace fpu_shad_scale {
+    namespace simple_shadow_enable {
+      constexpr uint32_t parameter_selection_volume_mode = 0 << 8;
+      constexpr uint32_t intensity_volume_mode = 1 << 8;
+
+      constexpr uint32_t bit_mask = 0x1 << 8;
+    }
+
+    constexpr uint32_t scale_factor_for_shadows(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace fpu_cull_val {
+    inline uint32_t culling_comparison_value(float num) { return _i(__builtin_fabsf(num));; }
+  }
+
+  namespace fpu_param_cfg {
+    namespace region_header_type {
+      constexpr uint32_t type_1 = 0 << 21;
+      constexpr uint32_t type_2 = 1 << 21;
+
+      constexpr uint32_t bit_mask = 0x1 << 21;
+    }
+
+    constexpr uint32_t tsp_parameter_burst_threshold(uint32_t num) { return (num & 0x3f) << 14; }
+    constexpr uint32_t isp_parameter_burst_threshold(uint32_t num) { return (num & 0x3f) << 8; }
+    constexpr uint32_t pointer_burst_size(uint32_t num) { return (num & 0xf) << 4; }
+    constexpr uint32_t pointer_first_burst_size(uint32_t num) { return (num & 0xf) << 0; }
+  }
+
+  namespace half_offset {
+    namespace tsp_texel_sampling_position {
+      constexpr uint32_t top_left = 1 << 2;
+      constexpr uint32_t center = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace tsp_pixel_sampling_position {
+      constexpr uint32_t top_left = 1 << 1;
+      constexpr uint32_t center = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace fpu_pixel_sampling_position {
+      constexpr uint32_t top_left = 1 << 0;
+      constexpr uint32_t center = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace fpu_perp_val {
+    inline uint32_t perpendicular_triangle_compare(float num) { return _i(__builtin_fabsf(num));; }
+  }
+
+  namespace isp_backgnd_d {
+    inline uint32_t background_plane_depth(float num) { return _i(num) & 0xfffffff0; }
+  }
+
+  namespace isp_backgnd_t {
+    constexpr uint32_t cache_bypass = 1 << 28;
+    constexpr uint32_t shadow = 1 << 27;
+    constexpr uint32_t skip(uint32_t num) { return (num & 0x7) << 24; }
+    constexpr uint32_t tag_address(uint32_t num) { return (num & 0x1fffff) << 3; }
+    constexpr uint32_t tag_offset(uint32_t num) { return (num & 0x7) << 0; }
+  }
+
+  namespace isp_feed_cfg {
+    constexpr uint32_t cache_size_for_translucency(uint32_t num) { return (num & 0x3ff) << 14; }
+    constexpr uint32_t punch_through_chunk_size(uint32_t num) { return (num & 0x3ff) << 4; }
+    constexpr uint32_t discard_mode = 1 << 3;
+    constexpr uint32_t pre_sort_mode = 1 << 0;
+  }
+
+  namespace sdram_refresh {
+    constexpr uint32_t refresh_counter_value(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace sdram_arb_cfg {
+    namespace override_value {
+      constexpr uint32_t priority_only = 0x0 << 18;
+      constexpr uint32_t rendered_data = 0x1 << 18;
+      constexpr uint32_t texture_vq_index = 0x2 << 18;
+      constexpr uint32_t texture_normal_data_and_vq_codebook = 0x3 << 18;
+      constexpr uint32_t tile_accelerator_isp_tsp_data = 0x4 << 18;
+      constexpr uint32_t tile_accelerator_pointers = 0x5 << 18;
+      constexpr uint32_t sh4 = 0x6 << 18;
+      constexpr uint32_t tsp_parameters = 0x7 << 18;
+      constexpr uint32_t tsp_region_data = 0x8 << 18;
+      constexpr uint32_t isp_pointer_data = 0x9 << 18;
+      constexpr uint32_t isp_parameters = 0xa << 18;
+      constexpr uint32_t crt_controller = 0xb << 18;
+
+      constexpr uint32_t bit_mask = 0xf << 18;
+    }
+
+    namespace arbiter_priority_control {
+      constexpr uint32_t priority_arbitration_only = 0x0 << 16;
+      constexpr uint32_t override_value_field = 0x1 << 16;
+      constexpr uint32_t round_robin_counter = 0x2 << 16;
+
+      constexpr uint32_t bit_mask = 0x3 << 16;
+    }
+
+    constexpr uint32_t arbiter_crt_page_break_latency_count_value(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t arbiter_page_break_latency_count_value(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace sdram_cfg {
+    constexpr uint32_t read_command_to_returned_data_delay(uint32_t num) { return (num & 0x7) << 26; }
+    constexpr uint32_t cas_latency_value(uint32_t num) { return (num & 0x7) << 23; }
+    constexpr uint32_t activate_to_activate_period(uint32_t num) { return (num & 0x3) << 21; }
+    constexpr uint32_t read_to_write_period(uint32_t num) { return (num & 0x7) << 18; }
+    constexpr uint32_t refresh_to_activate_period(uint32_t num) { return (num & 0xf) << 14; }
+    constexpr uint32_t pre_charge_to_activate_period(uint32_t num) { return (num & 0x3) << 10; }
+    constexpr uint32_t activate_to_pre_charge_period(uint32_t num) { return (num & 0xf) << 6; }
+    constexpr uint32_t activate_to_read_write_command_period(uint32_t num) { return (num & 0x3) << 4; }
+    constexpr uint32_t write_to_pre_charge_period(uint32_t num) { return (num & 0x3) << 2; }
+    constexpr uint32_t read_to_pre_charge_period(uint32_t num) { return (num & 0x3) << 0; }
+  }
+
+  namespace fog_col_ram {
+    constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+    constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace fog_col_vert {
+    constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+    constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace fog_density {
+    constexpr uint32_t fog_scale_mantissa(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t fog_scale_exponent(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace fog_clamp_max {
+    constexpr uint32_t alpha(uint32_t num) { return (num & 0xff) << 24; }
+    constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+    constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace fog_clamp_min {
+    constexpr uint32_t alpha(uint32_t num) { return (num & 0xff) << 24; }
+    constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+    constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace spg_trigger_pos {
+    constexpr uint32_t trigger_v_count(uint32_t reg) { return (reg >> 16) & 0x3ff; }
+    constexpr uint32_t trigger_h_count(uint32_t reg) { return (reg >> 0) & 0x3ff; }
+  }
+
+  namespace spg_hblank_int {
+    constexpr uint32_t hblank_in_interrupt(uint32_t reg) { return (reg >> 16) & 0x3ff; }
+
+    namespace hblank_int_mode {
+      constexpr uint32_t output_equal_line_comp_val = 0x0 << 12;
+      constexpr uint32_t output_every_line_comp_val = 0x1 << 12;
+      constexpr uint32_t output_every_line = 0x2 << 12;
+
+      constexpr uint32_t bit_mask = 0x3 << 12;
+    }
+
+    constexpr uint32_t line_comp_val(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace spg_vblank_int {
+    constexpr uint32_t vblank_out_interrupt_line_number(uint32_t num) { return (num & 0x3ff) << 16; }
+    constexpr uint32_t vblank_in_interrupt_line_number(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace spg_control {
+    namespace csync_on_h {
+      constexpr uint32_t hsync = 0 << 9;
+      constexpr uint32_t csync = 1 << 9;
+
+      constexpr uint32_t bit_mask = 0x1 << 9;
+    }
+
+    namespace sync_direction {
+      constexpr uint32_t input = 0 << 8;
+      constexpr uint32_t output = 1 << 8;
+
+      constexpr uint32_t bit_mask = 0x1 << 8;
+    }
+
+    constexpr uint32_t pal = 1 << 7;
+    constexpr uint32_t ntsc = 1 << 6;
+    constexpr uint32_t force_field2 = 1 << 5;
+    constexpr uint32_t interlace = 1 << 4;
+    constexpr uint32_t spg_lock = 1 << 3;
+
+    namespace mcsync_pol {
+      constexpr uint32_t active_low = 0 << 2;
+      constexpr uint32_t active_high = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace mvsync_pol {
+      constexpr uint32_t active_low = 0 << 1;
+      constexpr uint32_t active_high = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace mhsync_pol {
+      constexpr uint32_t active_low = 0 << 0;
+      constexpr uint32_t active_high = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace spg_hblank {
+    constexpr uint32_t hbend(uint32_t num) { return (num & 0x3ff) << 16; }
+    constexpr uint32_t hbstart(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace spg_load {
+    constexpr uint32_t vcount(uint32_t num) { return (num & 0x3ff) << 16; }
+    constexpr uint32_t hcount(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace spg_vblank {
+    constexpr uint32_t vbend(uint32_t num) { return (num & 0x3ff) << 16; }
+    constexpr uint32_t vbstart(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace spg_width {
+    constexpr uint32_t eqwidth(uint32_t num) { return (num & 0x3ff) << 22; }
+    constexpr uint32_t bpwidth(uint32_t num) { return (num & 0x3ff) << 12; }
+    constexpr uint32_t vswidth(uint32_t num) { return (num & 0xf) << 8; }
+    constexpr uint32_t hswidth(uint32_t num) { return (num & 0x7f) << 0; }
+  }
+
+  namespace text_control {
+    namespace code_book_endian {
+      constexpr uint32_t little_endian = 0 << 17;
+      constexpr uint32_t big_endian = 1 << 17;
+
+      constexpr uint32_t bit_mask = 0x1 << 17;
+    }
+
+    namespace index_endian {
+      constexpr uint32_t little_endian = 0 << 16;
+      constexpr uint32_t big_endian = 1 << 16;
+
+      constexpr uint32_t bit_mask = 0x1 << 16;
+    }
+
+    constexpr uint32_t bank_bit(uint32_t num) { return (num & 0x1f) << 8; }
+    constexpr uint32_t stride(uint32_t num) { return (num & 0x1f) << 0; }
+  }
+
+  namespace vo_control {
+    constexpr uint32_t pclk_delay_reset = 1 << 21;
+    constexpr uint32_t pclk_delay(uint32_t num) { return (num & 0x1f) << 16; }
+    constexpr uint32_t pixel_double = 1 << 8;
+
+    namespace field_mode {
+      constexpr uint32_t use_field_flag_from_spg = 0x0 << 4;
+      constexpr uint32_t use_inverse_of_field_flag_from_spg = 0x1 << 4;
+      constexpr uint32_t field_1_fixed = 0x2 << 4;
+      constexpr uint32_t field_2_fixed = 0x3 << 4;
+      constexpr uint32_t field_1_when_the_active_edges_of_hsync_and_vsync_match = 0x4 << 4;
+      constexpr uint32_t field_2_when_the_active_edges_of_hsync_and_vsync_match = 0x5 << 4;
+      constexpr uint32_t field_1_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge = 0x6 << 4;
+      constexpr uint32_t field_2_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge = 0x7 << 4;
+      constexpr uint32_t inverted_at_the_active_edge_of_vsync = 0x8 << 4;
+
+      constexpr uint32_t bit_mask = 0xf << 4;
+    }
+
+    constexpr uint32_t blank_video = 1 << 3;
+
+    namespace blank_pol {
+      constexpr uint32_t active_low = 0 << 2;
+      constexpr uint32_t active_high = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace vsync_pol {
+      constexpr uint32_t active_low = 0 << 1;
+      constexpr uint32_t active_high = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace hsync_pol {
+      constexpr uint32_t active_low = 0 << 0;
+      constexpr uint32_t active_high = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace vo_startx {
+    constexpr uint32_t horizontal_start_position(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace vo_starty {
+    constexpr uint32_t vertical_start_position_on_field_2(uint32_t num) { return (num & 0x3ff) << 16; }
+    constexpr uint32_t vertical_start_position_on_field_1(uint32_t num) { return (num & 0x3ff) << 0; }
+  }
+
+  namespace scaler_ctl {
+    namespace field_select {
+      constexpr uint32_t field_1 = 0 << 18;
+      constexpr uint32_t field_2 = 1 << 18;
+
+      constexpr uint32_t bit_mask = 0x1 << 18;
+    }
+
+    constexpr uint32_t interlace = 1 << 17;
+    constexpr uint32_t horizontal_scaling_enable = 1 << 16;
+    constexpr uint32_t vertical_scale_factor(uint32_t num) { return (num & 0xffff) << 0; }
+  }
+
+  namespace pal_ram_ctrl {
+    namespace pixel_format {
+      constexpr uint32_t argb1555 = 0 << 0;
+      constexpr uint32_t rgb565 = 1 << 0;
+      constexpr uint32_t argb4444 = 2 << 0;
+      constexpr uint32_t argb8888 = 3 << 0;
+
+      constexpr uint32_t bit_mask = 0x3 << 0;
+    }
+  }
+
+  namespace spg_status {
+    constexpr uint32_t vsync(uint32_t reg) { return (reg >> 13) & 0x1; }
+    constexpr uint32_t hsync(uint32_t reg) { return (reg >> 12) & 0x1; }
+    constexpr uint32_t blank(uint32_t reg) { return (reg >> 11) & 0x1; }
+    constexpr uint32_t fieldnum(uint32_t reg) { return (reg >> 10) & 0x1; }
+    constexpr uint32_t scanline(uint32_t reg) { return (reg >> 0) & 0x3ff; }
+  }
+
+  namespace fb_burstctrl {
+    constexpr uint32_t wr_burst(uint32_t num) { return (num & 0xf) << 16; }
+    constexpr uint32_t vid_lat(uint32_t num) { return (num & 0x7f) << 8; }
+    constexpr uint32_t vid_burst(uint32_t num) { return (num & 0x3f) << 0; }
+  }
+
+  namespace fb_c_sof {
+    constexpr uint32_t frame_buffer_current_read_address(uint32_t reg) { return (reg >> 0) & 0xffffff; }
+  }
+
+  namespace y_coeff {
+    constexpr uint32_t coefficient_1(uint32_t num) { return (num & 0xff) << 8; }
+    constexpr uint32_t coefficient_0_2(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace pt_alpha_ref {
+    constexpr uint32_t alpha_reference_for_punch_through(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace fog_table {
+    constexpr uint32_t fog_table_data(uint32_t num) { return (num & 0xffff) << 0; }
+  }
+
+  namespace palette_ram {
+    constexpr uint32_t palette_data(uint32_t num) { return (num & 0xffffffff) << 0; }
+  }
+
+  namespace ta_ol_base {
+    constexpr uint32_t base_address(uint32_t num) { return (num & 0xffffe0) << 0; }
+  }
+
+  namespace ta_isp_base {
+    constexpr uint32_t base_address(uint32_t num) { return (num & 0xfffffc) << 0; }
+  }
+
+  namespace ta_ol_limit {
+    constexpr uint32_t limit_address(uint32_t num) { return (num & 0xffffe0) << 0; }
+  }
+
+  namespace ta_isp_limit {
+    constexpr uint32_t limit_address(uint32_t num) { return (num & 0xfffffc) << 0; }
+  }
+
+  namespace ta_next_opb {
+    constexpr uint32_t address(uint32_t num) { return (num & 0xffffe0) << 0; }
+  }
+
+  namespace ta_itp_current {
+    constexpr uint32_t address(uint32_t reg) { return (reg >> 0) & 0xffffff; }
+  }
+
+  namespace ta_glob_tile_clip {
+    constexpr uint32_t tile_y_num(uint32_t num) { return (num & 0xf) << 16; }
+    constexpr uint32_t tile_x_num(uint32_t num) { return (num & 0x1f) << 0; }
+  }
+
+  namespace ta_alloc_ctrl {
+    namespace opb_mode {
+      constexpr uint32_t increasing_addresses = 0 << 20;
+      constexpr uint32_t decreasing_addresses = 1 << 20;
+
+      constexpr uint32_t bit_mask = 0x1 << 20;
+    }
+
+    namespace pt_opb {
+      constexpr uint32_t no_list = 0 << 16;
+      constexpr uint32_t _8x4byte = 1 << 16;
+      constexpr uint32_t _16x4byte = 2 << 16;
+      constexpr uint32_t _32x4byte = 3 << 16;
+
+      constexpr uint32_t bit_mask = 0x3 << 16;
+    }
+
+    namespace tm_opb {
+      constexpr uint32_t no_list = 0 << 12;
+      constexpr uint32_t _8x4byte = 1 << 12;
+      constexpr uint32_t _16x4byte = 2 << 12;
+      constexpr uint32_t _32x4byte = 3 << 12;
+
+      constexpr uint32_t bit_mask = 0x3 << 12;
+    }
+
+    namespace t_opb {
+      constexpr uint32_t no_list = 0 << 8;
+      constexpr uint32_t _8x4byte = 1 << 8;
+      constexpr uint32_t _16x4byte = 2 << 8;
+      constexpr uint32_t _32x4byte = 3 << 8;
+
+      constexpr uint32_t bit_mask = 0x3 << 8;
+    }
+
+    namespace om_opb {
+      constexpr uint32_t no_list = 0 << 4;
+      constexpr uint32_t _8x4byte = 1 << 4;
+      constexpr uint32_t _16x4byte = 2 << 4;
+      constexpr uint32_t _32x4byte = 3 << 4;
+
+      constexpr uint32_t bit_mask = 0x3 << 4;
+    }
+
+    namespace o_opb {
+      constexpr uint32_t no_list = 0 << 0;
+      constexpr uint32_t _8x4byte = 1 << 0;
+      constexpr uint32_t _16x4byte = 2 << 0;
+      constexpr uint32_t _32x4byte = 3 << 0;
+
+      constexpr uint32_t bit_mask = 0x3 << 0;
+    }
+  }
+
+  namespace ta_list_init {
+    constexpr uint32_t list_init = 1 << 31;
+  }
+
+  namespace ta_yuv_tex_base {
+    constexpr uint32_t base_address(uint32_t num) { return (num & 0xfffff8) << 0; }
+  }
+
+  namespace ta_yuv_tex_ctrl {
+    namespace yuv_form {
+      constexpr uint32_t yuv420 = 0 << 24;
+      constexpr uint32_t yuv422 = 1 << 24;
+
+      constexpr uint32_t bit_mask = 0x1 << 24;
+    }
+
+    namespace yuv_tex {
+      constexpr uint32_t one_texture = 0 << 16;
+      constexpr uint32_t multiple_textures = 1 << 16;
+
+      constexpr uint32_t bit_mask = 0x1 << 16;
+    }
+
+    constexpr uint32_t yuv_v_size(uint32_t num) { return (num & 0x3f) << 8; }
+    constexpr uint32_t yuv_u_size(uint32_t num) { return (num & 0x3f) << 0; }
+  }
+
+  namespace ta_yuv_tex_cnt {
+    constexpr uint32_t yuv_num(uint32_t reg) { return (reg >> 0) & 0x1fff; }
+  }
+
+  namespace ta_list_cont {
+    constexpr uint32_t list_cont = 1 << 31;
+  }
+
+  namespace ta_next_opb_init {
+    constexpr uint32_t address(uint32_t num) { return (num & 0xffffe0) << 0; }
+  }
+
+  namespace ta_ol_pointers {
+    constexpr uint32_t entry(uint32_t reg) { return (reg >> 31) & 0x1; }
+    constexpr uint32_t sprite(uint32_t reg) { return (reg >> 30) & 0x1; }
+    constexpr uint32_t triangle(uint32_t reg) { return (reg >> 29) & 0x1; }
+    constexpr uint32_t number_of_triangles_quads(uint32_t reg) { return (reg >> 25) & 0xf; }
+    constexpr uint32_t shadow(uint32_t reg) { return (reg >> 24) & 0x1; }
+    constexpr uint32_t pointer_address(uint32_t reg) { return (reg >> 2) & 0x3fffff; }
+    constexpr uint32_t skip(uint32_t reg) { return (reg >> 0) & 0x3; }
+  }
+
+}

dreamcast2/holly/region_array.cpp

@@ -0,0 +1,71 @@
+#include "holly/region_array.hpp"
+#include "holly/region_array_bits.hpp"
+
+#incllude "sh7091/store_queue_transfer.hpp"
+
+namespace holly::region_array {
+
+  void transfer_region_array(const int tile_width,
+                             const int tile_height,
+                             const list_block_size& list_block_size,
+                             const uint32_t region_array_start,
+                             const uint32_t object_list_start);
+  {
+    const uint32_t ol_base = object_list_start;
+    const uint32_t num_tiles = width * height;
+    region_array_entry region_array[num_tiles];
+
+    int ix = 0;
+
+    for (int y = 0; y < height; y++) {
+      for (int x = 0; x < width; x++) {
+        region_array[ix].tile = tile::y_position(y)
+                              | tile::x_position(x);
+
+        if (y == (height - 1) && x == (width - 1))
+          region_array[ix].tile |= tile::last_region;
+
+        region_array[ix].list_pointer.opaque                      = (opb_size.opaque               == 0) ? REGION_ARRAY__LIST_POINTER__EMPTY :
+                                                                    (ol_base + (opb_size.opaque * ix)
+                                                                     );
+
+        region_array[ix].list_pointer.opaque_modifier_volume      = (opb_size.opaque_modifier      == 0) ? REGION_ARRAY__LIST_POINTER__EMPTY :
+                                                                    (ol_base + num_tiles * ( opb_size.opaque
+                                                                                           )
+                                                                             + (opb_size.opaque_modifier_volume * ix)
+                                                                     );
+
+        region_array[ix].list_pointer.translucent                 = (opb_size.translucent          == 0) ? REGION_ARRAY__LIST_POINTER__EMPTY :
+                                                                    (ol_base + num_tiles * ( opb_size.opaque
+                                                                                           + opb_size.opaque_modifier_volume
+                                                                                           )
+                                                                             + (opb_size.translucent * ix)
+                                                                     );
+        region_array[ix].list_pointer.translucent_modifier_volume = (opb_size.translucent_modifier == 0) ? REGION_ARRAY__LIST_POINTER__EMPTY :
+                                                                    (ol_base + num_tiles * ( opb_size.opaque
+                                                                                           + opb_size.opaque_modifier_volume
+                                                                                           + opb_size.translucent
+                                                                                           )
+                                                                             + (opb_size.translucent_modifier_volume * ix)
+                                                                     );
+        region_array[ix].list_pointer.punch_through               = (opb_size.punch_through        == 0) ? REGION_ARRAY__LIST_POINTER__EMPTY :
+                                                                    (ol_base + num_tiles * ( opb_size.opaque
+                                                                                           + opb_size.opaque_modifier_volume
+                                                                                           + opb_size.translucent
+                                                                                           + opb_size.translucent_modifier_volume
+                                                                                           )
+                                                                             + (opb_size.punch_through * ix)
+                                                                     );
+
+        ix += 1;
+      }
+    }
+
+    system.LMMODE0 = 1; // 32-bit address space
+    system.LMMODE1 = 1; // 32-bit address space
+
+    void * dst = (void *)(&ta_fifo_texture_memory[region_array_start]);
+    void * src = (void *)(region_array);
+    sh7091::store_queue_transfer::copy(dst, src, (sizeof (region_array_entry)) * num_tiles);
+  }
+}

dreamcast2/holly/region_array.hpp

@@ -0,0 +1,41 @@
+#pragma once
+
+#include <cstdint>
+
+namespace holly {
+  namespace region_array {
+    struct region_array_entry {
+      uint32_t tile;
+      struct {
+        uint32_t opaque;
+        uint32_t opaque_modifier_volume;
+        uint32_t translucent;
+        uint32_t translucent_modifier_volume;
+        uint32_t punch_through;
+      } list_pointer;
+    };
+
+    struct list_block_size {
+      uint32_t opaque;
+      uint32_t opaque_modifier_volume;
+      uint32_t translucent;
+      uint32_t translucent_modifier_volume;
+      uint32_t punch_through;
+
+      uint32_t total() const
+      {
+        return opaque
+             + opaque_modifier_volume
+             + translucent
+             + translucent_modifier_volume
+             + punch_through;
+      }
+    };
+
+    void transfer_region_array(const int tile_width,
+                               const int tile_height,
+                               const list_block_size& list_block_size,
+                               const uint32_t region_array_start,
+                               const uint32_t object_list_start);
+  }
+}

dreamcast2/holly/region_array_bits.hpp

@@ -0,0 +1,22 @@
+#pragma once
+
+#include <cstdint>
+
+namespace holly {
+  namespace region_array {
+    namespace tile {
+      constexpr uint32_t last_region = 1 << 31;
+      constexpr uint32_t z_clear = 1 << 30;
+      constexpr uint32_t pre_sort = 1 << 29;
+      constexpr uint32_t flush_accumulate = 1 << 28;
+      constexpr uint32_t y_position(uint32_t num) { return (num & 0x3f) << 8; }
+      constexpr uint32_t x_position(uint32_t num) { return (num & 0x3f) << 2; }
+    }
+
+    namespace list_pointer {
+      constexpr uint32_t empty = 1 << 31;
+      constexpr uint32_t object_list(uint32_t num) { return (num & 0xfffffc) << 0; }
+    }
+
+  }
+}

dreamcast2/memorymap.hpp

@@ -0,0 +1,15 @@
+#include <cstdint>
+
+extern volatile uint8_t system_boot_rom[0x200000] __asm("system_boot_rom");
+extern volatile uint8_t aica_wave_memory[0x200000] __asm("aica_wave_memory");
+extern volatile uint8_t texture_memory64[0x800000] __asm("texture_memory64");
+extern volatile uint8_t texture_memory32[0x800000] __asm("texture_memory32");
+extern volatile uint8_t system_memory[0x1000000] __asm("system_memory");
+extern volatile uint8_t ta_fifo_polygon_converter[0x800000] __asm("ta_fifo_polygon_converter");
+extern volatile uint8_t ta_fifo_yuv_converter[0x800000] __asm("ta_fifo_yuv_converter");
+extern volatile uint8_t ta_fifo_texture_memory[0x800000] __asm("ta_fifo_texture_memory");
+extern volatile uint8_t ta_fifo_polygon_converter_mirror[0x800000] __asm("ta_fifo_polygon_converter_mirror");
+extern volatile uint8_t ta_fifo_yuv_converter_mirror[0x800000] __asm("ta_fifo_yuv_converter_mirror");
+extern volatile uint8_t ta_fifo_texture_memory_mirror[0x800000] __asm("ta_fifo_texture_memory_mirror");
+extern volatile uint8_t store_queue[0x4000000] __asm("store_queue");
+extern volatile uint8_t sh7091_oc_d[0x1000] __asm("sh7091_oc_d");

dreamcast2/reg.hpp

@@ -0,0 +1,12 @@
+#pragma once
+
+#include <cstddef>
+#include <cstdint>
+
+typedef volatile uint8_t reg8;
+typedef volatile uint16_t reg16;
+typedef volatile uint32_t reg32;
+
+static_assert((sizeof (reg8)) == 1);
+static_assert((sizeof (reg16)) == 2);
+static_assert((sizeof (reg32)) == 4);

dreamcast2/regs/block_regs.py

@@ -0,0 +1,100 @@
+import sys
+
+from generate import renderer
+from csv_input import read_input
+
+def size_p(size):
+    return size in {1, 2, 4}
+
+def size_to_type(size):
+    if size == 1:
+        return "reg8 "
+    elif size == 2:
+        return "reg16"
+    elif size == 4:
+        return "reg32"
+    else:
+        raise NotImplemented(size)
+
+def new_writer():
+    first_address = 0
+    next_address = 0
+    last_block = None
+    size_total = 0
+    reserved_num = 0
+    stack = []
+
+    def terminate():
+        nonlocal last_block
+        nonlocal stack
+
+        if last_block is not None:
+            yield "};"
+            for address, name in stack:
+                yield f"static_assert((offsetof (struct {last_block.lower()}_reg, {name})) == {hex(address - first_address)});"
+            yield ""
+        stack = []
+
+    def process_row(row):
+        nonlocal first_address
+        nonlocal next_address
+        nonlocal last_block
+        nonlocal reserved_num
+        nonlocal size_total
+        nonlocal stack
+
+        block = row["block"]
+        _offset = int(row["offset"], 16) if "offset" in row else 0
+        _address = int(row["address"], 16)
+        assert _offset  <= 0xff
+        assert _address <= 0xffff
+        offset_address = (_offset << 16)
+        address = offset_address | (_address << 0)
+        size = int(row["size"], 10)
+        name = row["name"]
+        description = row["description"]
+
+        if block != last_block:
+            yield from terminate()
+            first_address = offset_address
+            next_address = offset_address
+            size_total = 0
+            reserved_num = 0
+            yield f"struct {block.lower()}_reg {{"
+
+        assert address >= next_address, row
+        if address > next_address:
+            padding = address - next_address
+            type = size_to_type(1)
+            yield f"{type} _pad{reserved_num}[{padding}];"
+            reserved_num += 1
+            size_total += padding
+
+        def field():
+            if size_p(size):
+                assert address % size == 0
+                type = size_to_type(size)
+                return f"{type} {name};"
+            else:
+                type = size_to_type(4)
+                return f"{type} {name}[{size // 4}];"
+
+        yield field().ljust(27) + f"/* {description} */"
+
+        stack.append((address, name))
+        next_address = address + size
+        last_block = block
+        size_total += size
+
+    def process(rows):
+        for row in rows:
+            yield from process_row(row)
+        yield from terminate()
+
+    return process
+
+def headers():
+    yield "#pragma once"
+    yield ""
+    yield '#include "reg.hpp"'
+    yield ""

dreamcast2/regs/csv_input.py

@@ -0,0 +1,27 @@
+import csv
+
+def as_dict(header, row0):
+    row = [s.strip() for s in row0]
+    return dict(zip(header, row))
+
+def read_input(filename):
+    with open(filename) as f:
+        reader = csv.reader(f, delimiter=",", quotechar='"')
+        header, *rows = reader
+
+    rows = [
+        as_dict(header, row)
+        for row in rows
+        if "".join(map(str, row)).strip()
+    ]
+
+    return rows
+
+def read_input_headerless(filename):
+    with open(filename) as f:
+        reader = csv.reader(f, delimiter=",", quotechar='"')
+        rows = [
+            [s.strip() for s in row]
+            for row in reader
+        ]
+    return rows

dreamcast2/regs/generate.py

@@ -0,0 +1,43 @@
+import io
+
+def should_autonewline(line):
+    return (
+        "static_assert" not in line
+        and "extern" not in line
+        and (len(line.split()) < 2 or line.split()[1] != '=') # hacky; meh
+    )
+
+def _render(out, lines):
+    indent = " "
+    level = 0
+    #namespace = 0
+    for l in lines:
+        if l and (l[0] == "}" or l[0] == ")"):
+            level -= 2
+            #if level < 0:
+                #assert namespace >= 0
+                #namespace -= 1
+                #level = 0
+            assert level >= 0
+
+        if len(l) == 0:
+            out.write("\n")
+        else:
+            out.write(indent * level + l + "\n")
+
+        if l and (l[-1] == "{" or l[-1] == "("):
+            #if l.startswith("namespace"):
+            #    namespace += 1
+            #else:
+            level += 2
+
+        if level == 0 and l and l[-1] == ";":
+            if should_autonewline(l):
+                out.write("\n")
+    return out
+
+def renderer():
+    out = io.StringIO()
+    def render(lines):
+        return _render(out, lines)
+    return render, out

dreamcast2/regs/holly.py

@@ -0,0 +1,18 @@
+import sys
+
+from csv_input import read_input
+from generate import renderer
+from block_regs import new_writer
+from block_regs import headers
+
+def block():
+    yield 'extern struct holly_reg holly __asm("holly");'
+
+input_file = sys.argv[1]
+rows = read_input(input_file)
+process = new_writer()
+render, out = renderer()
+render(headers())
+render(process(rows))
+render(block())
+sys.stdout.write(out.getvalue())

dreamcast2/regs/holly/holly.csv

@@ -0,0 +1,87 @@
+"block","address","size","name","r/w","description"
+"holly","0000","4","ID","R","Device ID"
+"holly","0004","4","REVISION","R","Revision Number"
+"holly","0008","4","SOFTRESET","RW","CORE & TA software reset"
+,,,,,
+"holly","0014","4","STARTRENDER","RW","Drawing start"
+"holly","0018","4","TEST_SELECT","RW","Test (writing this register is prohibited)"
+,,,,,
+"holly","0020","4","PARAM_BASE","RW","Base address for ISP parameters"
+,,,,,
+"holly","002c","4","REGION_BASE","RW","Base address for Region Array"
+"holly","0030","4","SPAN_SORT_CFG","RW","Span Sorter control"
+,,,,,
+"holly","0040","4","VO_BORDER_COL","RW","Border area color"
+"holly","0044","4","FB_R_CTRL","RW","Frame buffer read control"
+"holly","0048","4","FB_W_CTRL","RW","Frame buffer write control"
+"holly","004c","4","FB_W_LINESTRIDE","RW","Frame buffer line stride"
+"holly","0050","4","FB_R_SOF1","RW","Read start address for field - 1/strip - 1"
+"holly","0054","4","FB_R_SOF2","RW","Read start address for field - 2/strip - 2"
+,,,,,
+"holly","005c","4","FB_R_SIZE","RW","Frame buffer XY size"
+"holly","0060","4","FB_W_SOF1","RW","Write start address for field - 1/strip - 1"
+"holly","0064","4","FB_W_SOF2","RW","Write start address for field - 2/strip - 2"
+"holly","0068","4","FB_X_CLIP","RW","Pixel clip X coordinate"
+"holly","006c","4","FB_Y_CLIP","RW","Pixel clip Y coordinate"
+,,,,,
+"holly","0074","4","FPU_SHAD_SCALE","RW","Intensity Volume mode"
+"holly","0078","4","FPU_CULL_VAL","RW","Comparison value for culling"
+"holly","007c","4","FPU_PARAM_CFG","RW","Parameter read control"
+"holly","0080","4","HALF_OFFSET","RW","Pixel sampling control"
+"holly","0084","4","FPU_PERP_VAL","RW","Comparison value for perpendicular polygons"
+"holly","0088","4","ISP_BACKGND_D","RW","Background surface depth"
+"holly","008c","4","ISP_BACKGND_T","RW","Background surface tag"
+,,,,,
+"holly","0098","4","ISP_FEED_CFG","RW","Translucent polygon sort mode"
+,,,,,
+"holly","00a0","4","SDRAM_REFRESH","RW","Texture memory refresh counter"
+"holly","00a4","4","SDRAM_ARB_CFG","RW","Texture memory arbiter control"
+"holly","00a8","4","SDRAM_CFG","RW","Texture memory control"
+,,,,,
+"holly","00b0","4","FOG_COL_RAM","RW","Color for Look Up table Fog"
+"holly","00b4","4","FOG_COL_VERT","RW","Color for vertex Fog"
+"holly","00b8","4","FOG_DENSITY","RW","Fog scale value"
+"holly","00bc","4","FOG_CLAMP_MAX","RW","Color clamping maximum value"
+"holly","00c0","4","FOG_CLAMP_MIN","RW","Color clamping minimum value"
+"holly","00c4","4","SPG_TRIGGER_POS","RW","External trigger signal HV counter value"
+"holly","00c8","4","SPG_HBLANK_INT","RW","H-blank interrupt control"
+"holly","00cc","4","SPG_VBLANK_INT","RW","V-blank interrupt control"
+"holly","00d0","4","SPG_CONTROL","RW","Sync pulse generator control"
+"holly","00d4","4","SPG_HBLANK","RW","H-blank control"
+"holly","00d8","4","SPG_LOAD","RW","HV counter load value"
+"holly","00dc","4","SPG_VBLANK","RW","V-blank control"
+"holly","00e0","4","SPG_WIDTH","RW","Sync width control"
+"holly","00e4","4","TEXT_CONTROL","RW","Texturing control"
+"holly","00e8","4","VO_CONTROL","RW","Video output control"
+"holly","00ec","4","VO_STARTX","RW","Video output start X position"
+"holly","00f0","4","VO_STARTY","RW","Video output start Y position"
+"holly","00f4","4","SCALER_CTL","RW","X & Y scaler control"
+,,,,,
+"holly","0108","4","PAL_RAM_CTRL","RW","Palette RAM control"
+"holly","010c","4","SPG_STATUS","R","Sync pulse generator status"
+"holly","0110","4","FB_BURSTCTRL","RW","Frame buffer burst control"
+"holly","0114","4","FB_C_SOF","R","Current frame buffer start address"
+"holly","0118","4","Y_COEFF","RW","Y scaling coefficent"
+"holly","011c","4","PT_ALPHA_REF","RW","Alpha value for Punch Through polygon comparison"
+,,,,,
+"holly","0124","4","TA_OL_BASE","RW","Object List write start address"
+"holly","0128","4","TA_ISP_BASE","RW","ISP/TSP Parameter write start address"
+"holly","012c","4","TA_OL_LIMIT","RW","Object List write limit address"
+"holly","0130","4","TA_ISP_LIMIT","RW","ISP/TSP Parameter limit address"
+"holly","0134","4","TA_NEXT_OPB","R","Start address for the Object Pointer Block"
+"holly","0138","4","TA_ITP_CURRENT","R","Starting address where the next ISP/TSP Parameters are stored"
+"holly","013c","4","TA_GLOB_TILE_CLIP","RW","Global Tile Clip control"
+"holly","0140","4","TA_ALLOC_CTRL","RW","Object list control"
+"holly","0144","4","TA_LIST_INIT","RW","TA initialization"
+"holly","0148","4","TA_YUV_TEX_BASE","RW","YUV422 texture write start address"
+"holly","014c","4","TA_YUV_TEX_CTRL","RW","YUV converter control"
+"holly","0150","4","TA_YUV_TEX_CNT","R","YUV converter macro block counter value"
+,,,,,
+"holly","0160","4","TA_LIST_CONT","RW","TA continuation processing"
+"holly","0164","4","TA_NEXT_OPB_INIT","RW","Additional OPB starting address"
+,,,,,
+"holly","0200","512","FOG_TABLE","RW","Look-up table fog data"
+,,,,,
+"holly","0600","2400","TA_OL_POINTERS","R","TA Object List Pointer data"
+,,,,,
+"holly","1000","4096","PALETTE_RAM","RW","Palette RAM"

dreamcast2/regs/holly/holly_bits.csv

@@ -0,0 +1,327 @@
+"register_name","enum_name","bits","bit_name","value","mask","description",,,,,
+"ID",,"31-16","device_id",,,,,,,,
+"ID",,"15-0","vendor_id",,,,,,,,
+,,,,,,,,,,,
+"REVISION",,"15-0","chip_revision",,,,,,,,
+,,,,,,,,,,,
+"SOFTRESET",,2,"sdram_if_soft_reset",1,,,,,,,
+"SOFTRESET",,1,"pipeline_soft_reset",1,,,,,,,
+"SOFTRESET",,0,"ta_soft_reset",1,,,,,,,
+,,,,,,,,,,,
+"STARTRENDER",,0,"start_render",1,,,,,,,
+,,,,,,,,,,,
+"TEST_SELECT",,"9-5","diagdb_data",,,,,,,,
+"TEST_SELECT",,"4-0","diagda_data",,,,,,,,
+,,,,,,,,,,,
+"PARAM_BASE",,"23-0","base_address",,"0xf00000",,,,,,
+,,,,,,,,,,,
+"REGION_BASE",,"23-0","base_address",,"0xfffffc",,,,,,
+,,,,,,,,,,,
+"SPAN_SORT_CFG",,16,"cache_bypass",1,,,,,,,
+"SPAN_SORT_CFG",,8,"offset_sort_enable",1,,,,,,,
+"SPAN_SORT_CFG",,0,"span_sort_enable",1,,,,,,,
+,,,,,,,,,,,
+"VO_BORDER_COL",,24,"chroma",,"0b1",,,,,,
+"VO_BORDER_COL",,"23-16","red",,"0xff",,,,,,
+"VO_BORDER_COL",,"15-8","green",,"0xff",,,,,,
+"VO_BORDER_COL",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"FB_R_CTRL","vclk_div",23,"pclk_vclk_2",0,,,,,,,
+"FB_R_CTRL","vclk_div",23,"pclk_vclk_1",1,,,,,,,
+"FB_R_CTRL",,22,"fb_strip_buf_en",1,,,,,,,
+"FB_R_CTRL",,"21-16","fb_stripsize",,"0b111_110","In units of 16 lines, in multiples of 32 lines. 0x02 is 32 lines, 0x04 is 64 lines, 0x03 is an illegal value",,,,,
+"FB_R_CTRL",,"15-8","fb_chroma_threshold",,"0xff",,,,,,
+"FB_R_CTRL",,"6-4","fb_concat",,"0b11",,,,,,
+"FB_R_CTRL","fb_depth","3-2","xrgb0555",0,,,,,,,
+"FB_R_CTRL","fb_depth","3-2","rgb565",1,,,,,,,
+"FB_R_CTRL","fb_depth","3-2","rgb888",2,,,,,,,
+"FB_R_CTRL","fb_depth","3-2","xrgb0888",3,,,,,,,
+"FB_R_CTRL",,1,"fb_line_double",1,,,,,,,
+"FB_R_CTRL",,0,"fb_enable",1,,,,,,,
+,,,,,,,,,,,
+"FB_W_CTRL",,"23-16","fb_alpha_threshold",,"0xff",,,,,,
+"FB_W_CTRL",,"15-8","fb_kval",,"0xff",,,,,,
+"FB_W_CTRL",,3,"fb_dither",1,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","krgb0555",0,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","rgb565",1,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","argb4444",2,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","argb1555",3,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","rgb888",4,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","krgb0888",5,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","argb8888",6,,,,,,,
+,,,,,,,,,,,
+"FB_W_LINESTRIDE",,"8-0","fb_line_stride",,"0xff","In 8-byte units",,,,,
+,,,,,,,,,,,
+"FB_R_SOF1",,"23-0","frame_buffer_read_address_frame_1",,"0xfffffc",,,,,,
+,,,,,,,,,,,
+"FB_R_SOF2",,"23-0","frame_buffer_read_address_frame_2",,"0xfffffc",,,,,,
+,,,,,,,,,,,
+"FB_R_SIZE",,"29-20","fb_modulus",,"0x3ff","In 4-byte units",,,,,
+"FB_R_SIZE",,"19-10","fb_y_size",,"0x3ff",,,,,,
+"FB_R_SIZE",,"9-0","fb_x_size",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"FB_W_SOF1",,"24-0","frame_buffer_write_address_frame_1",,"0x1fffffc",,,,,,
+,,,,,,,,,,,
+"FB_W_SOF2",,"24-0","frame_buffer_write_address_frame_2",,"0x1fffffc",,,,,,
+,,,,,,,,,,,
+"FB_X_CLIP",,"26-16","fb_x_clip_max",,"0x7ff",,,,,,
+"FB_X_CLIP",,"10-0","fb_x_clip_min",,"0x7ff",,,,,,
+,,,,,,,,,,,
+"FB_Y_CLIP",,"25-16","fb_y_clip_max",,"0x3ff",,,,,,
+"FB_Y_CLIP",,"9-0","fb_y_clip_min",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"FPU_SHAD_SCALE","simple_shadow_enable",8,"parameter_selection_volume_mode",0,,,,,,,
+"FPU_SHAD_SCALE","simple_shadow_enable",8,"intensity_volume_mode",1,,,,,,,
+"FPU_SHAD_SCALE",,"7-0","scale_factor_for_shadows",,"0xff",,,,,,
+,,,,,,,,,,,
+"FPU_CULL_VAL",,"30-0","culling_comparison_value",,"float_0_8_23",,,,,,
+,,,,,,,,,,,
+"FPU_PARAM_CFG","region_header_type",21,"type_1",0,,,,,,,
+"FPU_PARAM_CFG","region_header_type",21,"type_2",1,,,,,,,
+"FPU_PARAM_CFG",,"19-14","tsp_parameter_burst_threshold",,"0x3f",,,,,,
+"FPU_PARAM_CFG",,"13-8","isp_parameter_burst_threshold",,"0x3f",,,,,,
+"FPU_PARAM_CFG",,"7-4","pointer_burst_size",,"0xf",,,,,,
+"FPU_PARAM_CFG",,"3-0","pointer_first_burst_size",,"0xf",,,,,,
+,,,,,,,,,,,
+"HALF_OFFSET","tsp_texel_sampling_position",2,"top_left",1,,,,,,,
+"HALF_OFFSET","tsp_texel_sampling_position",2,"center",1,,,,,,,
+"HALF_OFFSET","tsp_pixel_sampling_position",1,"top_left",1,,,,,,,
+"HALF_OFFSET","tsp_pixel_sampling_position",1,"center",1,,,,,,,
+"HALF_OFFSET","fpu_pixel_sampling_position",0,"top_left",1,,,,,,,
+"HALF_OFFSET","fpu_pixel_sampling_position",0,"center",1,,,,,,,
+,,,,,,,,,,,
+"FPU_PERP_VAL",,"30-0","perpendicular_triangle_compare",,"float_0_8_23",,,,,,
+,,,,,,,,,,,
+"ISP_BACKGND_D",,"31-4","background_plane_depth",,"float_1_8_19",,,,,,
+,,,,,,,,,,,
+"ISP_BACKGND_T",,28,"cache_bypass",1,,,,,,,
+"ISP_BACKGND_T",,27,"shadow",1,,,,,,,
+"ISP_BACKGND_T",,"26-24","skip",,"0b111",,,,,,
+"ISP_BACKGND_T",,"23-3","tag_address",,"0x1fffff","In 32-bit units",,,,,
+"ISP_BACKGND_T",,"2-0","tag_offset",,"0b111",,,,,,
+,,,,,,,,,,,
+"ISP_FEED_CFG",,"23-14","cache_size_for_translucency",,"0x3ff","Must be between 0x020 and 0x200",,,,,
+"ISP_FEED_CFG",,"13-4","punch_through_chunk_size",,"0x3ff","Must be between 0x020 and 0x200, must be larger than cache_size_for_translucency",,,,,
+"ISP_FEED_CFG",,3,"discard_mode",1,,,,,,,
+"ISP_FEED_CFG",,0,"pre_sort_mode",1,,,,,,,
+,,,,,,,,,,,
+"SDRAM_REFRESH",,"7-0","refresh_counter_value",,"0xff",,,,,,
+,,,,,,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","priority_only","0x0",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","rendered_data","0x1",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","texture_vq_index","0x2",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","texture_normal_data_and_vq_codebook","0x3",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","tile_accelerator_isp_tsp_data","0x4",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","tile_accelerator_pointers","0x5",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","sh4","0x6",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","tsp_parameters","0x7",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","tsp_region_data","0x8",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","isp_pointer_data","0x9",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","isp_parameters","0xa",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","crt_controller","0xb",,,,,,,
+"SDRAM_ARB_CFG","arbiter_priority_control","17-16","priority_arbitration_only","0x0",,,,,,,
+"SDRAM_ARB_CFG","arbiter_priority_control","17-16","override_value_field","0x1",,,,,,,
+"SDRAM_ARB_CFG","arbiter_priority_control","17-16","round_robin_counter","0x2",,,,,,,
+"SDRAM_ARB_CFG",,"15-8","arbiter_crt_page_break_latency_count_value",,"0xff",,,,,,
+"SDRAM_ARB_CFG",,"7-0","arbiter_page_break_latency_count_value",,"0xff",,,,,,
+,,,,,,,,,,,
+"SDRAM_CFG",,"28-26","read_command_to_returned_data_delay",,"0b111",,,,,,
+"SDRAM_CFG",,"25-23","cas_latency_value",,"0b111",,,,,,
+"SDRAM_CFG",,"22-21","activate_to_activate_period",,"0b11",,,,,,
+"SDRAM_CFG",,"20-18","read_to_write_period",,"0b111",,,,,,
+"SDRAM_CFG",,"17-14","refresh_to_activate_period",,"0b1111",,,,,,
+"SDRAM_CFG",,"11-10","pre_charge_to_activate_period",,"0b11",,,,,,
+"SDRAM_CFG",,"9-6","activate_to_pre_charge_period",,"0b1111",,,,,,
+"SDRAM_CFG",,"5-4","activate_to_read_write_command_period",,"0b11",,,,,,
+"SDRAM_CFG",,"3-2","write_to_pre_charge_period",,"0b11",,,,,,
+"SDRAM_CFG",,"1-0","read_to_pre_charge_period",,"0b11",,,,,,
+,,,,,,,,,,,
+"FOG_COL_RAM",,"23-16","red",,"0xff",,,,,,
+"FOG_COL_RAM",,"15-8","green",,"0xff",,,,,,
+"FOG_COL_RAM",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_COL_VERT",,"23-16","red",,"0xff",,,,,,
+"FOG_COL_VERT",,"15-8","green",,"0xff",,,,,,
+"FOG_COL_VERT",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_DENSITY",,"15-8","fog_scale_mantissa",,"0xff",,,,,,
+"FOG_DENSITY",,"7-0","fog_scale_exponent",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_CLAMP_MAX",,"31-24","alpha",,"0xff",,,,,,
+"FOG_CLAMP_MAX",,"23-16","red",,"0xff",,,,,,
+"FOG_CLAMP_MAX",,"15-8","green",,"0xff",,,,,,
+"FOG_CLAMP_MAX",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_CLAMP_MIN",,"31-24","alpha",,"0xff",,,,,,
+"FOG_CLAMP_MIN",,"23-16","red",,"0xff",,,,,,
+"FOG_CLAMP_MIN",,"15-8","green",,"0xff",,,,,,
+"FOG_CLAMP_MIN",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"SPG_TRIGGER_POS",,"25-16","trigger_v_count",,,,,,,,
+"SPG_TRIGGER_POS",,"9-0","trigger_h_count",,,,,,,,
+,,,,,,,,,,,
+"SPG_HBLANK_INT",,"25-16","hblank_in_interrupt",,,,,,,,
+"SPG_HBLANK_INT","hblank_int_mode","13-12","output_equal_line_comp_val","0x0",,,,,,,
+"SPG_HBLANK_INT","hblank_int_mode","13-12","output_every_line_comp_val","0x1",,,,,,,
+"SPG_HBLANK_INT","hblank_int_mode","13-12","output_every_line","0x2",,,,,,,
+"SPG_HBLANK_INT",,"9-0","line_comp_val",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_VBLANK_INT",,"25-16","vblank_out_interrupt_line_number",,"0x3ff",,,,,,
+"SPG_VBLANK_INT",,"9-0","vblank_in_interrupt_line_number",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_CONTROL","csync_on_h",9,"hsync",0,,,,,,,
+"SPG_CONTROL","csync_on_h",9,"csync",1,,,,,,,
+"SPG_CONTROL","sync_direction",8,"input",0,,,,,,,
+"SPG_CONTROL","sync_direction",8,"output",1,,,,,,,
+"SPG_CONTROL",,7,"pal",1,,,,,,,
+"SPG_CONTROL",,6,"ntsc",1,,,,,,,
+"SPG_CONTROL",,5,"force_field2",1,,,,,,,
+"SPG_CONTROL",,4,"interlace",1,,,,,,,
+"SPG_CONTROL",,3,"spg_lock",1,,,,,,,
+"SPG_CONTROL","mcsync_pol",2,"active_low",0,,,,,,,
+"SPG_CONTROL","mcsync_pol",2,"active_high",1,,,,,,,
+"SPG_CONTROL","mvsync_pol",1,"active_low",0,,,,,,,
+"SPG_CONTROL","mvsync_pol",1,"active_high",1,,,,,,,
+"SPG_CONTROL","mhsync_pol",0,"active_low",0,,,,,,,
+"SPG_CONTROL","mhsync_pol",0,"active_high",1,,,,,,,
+,,,,,,,,,,,
+"SPG_HBLANK",,"25-16","hbend",,"0x3ff",,,,,,
+"SPG_HBLANK",,"9-0","hbstart",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_LOAD",,"25-16","vcount",,"0x3ff",,,,,,
+"SPG_LOAD",,"9-0","hcount",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_VBLANK",,"25-16","vbend",,"0x3ff",,,,,,
+"SPG_VBLANK",,"9-0","vbstart",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_WIDTH",,"31-22","eqwidth",,"0x3ff",,,,,,
+"SPG_WIDTH",,"21-12","bpwidth",,"0x3ff",,,,,,
+"SPG_WIDTH",,"11-8","vswidth",,"0b1111",,,,,,
+"SPG_WIDTH",,"6-0","hswidth",,"0x7f",,,,,,
+,,,,,,,,,,,
+"TEXT_CONTROL","code_book_endian",17,"little_endian",0,,,,,,,
+"TEXT_CONTROL","code_book_endian",17,"big_endian",1,,,,,,,
+"TEXT_CONTROL","index_endian",16,"little_endian",0,,,,,,,
+"TEXT_CONTROL","index_endian",16,"big_endian",1,,,,,,,
+"TEXT_CONTROL",,"12-8","bank_bit",,"0x1f",,,,,,
+"TEXT_CONTROL",,"4-0","stride",,"0x1f",,,,,,
+,,,,,,,,,,,
+"VO_CONTROL",,21,"pclk_delay_reset",1,,,,,,,
+"VO_CONTROL",,"20-16","pclk_delay",,"0b11111",,,,,,
+"VO_CONTROL",,8,"pixel_double",1,,,,,,,
+"VO_CONTROL","field_mode","7-4","use_field_flag_from_spg","0x0",,,,,,,
+"VO_CONTROL","field_mode","7-4","use_inverse_of_field_flag_from_spg","0x1",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_1_fixed","0x2",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_2_fixed","0x3",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_1_when_the_active_edges_of_hsync_and_vsync_match","0x4",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_2_when_the_active_edges_of_hsync_and_vsync_match","0x5",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_1_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge","0x6",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_2_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge","0x7",,,,,,,
+"VO_CONTROL","field_mode","7-4","inverted_at_the_active_edge_of_vsync","0x8",,,,,,,
+"VO_CONTROL",,3,"blank_video",1,,,,,,,
+"VO_CONTROL","blank_pol",2,"active_low",0,,,,,,,
+"VO_CONTROL","blank_pol",2,"active_high",1,,,,,,,
+"VO_CONTROL","vsync_pol",1,"active_low",0,,,,,,,
+"VO_CONTROL","vsync_pol",1,"active_high",1,,,,,,,
+"VO_CONTROL","hsync_pol",0,"active_low",0,,,,,,,
+"VO_CONTROL","hsync_pol",0,"active_high",1,,,,,,,
+,,,,,,,,,,,
+"VO_STARTX",,"9-0","horizontal_start_position",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"VO_STARTY",,"25-16","vertical_start_position_on_field_2",,"0x3ff",,,,,,
+"VO_STARTY",,"9-0","vertical_start_position_on_field_1",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SCALER_CTL","field_select",18,"field_1",0,,,,,,,
+"SCALER_CTL","field_select",18,"field_2",1,,,,,,,
+"SCALER_CTL",,17,"interlace",1,,,,,,,
+"SCALER_CTL",,16,"horizontal_scaling_enable",1,,,,,,,
+"SCALER_CTL",,"15-0","vertical_scale_factor",,"0xffff",,,,,,
+,,,,,,,,,,,
+"PAL_RAM_CTRL","pixel_format","1-0","argb1555",0,,,,,,,
+"PAL_RAM_CTRL","pixel_format","1-0","rgb565",1,,,,,,,
+"PAL_RAM_CTRL","pixel_format","1-0","argb4444",2,,,,,,,
+"PAL_RAM_CTRL","pixel_format","1-0","argb8888",3,,,,,,,
+,,,,,,,,,,,
+"SPG_STATUS",,13,"vsync",,,,,,,,
+"SPG_STATUS",,12,"hsync",,,,,,,,
+"SPG_STATUS",,11,"blank",,,,,,,,
+"SPG_STATUS",,10,"fieldnum",,,,,,,,
+"SPG_STATUS",,"9-0","scanline",,,,,,,,
+,,,,,,,,,,,
+"FB_BURSTCTRL",,"19-16","wr_burst",,"0b1111",,,,,,
+"FB_BURSTCTRL",,"14-8","vid_lat",,"0x7f",,,,,,
+"FB_BURSTCTRL",,"5-0","vid_burst",,"0x3f",,,,,," >"
+,,,,,,,,,,,
+"FB_C_SOF",,"23-0","frame_buffer_current_read_address",,,,,,,,
+,,,,,,,,,,,
+"Y_COEFF",,"15-8","coefficient_1",,"0xff",,,,,,
+"Y_COEFF",,"7-0","coefficient_0_2",,"0xff",,,,,,
+,,,,,,,,,,,
+"PT_ALPHA_REF",,"7-0","alpha_reference_for_punch_through",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_TABLE",,"15-0","fog_table_data",,"0xffff",,,,,,
+,,,,,,,,,,,
+"PALETTE_RAM",,"31-0","palette_data",,"0xffff_ffff",,,,,,
+,,,,,,,,,,,
+"TA_OL_BASE",,"23-0","base_address",,"0xffffe0","in 32-byte units",,,,,
+,,,,,,,,,,,
+"TA_ISP_BASE",,"23-0","base_address",,"0xfffffc","in 4-byte units",,,,,
+,,,,,,,,,,,
+"TA_OL_LIMIT",,"23-0","limit_address",,"0xffffe0","in 32-byte units",,,,,
+,,,,,,,,,,,
+"TA_ISP_LIMIT",,"23-0","limit_address",,"0xfffffc","in 4-byte units",,,,,
+,,,,,,,,,,,
+"TA_NEXT_OPB",,"23-0","address",,"0xffffe0","in 32-byte units",,,,,
+,,,,,,,,,,,
+"TA_ITP_CURRENT",,"23-0","address",,,,,,,,
+,,,,,,,,,,,
+"TA_GLOB_TILE_CLIP",,"19-16","tile_y_num",,"0xf",,,,,,
+"TA_GLOB_TILE_CLIP",,"5-0","tile_x_num",,"0x1f",,,,,,
+,,,,,,,,,,,
+"TA_ALLOC_CTRL","opb_mode",20,"increasing_addresses",0,,,,,,,
+"TA_ALLOC_CTRL","opb_mode",20,"decreasing_addresses",1,,,,,,,
+"TA_ALLOC_CTRL","pt_opb","17-16","no_list",0,,,,,,,
+"TA_ALLOC_CTRL","pt_opb","17-16","8x4byte",1,,,,,,,
+"TA_ALLOC_CTRL","pt_opb","17-16","16x4byte",2,,,,,,,
+"TA_ALLOC_CTRL","pt_opb","17-16","32x4byte",3,,,,,,,
+"TA_ALLOC_CTRL","tm_opb","13-12","no_list",0,,,,,,,
+"TA_ALLOC_CTRL","tm_opb","13-12","8x4byte",1,,,,,,,
+"TA_ALLOC_CTRL","tm_opb","13-12","16x4byte",2,,,,,,,
+"TA_ALLOC_CTRL","tm_opb","13-12","32x4byte",3,,,,,,,
+"TA_ALLOC_CTRL","t_opb","9-8","no_list",0,,,,,,,
+"TA_ALLOC_CTRL","t_opb","9-8","8x4byte",1,,,,,,,
+"TA_ALLOC_CTRL","t_opb","9-8","16x4byte",2,,,,,,,
+"TA_ALLOC_CTRL","t_opb","9-8","32x4byte",3,,,,,,,
+"TA_ALLOC_CTRL","om_opb","5-4","no_list",0,,,,,,,
+"TA_ALLOC_CTRL","om_opb","5-4","8x4byte",1,,,,,,,
+"TA_ALLOC_CTRL","om_opb","5-4","16x4byte",2,,,,,,,
+"TA_ALLOC_CTRL","om_opb","5-4","32x4byte",3,,,,,,,
+"TA_ALLOC_CTRL","o_opb","1-0","no_list",0,,,,,,,
+"TA_ALLOC_CTRL","o_opb","1-0","8x4byte",1,,,,,,,
+"TA_ALLOC_CTRL","o_opb","1-0","16x4byte",2,,,,,,,
+"TA_ALLOC_CTRL","o_opb","1-0","32x4byte",3,,,,,,,
+,,,,,,,,,,,
+"TA_LIST_INIT",,31,"list_init",1,,,,,,,
+,,,,,,,,,,,
+"TA_YUV_TEX_BASE",,"23-0","base_address",,"0xfffff8","in 8-byte units",,,,,
+,,,,,,,,,,,
+"TA_YUV_TEX_CTRL","yuv_form",24,"yuv420",0,,,,,,,
+"TA_YUV_TEX_CTRL","yuv_form",24,"yuv422",1,,,,,,,
+"TA_YUV_TEX_CTRL","yuv_tex",16,"one_texture",0,,,,,,,
+"TA_YUV_TEX_CTRL","yuv_tex",16,"multiple_textures",1,,,,,,,
+"TA_YUV_TEX_CTRL",,"13-8","yuv_v_size",,"0x3f",,,,,,
+"TA_YUV_TEX_CTRL",,"5-0","yuv_u_size",,"0x3f",,,,,,
+,,,,,,,,,,,
+"TA_YUV_TEX_CNT",,"12-0","yuv_num",,,,,,,,
+,,,,,,,,,,,
+"TA_LIST_CONT",,31,"list_cont",1,,,,,,,
+,,,,,,,,,,,
+"TA_NEXT_OPB_INIT",,"23-0","address",,"0xffffe0","in 32-byte units",,,,,
+,,,,,,,,,,,
+"TA_OL_POINTERS",,31,"entry",,,,,,,,
+"TA_OL_POINTERS",,30,"sprite",,,,,,,,
+"TA_OL_POINTERS",,29,"triangle",,,,,,,,
+"TA_OL_POINTERS",,"28-25","number_of_triangles_quads",,,,,,,,
+"TA_OL_POINTERS",,24,"shadow",,,,,,,,
+"TA_OL_POINTERS",,"23-2","pointer_address",,,,,,,,
+"TA_OL_POINTERS",,"1-0","skip",,,,,,,,

dreamcast2/regs/holly/region_array_bits.csv

@@ -0,0 +1,10 @@
+"register_name","enum_name","bits","bit_name","value","mask","description"
+"tile",,31,"last_region",1,,
+"tile",,30,"z_clear",1,,
+"tile",,29,"pre_sort",1,,
+"tile",,28,"flush_accumulate",1,,
+"tile",,"13-8","y_position",,"0x3f",
+"tile",,"7-2","x_position",,"0x3f",
+,,,,,,
+"list_pointer",,31,"empty",1,,
+"list_pointer",,"23-0","object_list",,"0xfffffc",

dreamcast2/regs/holly_bits.py

@@ -0,0 +1,286 @@
+import sys
+from collections import defaultdict
+from pprint import pprint
+from dataclasses import dataclass
+from typing import Union
+
+from csv_input import read_input
+from generate import renderer
+
+def aggregate_registers(d):
+    aggregated = defaultdict(list)
+    for row in d:
+        #assert row["register_name"] != ""
+        aggregated[row["register_name"]].append(row)
+    return dict(aggregated)
+
+def parse_bit_number(s):
+    assert '-' not in s, s
+    assert ',' not in s, s
+    return int(s, 10)
+
+def parse_bit_set(s, split_char, maxsplit):
+    #assert len(list(c for c in s if c == split_char)) == 1, s
+    split = list(map(parse_bit_number, s.split(split_char, maxsplit=maxsplit)))
+    for i in range(len(split) - 1):
+        left = split[i]
+        right = split[i+1]
+        assert left > right, (left, right)
+    return split
+
+def parse_bit_range(s):
+    if '-' in s:
+        left, right = parse_bit_set(s, '-', 1)
+        return set(range(right, left+1))
+    elif ',' in s:
+        bits = parse_bit_set(s, ',', -1)
+        return set(bits)
+    else:
+        num = parse_bit_number(s)
+        return set([num])
+
+def aggregate_enums(aggregated_rows):
+    non_enum = []
+    enum_aggregated = defaultdict(list)
+    all_bits = set()
+    enum_bits = dict()
+
+    def assert_unique_ordered(bits, row):
+        nonlocal all_bits
+        assert all(bit not in all_bits for bit in bits), (bits, row)
+        assert max(all_bits, default=32) > max(bits), (all_bits, bits)
+        all_bits |= bits
+
+    for row in aggregated_rows:
+        bits = parse_bit_range(row["bits"])
+        assert row["bit_name"] != "", row
+        if row["enum_name"] == "":
+            assert_unique_ordered(bits, row)
+            non_enum.append(row)
+        else:
+            if row["enum_name"] not in enum_bits:
+                assert_unique_ordered(bits, row)
+                non_enum.append(row["enum_name"])
+            else:
+                assert enum_bits[row["enum_name"]] == bits, row
+
+            enum_bits[row["enum_name"]] = bits
+            enum_aggregated[row["enum_name"]].append(row)
+
+    return non_enum, dict(enum_aggregated)
+
+@dataclass
+class enum:
+    name: str
+    defs: list[dict]
+
+@dataclass
+class register:
+    block: Union[None, str]
+    name: str
+    defs: list[Union[dict, enum]]
+
+def aggregate_all_enums(aggregated):
+    out = []
+    for register_name, rows in aggregated.items():
+        non_enum, enum_aggregated = aggregate_enums(rows)
+        def resolve(row_or_string):
+            if type(row_or_string) == str:
+                return enum(row_or_string,
+                            enum_aggregated[row_or_string])
+            elif type(row_or_string) == dict:
+                return row_or_string
+            else:
+                assert False, (row_or_string, type(row_or_string))
+
+        defs = [resolve(aggregate) for aggregate in non_enum]
+        if 'block' in rows[0]:
+            blocks = set(row['block'] for row in rows)
+            assert len(blocks) == 1, blocks
+            block_name = next(iter(blocks))
+            out.append(
+                register(block_name, register_name, defs))
+        else:
+            out.append(
+                register(None, register_name, defs))
+    return out
+
+'''
+ register(name='SCALER_CTL',
+          defs=[enum(name='field_select',
+                     defs=[{'bit_name': 'field_1',
+                            'bits': '18',
+                            'description': '',
+                            'enum_name': 'field_select',
+                            'mask': '',
+                            'register_name': 'SCALER_CTL',
+                            'value': '0'},
+                           {...}]),
+                {'bit_name': 'interlace',
+                 'bits': '17',
+                 'description': '',
+                 'enum_name': '',
+                 'mask': '',
+                 'register_name': 'SCALER_CTL',
+                 'value': '1'},
+                {...},
+                ...]),
+'''
+
+def mask_from_bits(bits):
+    mask = 0
+    for b in bits:
+        mask |= 1 << b
+    mask >>= min(bits)
+    return mask
+
+def parse_value(value):
+    return eval(value)
+
+def escape(bit_name):
+    if bit_name[0] in {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9'}:
+        return '_' + bit_name
+    else:
+        return bit_name
+
+def render_read_only(bit_def):
+    assert bit_def["value"] == ""
+    assert bit_def["mask"] == ""
+    bits = parse_bit_range(bit_def["bits"])
+    mask_value = mask_from_bits(bits)
+    yield (
+        f"constexpr uint32_t {escape(bit_def['bit_name'])}(uint32_t reg) {{ "
+        f"return (reg >> {min(bits)}) & {hex(mask_value)};"
+        " }"
+    )
+
+def render_float_mask(mask):
+    if mask == "float_0_8_23":
+        return "_i(__builtin_fabsf(num));"
+    elif mask == "float_1_8_23":
+        return "_i(num)"
+    else:
+        assert mask.startswith("float_")
+        mask = mask.removeprefix("float_")
+        sign, exponent, fraction = map(int, mask.split('_'))
+        assert exponent == 8, exponent
+        assert sign == 1
+        bit_length = (sign + exponent + fraction)
+        mask = (2 ** bit_length - 1) << (32 - bit_length)
+        return f"_i(num) & {hex(mask)}"
+
+def render_mask(bit_def):
+    assert bit_def["value"] == ""
+    mask = bit_def["mask"]
+    bits = parse_bit_range(bit_def["bits"])
+    if mask.startswith("float_"):
+        yield (
+            f"inline uint32_t {escape(bit_def['bit_name'])}(float num) {{ "
+            f"return {render_float_mask(mask)};"
+            " }"
+        )
+    else:
+        assert mask.startswith("0x") or mask.startswith("0b") or mask[0] in set(range(0, 9+1)), mask
+        mask_value = eval(mask)
+        assert mask_value & mask_from_bits(bits) == mask_value, (mask_value, mask_from_bits(bits))
+
+        yield (
+            f"constexpr uint32_t {escape(bit_def['bit_name'])}(uint32_t num) {{ "
+            f"return (num & {hex(mask_value)}) << {min(bits)};"
+            " }"
+        )
+
+def render_value(bit_def):
+    assert bit_def["mask"] == ""
+    bits = parse_bit_range(bit_def["bits"])
+    assert parse_value(bit_def["value"]) <= mask_from_bits(bits), (bit_def["value"], mask_from_bits(bits), bits)
+    bit_ix = min(bits)
+    yield f"constexpr uint32_t {escape(bit_def['bit_name'])} = {bit_def['value']} << {bit_ix};"
+
+def render_defs(bit_def):
+    if bit_def["value"] != "":
+        yield from render_value(bit_def)
+    elif bit_def["mask"] != "":
+        yield from render_mask(bit_def)
+    else:
+        yield from render_read_only(bit_def)
+
+def render_enum_mask(enum_def):
+    all_bits = set(bit_def["bits"] for bit_def in enum_def.defs)
+    assert len(all_bits) == 1
+    assert all(bit_def["bit_name"] != "bit_mask" for bit_def in enum_def.defs), bit_def
+    _bits = next(iter(all_bits))
+    bits = parse_bit_range(_bits)
+    mask_value = mask_from_bits(bits)
+    bit_ix = min(bits)
+    yield ""
+    yield f"constexpr uint32_t bit_mask = {hex(mask_value)} << {bit_ix};"
+
+def render_enum(enum_def):
+    yield f"namespace {enum_def.name.lower()} {{"
+    for bit_def in enum_def.defs:
+        yield from render_defs(bit_def)
+    yield from render_enum_mask(enum_def)
+    yield "}"
+
+def render_register(register):
+    if register.name != "":
+        yield f"namespace {register.name.lower()} {{"
+
+    last = None
+    for ix, bit_def in enumerate(register.defs):
+        if type(bit_def) is enum:
+            if ix != 0:
+                yield ""
+            yield from render_enum(bit_def)
+        else:
+            if ix != 0 and type(last) is enum:
+                yield ""
+            yield from render_defs(bit_def)
+        last = bit_def
+
+    if register.name != "":
+        yield "}"
+    yield ""
+
+def render_registers_inner(registers):
+    last_block = None
+    for register in registers:
+        if register.block != last_block:
+            assert register.block is not None
+            if last_block is not None:
+                yield '}' # end of previous namespace
+                yield ""
+            yield f'namespace {register.block.lower()} {{'
+        if register.block is None:
+            assert last_block is None
+        last_block = register.block
+
+        yield from render_register(register)
+
+    if last_block is not None:
+        yield '}' # end of block namespace
+
+def render_registers(registers, file_namespaces):
+    if file_namespaces:
+        yield f"namespace {file_namespaces[0]} {{"
+        yield from render_registers(registers, file_namespaces[1:])
+        yield '}' # end of file namespace
+    else:
+        yield from render_registers_inner(registers)
+
+def header():
+    yield "#pragma once"
+    yield ""
+    yield "#include <cstdint>"
+    yield ""
+
+if __name__ == "__main__":
+    d = read_input(sys.argv[1])
+    file_namespaces = sys.argv[2:]
+    aggregated = aggregate_registers(d)
+    registers = aggregate_all_enums(aggregated)
+    render, out = renderer()
+    render(header())
+    render(render_registers(registers, file_namespaces))
+    sys.stdout.write(out.getvalue())

dreamcast2/regs/sh7091.py

@@ -0,0 +1,145 @@
+import sys
+
+from generate import renderer
+from csv_input import read_input
+
+def size_p(size):
+    return size in {1, 2, 4}
+
+def size_to_type(size):
+    if size == 1:
+        return "reg8 "
+    elif size == 2:
+        return "reg16"
+    elif size == 4:
+        return "reg32"
+    else:
+        raise NotImplemented(size)
+
+def new_writer():
+    first_address = 0
+    next_address = 0
+    last_block = None
+    size_total = 0
+    reserved_num = 0
+    stack = []
+
+    def terminate():
+        nonlocal last_block
+        nonlocal stack
+
+        if last_block is not None:
+            yield "};"
+            for address, name in stack:
+                yield f"static_assert((offsetof (struct {last_block.lower()}_reg, {name})) == {hex(address - first_address)});"
+            yield ""
+        stack = []
+
+    def process_row(row):
+        nonlocal first_address
+        nonlocal next_address
+        nonlocal last_block
+        nonlocal reserved_num
+        nonlocal size_total
+        nonlocal stack
+
+        block = row["block"]
+        _offset = int(row["offset"], 16) if "offset" in row else 0
+        _address = int(row["address"], 16)
+        assert _offset  <= 0xff
+        assert _address <= 0xffff
+        offset_address = (_offset << 16)
+        address = offset_address | (_address << 0)
+        size = int(row["size"], 10)
+        name = row["name"]
+        description = row["description"]
+
+        if block != last_block:
+            yield from terminate()
+            first_address = offset_address
+            next_address = offset_address
+            size_total = 0
+            reserved_num = 0
+            yield f"struct {block.lower()}_reg {{"
+
+        assert address >= next_address, row
+        if address > next_address:
+            padding = address - next_address
+            type = size_to_type(1)
+            yield f"{type} _pad{reserved_num}[{padding}];"
+            reserved_num += 1
+            size_total += padding
+
+        def field():
+            if size_p(size):
+                assert address % size == 0
+                type = size_to_type(size)
+                return f"{type} {name};"
+            else:
+                type = size_to_type(4)
+                return f"{type} {name}[{size // 4}];"
+
+        yield field().ljust(27) + f"/* {description} */"
+
+        stack.append((address, name))
+        next_address = address + size
+        last_block = block
+        size_total += size
+
+    def process(rows):
+        for row in rows:
+            yield from process_row(row)
+        yield from terminate()
+
+    return process
+
+def blocks(rows):
+    stack = []
+    last_block = None
+    for row in rows:
+        block = row["block"]
+        if last_block != block:
+            offset = int(row["offset"], 16)
+            stack.append((block, offset))
+        last_block = block
+
+    yield "struct sh7091_reg {"
+    last_offset = 0
+    last_block = None
+    reserved_num = 0
+    for block, offset in stack:
+        if offset != last_offset:
+            assert last_block is not None
+            type = size_to_type(1)
+            raw_pad = (offset - last_offset) << 16
+            yield f"{type} _pad{reserved_num}[{hex(raw_pad)} - (sizeof (struct {last_block.lower()}_reg))];"
+            reserved_num += 1
+        yield f"struct {block.lower()}_reg {block};"
+        last_offset = offset
+        last_block = block
+    yield "};"
+
+    for block, offset in stack:
+        yield f"static_assert((offsetof (struct sh7091_reg, {block})) == {hex(offset << 16)});"
+
+    yield ""
+    yield 'extern struct sh7091_reg sh7091 __asm("sh7091");'
+
+def headers():
+    yield "#pragma once"
+    yield ""
+    yield "#include <cstdint>"
+    yield "#include <cstddef>"
+    yield ""
+    yield '#include "type.hpp"'
+    yield ""
+
+if __name__ == "__main__":
+    input_file = sys.argv[1]
+    rows = read_input(input_file)
+    process = new_writer()
+    render, out = renderer()
+    render(headers())
+    render(process(rows))
+    render(blocks(rows))
+    sys.stdout.write(out.getvalue())

dreamcast2/regs/sh7091/sh7091.csv

@@ -0,0 +1,126 @@
+"block","offset","address","size","name","r/w","description"
+"CCN","00","0000",4,"PTEH","RW","Page table entry high register"
+"CCN","00","0004",4,"PTEL","RW","Page table entry low register"
+"CCN","00","0008",4,"TTB","RW","Translation table base register"
+"CCN","00","000c",4,"TEA","RW","TLB exception address register"
+"CCN","00","0010",4,"MMUCR","RW","MMU control register"
+"CCN","00","0014",1,"BASRA","RW","Break ASID register A"
+"CCN","00","0018",1,"BASRB","RW","Break ASID register B"
+"CCN","00","001c",4,"CCR","RW","Cache control register"
+"CCN","00","0020",4,"TRA","RW","TRAPA exception register"
+"CCN","00","0024",4,"EXPEVT","RW","Exception event register"
+"CCN","00","0028",4,"INTEVT","RW","Interrupt event register"
+"CCN","00","0034",4,"PTEA","RW","Page table entry assistance register"
+"CCN","00","0038",4,"QACR0","RW","Queue address control register 0"
+"CCN","00","003c",4,"QACR1","RW","Queue address control register 1"
+,,,,,,
+"UBC","20","0000",4,"BARA","RW","Break address register A"
+"UBC","20","0004",1,"BAMRA","RW","Break address mask register A"
+"UBC","20","0008",2,"BBRA","RW","Break bus cycle register A"
+"UBC","20","000c",4,"BARB","RW","Break address register B"
+"UBC","20","0010",1,"BAMRB","RW","Break address mask register B"
+"UBC","20","0014",2,"BBRB","RW","Break bus cycle register B"
+"UBC","20","0018",4,"BDRB","RW","Break data register B"
+"UBC","20","001c",4,"BDMRB","RW","Break data mask register B"
+"UBC","20","0020",2,"BRCR","RW","Break control register"
+,,,,,,
+"BSC","80","0000",4,"BCR1","RW","Bus control register 1"
+"BSC","80","0004",2,"BCR2","RW","Bus control register 2"
+"BSC","80","0008",4,"WCR1","RW","Wait state control register 1"
+"BSC","80","000c",4,"WCR2","RW","Wait state control register 2"
+"BSC","80","0010",4,"WCR3","RW","Wait state control register 3"
+"BSC","80","0014",4,"MCR","RW","Memory control register"
+"BSC","80","0018",2,"PCR","RW","PCMCIA control register"
+"BSC","80","001c",2,"RTCSR","RW","Refresh timer control/status register"
+"BSC","80","0020",2,"RTCNT","RW","Refresh timer counter"
+"BSC","80","0024",2,"RTCOR","RW","Refresh timer constant counter"
+"BSC","80","0028",2,"RFCR","RW","Refresh count register"
+"BSC","80","002c",4,"PCTRA","RW","Port control register A"
+"BSC","80","0030",2,"PDTRA","RW","Port data register A"
+"BSC","80","0040",4,"PCTRB","RW","Port control register B"
+"BSC","80","0044",2,"PDTRB","RW","Port data register B"
+"BSC","80","0048",2,"GPIOIC","RW","GPIO interrupt control register"
+"BSC","90","0000",65536,"SDMR2","W","Synchronous DRAM mode registers"
+"BSC","94","0000",65536,"SDMR3","W","Synchronous DRAM mode registers"
+,,,,,,
+"DMAC","a0","0000",4,"SAR0","RW","DMA source address register 0"
+"DMAC","a0","0004",4,"DAR0","RW","DMA destination address register 0"
+"DMAC","a0","0008",4,"DMATCR0","RW","DMA transfer count register 0"
+"DMAC","a0","000c",4,"CHCR0","RW","DMA control register 0"
+"DMAC","a0","0010",4,"SAR1","RW","DMA source address register 1"
+"DMAC","a0","0014",4,"DAR1","RW","DMA destination address register 1"
+"DMAC","a0","0018",4,"DMATCR1","RW","DMA transfer count register 1"
+"DMAC","a0","001c",4,"CHCR1","RW","DMA control register 1"
+"DMAC","a0","0020",4,"SAR2","RW","DMA source address register 2"
+"DMAC","a0","0024",4,"DAR2","RW","DMA destination address register 2"
+"DMAC","a0","0028",4,"DMATCR2","RW","DMA transfer count register 2"
+"DMAC","a0","002c",4,"CHCR2","RW","DMA control register 2"
+"DMAC","a0","0030",4,"SAR3","RW","DMA source address register 3"
+"DMAC","a0","0034",4,"DAR3","RW","DMA destination address register 3"
+"DMAC","a0","0038",4,"DMATCR3","RW","DMA transfer count register 3"
+"DMAC","a0","003c",4,"CHCR3","RW","DMA control register 3"
+"DMAC","a0","0040",4,"DMAOR","RW","DMA operation register"
+,,,,,,
+"CPG","c0","0000",2,"FRQCR","RW","Frequency control register"
+"CPG","c0","0004",1,"STBCR","RW","Standby control register"
+"CPG","c0","0008",2,"WTCNT","RW","Watchdog timer counter"
+"CPG","c0","000c",2,"WTCSR","RW","Watchdog timer control/status register"
+"CPG","c0","0010",1,"STBCR2","RW","Standby control register 2"
+,,,,,,
+"RTC","c8","0000",1,"R64CNT","R","64 Hz counter"
+"RTC","c8","0004",1,"RSECCNT","RW","Second counter"
+"RTC","c8","0008",1,"RMINCNT","RW","Minute counter"
+"RTC","c8","000c",1,"RHRCNT","RW","Hour counter"
+"RTC","c8","0010",1,"RWKCNT","RW","Day-of-week counter"
+"RTC","c8","0014",1,"RDAYCNT","RW","Day counter"
+"RTC","c8","0018",1,"RMONCNT","RW","Month counter"
+"RTC","c8","001c",2,"RYRCNT","RW","Year counter"
+"RTC","c8","0020",1,"RSECAR","RW","Second alarm register"
+"RTC","c8","0024",1,"RMINAR","RW","Minute alarm register"
+"RTC","c8","0028",1,"RHRAR","RW","Hour alarm register"
+"RTC","c8","002c",1,"RWKAR","RW","Day-of-week alarm register"
+"RTC","c8","0030",1,"RDAYAR","RW","Day alarm register"
+"RTC","c8","0034",1,"RMONAR","RW","Month alarm register"
+"RTC","c8","0038",1,"RCR1","RW","RTC control register 1"
+"RTC","c8","003c",1,"RCR2","RW","RTC control register 2"
+,,,,,,
+"INTC","d0","0000",2,"ICR","RW","Interrupt control register"
+"INTC","d0","0004",2,"IPRA","RW","Interrupt priority register A"
+"INTC","d0","0008",2,"IPRB","RW","Interrupt priority register B"
+"INTC","d0","000c",2,"IPRC","RW","Interrupt priority register C"
+,,,,,,
+"TMU","d8","0000",1,"TOCR","RW","Timer output control register"
+"TMU","d8","0004",1,"TSTR","RW","Timer start register"
+"TMU","d8","0008",4,"TCOR0","RW","Timer constant register 0"
+"TMU","d8","000c",4,"TCNT0","RW","Timer counter 0"
+"TMU","d8","0010",2,"TCR0","RW","Timer control register 0"
+"TMU","d8","0014",4,"TCOR1","RW","Timer constant register 1"
+"TMU","d8","0018",4,"TCNT1","RW","Timer counter 1"
+"TMU","d8","001c",2,"TCR1","RW","Timer control register 1"
+"TMU","d8","0020",4,"TCOR2","RW","Timer constant register 2"
+"TMU","d8","0024",4,"TCNT2","RW","Timer counter 2"
+"TMU","d8","0028",2,"TCR2","RW","Timer control register 2"
+"TMU","d8","002c",4,"TCPR2","R","Timer input capture register 2"
+,,,,,,
+"SCI","e0","0000",1,"SCSMR1","RW","Serial mode register 1"
+"SCI","e0","0004",1,"SCBRR1","RW","Bit rate register 1"
+"SCI","e0","0008",1,"SCSCR1","RW","Serial control register 1"
+"SCI","e0","000c",1,"SCTDR1","RW","Transmit data register 1"
+"SCI","e0","0010",1,"SCSSR1","RW","Serial status register 1"
+"SCI","e0","0014",1,"SCRDR1","R","Receive data register 1"
+"SCI","e0","0018",1,"SCSCMR1","RW","Smart card mode register 1"
+"SCI","e0","001c",1,"SCSPTR1","RW","Serial port register"
+,,,,,,
+"SCIF","e8","0000",2,"SCSMR2","RW","Serial mode register 2"
+"SCIF","e8","0004",1,"SCBRR2","RW","Bit rate register 2"
+"SCIF","e8","0008",2,"SCSCR2","RW","Serial control register 2"
+"SCIF","e8","000c",1,"SCFTDR2","W","Transmit FIFO data register 2"
+"SCIF","e8","0010",2,"SCFSR2","RW","Serial status register 2"
+"SCIF","e8","0014",1,"SCFRDR2","R","Receive FIFO data register 2"
+"SCIF","e8","0018",2,"SCFCR2","RW","FIFO control register"
+"SCIF","e8","001c",2,"SCFDR2","R","FIFO data count register"
+"SCIF","e8","0020",2,"SCSPTR2","RW","Serial port register 2"
+"SCIF","e8","0024",2,"SCLSR2","RW","Line status register 2"
+,,,,,,
+"UDI","f0","0000",2,"SDIR","R","Instruction register"
+"UDI","f0","0008",4,"SDDR","R","Data register"

dreamcast2/regs/sh7091/sh7091_bits.csv

@@ -0,0 +1,366 @@
+"block","register_name","enum_name","bits","bit_name","value","mask","description"
+"CCN","PTEH",,"31-10","VPN",,,"Virtual Page Number"
+"CCN","PTEH",,"7-0","ASID",,,"Address space identifier"
+,,,,,,,
+"CCN","PTEL",,"28-10","PPN",,,"Physical page number"
+"CCN","PTEL","V","8","invalid","0",,"Validity"
+"CCN","PTEL","V","8","valid","1",,"Validity"
+"CCN","PTEL","SZ","7,4","1_kbyte_page","0b0000",,"Page size"
+"CCN","PTEL","SZ","7,4","4_kbyte_page","0b0001",,"Page size"
+"CCN","PTEL","SZ","7,4","64_kbyte_page","0b1000",,"Page size"
+"CCN","PTEL","SZ","7,4","1_mbyte_page","0b1001",,"Page size"
+"CCN","PTEL","PR","6-5","read_only_in_privileged_mode","0b00",,"Protection key data"
+"CCN","PTEL","PR","6-5","read_write_in_privileged_mode","0b01",,"Protection key data"
+"CCN","PTEL","PR","6-5","read_only_in_privileged_and_user_mode","0b10",,"Protection key data"
+"CCN","PTEL","PR","6-5","read_write_in_privileged_and_user_mode","0b11",,"Protection key data"
+"CCN","PTEL","C","3","not_cacheable","0",,"Cacheability bit"
+"CCN","PTEL","C","3","cacheable","1",,"Cacheability bit"
+"CCN","PTEL","D","2","write_has_not_been_performed","0",,"Dirty bit"
+"CCN","PTEL","D","2","write_has_been_performed","1",,"Dirty bit"
+"CCN","PTEL","SH","1","pages_are_shared_by_processes","0",,"Share status bit"
+"CCN","PTEL","SH","1","pages_are_not_shared_by_processes","1",,"Share status bit"
+"CCN","PTEL","WT","0","copy_back_mode","0",,"Write-through bit"
+"CCN","PTEL","WT","0","write_through_mode","1",,"Write-through bit"
+,,,,,,,
+"CCN","MMUCR",,"31-26","LRUI",,,"Least recently used ITLB"
+"CCN","MMUCR",,"23-18","URB",,,"UTLB replace boundary"
+"CCN","MMUCR",,"15-10","URC",,,"UTLB replace counter"
+"CCN","MMUCR","SQMD","9","user_privileged_access_possible","0",,"Store queue mode bit"
+"CCN","MMUCR","SQMD","9","privileged_access_possible","1",,"Store queue mode bit"
+"CCN","MMUCR","SV","8","multiple_virtual_memory_mode","0",,"Single virtual mode bit"
+"CCN","MMUCR","SV","8","single_virtual_memory_mode","1",,"Single virtual mode bit"
+"CCN","MMUCR","TI","2","invalidate_all_utlb_itlb_bits","1",,"TLB invalidate"
+"CCN","MMUCR","AT","0","mmu_disabled","0",,"Address translation bit"
+"CCN","MMUCR","AT","0","mmu_enabled","1",,"Address translation bit"
+,,,,,,,
+"CCN","BASRA",,"7-0","basa",,"0xff",
+,,,,,,,
+"CCN","BASRB",,"7-0","basa",,"0xff",
+,,,,,,,
+"CCN","CCR","IIX","15","address_bits_12_5_used_for_ic_entry_selection","0",,"IC index enable"
+"CCN","CCR","IIX","15","address_bits_25_and_11_5_used_for_ic_entry_selection","1",,"IC index enable"
+"CCN","CCR","ICI","11","clear_v_bits_of_all_ic_entries","1",,"IC invalidation"
+"CCN","CCR","ICE","8","ic_not_used","0",,"IC enable"
+"CCN","CCR","ICE","8","ic_used","1",,"IC enable"
+"CCN","CCR","OIX","7","address_bits_13_5_used_for_oc_entry_selection","0",,"OC index enable"
+"CCN","CCR","OIX","7","address_bits_25_and_12_5_used_for_oc_entry_selection","1",,"OC index enable"
+"CCN","CCR","ORA","5","16_kbytes_used_as_cache","0",,"OC RAM enable"
+"CCN","CCR","ORA","5","8_kbytes_used_as_cache_8_kbytes_used_as_ram","1",,"OC RAM enable"
+"CCN","CCR","OCI","3","clear_v_and_u_bits_of_all_oc_entries","1",,"OC invalidation"
+"CCN","CCR","CB","2","write_through_mode","0",,"Copy-back enable"
+"CCN","CCR","CB","2","copy_back_mode","1",,"Copy-back enable"
+"CCN","CCR","WT","1","copy_back_mode","0",,"Write-through enable"
+"CCN","CCR","WT","1","write_through_mode","1",,"Write-through enable"
+"CCN","CCR","OCE","0","oc_not_used","0",,"OC enable"
+"CCN","CCR","OCE","0","oc_used","1",,"OC enable"
+,,,,,,,
+"CCN","TRA",,"9-2","imm",,,
+,,,,,,,
+"CCN","EXPEVT",,"11-0","exception_code",,,
+,,,,,,,
+"CCN","INTEVT",,"11-0","exception_code",,,
+,,,,,,,
+"CCN","PTEA","TC","3","area_5_is_used","0",,"Timing control bit"
+"CCN","PTEA","TC","3","area_6_is_used","1",,"Timing control bit"
+"CCN","PTEA","SA","2-0","undefined","0b000",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","variable_size_io_space","0b001",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","8_bit_io_space","0b010",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","16_bit_io_space","0b011",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","8_bit_common_memory_space","0b100",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","16_bit_common_memory_space","0b101",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","8_bit_attribute_memory_space","0b110",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","16_bit_attribute_memory_space","0b111",,"Space attribute bits"
+,,,,,,,
+"CCN","QACR0",,"4-2","area",,"0b111",
+,,,,,,,
+"CCN","QACR1",,"4-2","area",,"0b111",
+,,,,,,,
+"DMAC","DMATCR",,"23-0","transfer_count",,"0xffffff",
+,,,,,,,
+"DMAC","CHCR","SSA","31-29","reserved_in_pcmcia_access","0b000",,
+"DMAC","CHCR","SSA","31-29","dynamic_bus_sizing_io_space","0b001",,
+"DMAC","CHCR","SSA","31-29","8_bit_io_space","0b010",,
+"DMAC","CHCR","SSA","31-29","16_bit_io_space","0b011",,
+"DMAC","CHCR","SSA","31-29","8_bit_common_memory_space","0b100",,
+"DMAC","CHCR","SSA","31-29","16_bit_common_memory_space","0b101",,
+"DMAC","CHCR","SSA","31-29","8_bit_attribute_memory_space","0b110",,
+"DMAC","CHCR","SSA","31-29","16_bit_attribute_memory_space","0b111",,
+"DMAC","CHCR","STC","28","c5_space_wait_cycle_selection","0",,
+"DMAC","CHCR","STC","28","c6_space_wait_cycle_selection","1",,
+"DMAC","CHCR","DSA","27-25","reserved_in_pcmcia_access","0b000",,
+"DMAC","CHCR","DSA","27-25","dynamic_bus_sizing_io_space","0b001",,
+"DMAC","CHCR","DSA","27-25","8_bit_io_space","0b010",,
+"DMAC","CHCR","DSA","27-25","16_bit_io_space","0b011",,
+"DMAC","CHCR","DSA","27-25","8_bit_common_memory_space","0b100",,
+"DMAC","CHCR","DSA","27-25","16_bit_common_memory_space","0b101",,
+"DMAC","CHCR","DSA","27-25","8_bit_attribute_memory_space","0b110",,
+"DMAC","CHCR","DSA","27-25","16_bit_attribute_memory_space","0b111",,
+"DMAC","CHCR","DTC","24","c5_space_wait_cycle_selection","0",,
+"DMAC","CHCR","DTC","24","c6_space_wait_cycle_selection","1",,
+"DMAC","CHCR","DS","19","low_level_detection","0",,
+"DMAC","CHCR","DS","19","falling_edge_detection","1",,
+"DMAC","CHCR","RL","18","drak_is_an_active_high","0",,
+"DMAC","CHCR","RL","18","drak_is_an_active_low","1",,
+"DMAC","CHCR","AM","17","dack_is_output_in_read_cycle","0",,
+"DMAC","CHCR","AM","17","dack_is_output_in_write_cycle","1",,
+"DMAC","CHCR","AL","16","active_high_output","0",,
+"DMAC","CHCR","AL","16","active_low_output","1",,
+"DMAC","CHCR","DM","15-14","destination_address_fixed","0b00",,
+"DMAC","CHCR","DM","15-14","destination_address_incremented","0b01",,
+"DMAC","CHCR","DM","15-14","destination_address_decremented","0b10",,
+"DMAC","CHCR","SM","13-12","source_address_fixed","0b00",,
+"DMAC","CHCR","SM","13-12","source_address_incremented","0b01",,
+"DMAC","CHCR","SM","13-12","source_address_decremented","0b10",,
+"DMAC","CHCR","RS","11-8","resource_select",,"0b1111",
+"DMAC","CHCR","TM","7","cycle_steal_mode","0",,
+"DMAC","CHCR","TM","7","cycle_burst_mode","1",,
+"DMAC","CHCR","TS","6-4","64_bit","0b000",,
+"DMAC","CHCR","TS","6-4","8_bit","0b001",,
+"DMAC","CHCR","TS","6-4","16_bit","0b010",,
+"DMAC","CHCR","TS","6-4","32_bit","0b011",,
+"DMAC","CHCR","TS","6-4","32_byte","0b100",,
+"DMAC","CHCR","IE","2","interrupt_request_not_generated","0",,
+"DMAC","CHCR","IE","2","interrupt_request_generated","1",,
+"DMAC","CHCR","TE","1","transfers_not_completed","0",,
+"DMAC","CHCR","TE","1","transfers_completed","1",,
+"DMAC","CHCR","DE","0","channel_operation_disabled","0",,
+"DMAC","CHCR","DE","0","channel_operation_enabled","1",,
+,,,,,,,
+"DMAC","DMAOR","DDT","15","normal_dma_mode","0",,
+"DMAC","DMAOR","DDT","15","on_demand_data_transfer_mode","1",,
+"DMAC","DMAOR","PR","9-8","ch0_ch1_ch2_ch3","0b00",,
+"DMAC","DMAOR","PR","9-8","ch0_ch2_ch3_ch1","0b01",,
+"DMAC","DMAOR","PR","9-8","ch2_ch0_ch1_ch3","0b10",,
+"DMAC","DMAOR","PR","9-8","round_robin","0b11",,
+"DMAC","DMAOR","AE","2","no_address_error__dma_transfer_enabled","0",,
+"DMAC","DMAOR","AE","2","address_error__dma_transfer_disabled","1",,
+"DMAC","DMAOR","NMIF","1","no_nmi__dma_transfer_enabled","0",,
+"DMAC","DMAOR","NMIF","1","nmi__dma_transfer_disabled","1",,
+"DMAC","DMAOR","DME","0","operation_disabled_on_all_channels","0",,
+"DMAC","DMAOR","DME","0","operation_enabled_on_all_channels","1",,
+,,,,,,,
+"INTC","ICR","NMIL","15","pin_input_level_is_low","0",,
+"INTC","ICR","NMIL","15","pin_input_level_is_high","1",,
+"INTC","ICR","MAI","14","interrupts_enabled_while_nmi_pin_is_low","0",,
+"INTC","ICR","MAI","14","interrupts_disabled_while_nmi_pin_is_low","1",,
+"INTC","ICR","NMIB","9","interrupt_requests_witheld","0",,
+"INTC","ICR","NMIB","9","interrupt_requests_detected","1",,
+"INTC","ICR","NMIE","8","interrupt_on_falling_edge_of_nmi","0",,
+"INTC","ICR","NMIE","8","interrupt_on_rising_edge_of_nmi","1",,
+"INTC","ICR","IRLM","7","level_encoded_interrupt_requests","0",,
+"INTC","ICR","IRLM","7","independent_interrupt_request","1",,
+,,,,,,,
+"INTC","IPRA",,"15-12","TMU0",,"0b1111",
+"INTC","IPRA",,"11-8","TMU1",,"0b1111",
+"INTC","IPRA",,"7-4","TMU2",,"0b1111",
+"INTC","IPRA",,"3-0","RTC",,"0b1111",
+,,,,,,,
+"INTC","IPRB",,"15-12","WDT",,"0b1111",
+"INTC","IPRB",,"11-8","REF",,"0b1111",
+"INTC","IPRB",,"7-4","SCI1",,"0b1111",
+,,,,,,,
+"INTC","IPRC",,"15-12","GPIO",,"0b1111",
+"INTC","IPRC",,"11-8","DMAC",,"0b1111",
+"INTC","IPRC",,"7-4","SCIF",,"0b1111",
+"INTC","IPRC",,"3-0","UDI",,"0b1111",
+,,,,,,,
+"TMU","TOCR","TCOE","0","tclk_is_external_clock_or_input_capture","0",,"Timer Clock Pin Control"
+"TMU","TOCR","TCOE","0","tclk_is_on_chip_rtc","1",,"Timer Clock Pin Control"
+,,,,,,,
+"TMU","TSTR","STR2","2","counter_start","1",,"Counter Start 2"
+"TMU","TSTR","STR1","1","counter_start","1",,"Counter Start 1"
+"TMU","TSTR","STR0","0","counter_start","1",,"Counter Start 0"
+,,,,,,,
+"TMU","TCR0",,"8","UNF","1",,"Underflow Flag"
+"TMU","TCR0",,"5","UNIE","1",,"Underflow Interrupt Control"
+"TMU","TCR0","CKEG","4-3","rising","0b00",,"Clock Edge"
+"TMU","TCR0","CKEG","4-3","falling","0b01",,"Clock Edge"
+"TMU","TCR0","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
+"TMU","TCR0","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","external","0b111",,"Timer Prescaler"
+,,,,,,,
+"TMU","TCR1",,"8","UNF","1",,"Underflow Flag"
+"TMU","TCR1",,"5","UNIE","1",,"Underflow Interrupt Control"
+"TMU","TCR1","CKEG","4-3","rising","0b00",,"Clock Edge"
+"TMU","TCR1","CKEG","4-3","falling","0b01",,"Clock Edge"
+"TMU","TCR1","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
+"TMU","TCR1","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","external","0b111",,"Timer Prescaler"
+,,,,,,,
+"TMU","TCR2",,"9","ICPF","1",,"Input Capture Interrupt Flag"
+"TMU","TCR2",,"8","UNF","1",,"Underflow Flag"
+"TMU","TCR2","ICPE","7-6","disabled","0b00",,"Input Capture Control"
+"TMU","TCR2","ICPE","7-6","enabled","0b10",,"Input Capture Control"
+"TMU","TCR2","ICPE","7-6","enabled_with_interrupts","0b11",,"Input Capture Control"
+"TMU","TCR2",,"5","UNIE","1",,"Underflow Interrupt Control"
+"TMU","TCR2","CKEG","4-3","rising","0b00",,"Clock Edge"
+"TMU","TCR2","CKEG","4-3","falling","0b01",,"Clock Edge"
+"TMU","TCR2","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
+"TMU","TCR2","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","external","0b111",,"Timer Prescaler"
+,,,,,,,
+"SCIF","SCSMR2","CHR","6","8_bit_data","0",,
+"SCIF","SCSMR2","CHR","6","7_bit_data","1",,
+"SCIF","SCSMR2","PE","5","parity_disabled","0",,
+"SCIF","SCSMR2","PE","5","parity_enabled","1",,
+"SCIF","SCSMR2","OE","4","even_parity","0",,
+"SCIF","SCSMR2","OE","4","odd_parity","1",,
+"SCIF","SCSMR2","STOP","3","1_stop_bit","0",,
+"SCIF","SCSMR2","STOP","3","2_stop_bits","1",,
+"SCIF","SCSMR2","CKS","1-0","p_phi_clock","0b00",,
+"SCIF","SCSMR2","CKS","1-0","p_phi_4_clock","0b01",,
+"SCIF","SCSMR2","CKS","1-0","p_phi_16_clock","0b10",,
+"SCIF","SCSMR2","CKS","1-0","p_phi_64_clock","0b11",,
+,,,,,,,
+"SCIF","SCSCR2","TIE","7","transmit_fifo_data_empty_interrupt_disabled","0",,
+"SCIF","SCSCR2","TIE","7","transmit_fifo_data_empty_interrupt_enabled","1",,
+"SCIF","SCSCR2","RIE","6","request_disabled","0",,
+"SCIF","SCSCR2","RIE","6","request_enabled","1",,
+"SCIF","SCSCR2","TE","5","transmission_disabled","0",,
+"SCIF","SCSCR2","TE","5","transmission_enabled","1",,
+"SCIF","SCSCR2","RE","4","reception_disabled","0",,
+"SCIF","SCSCR2","RE","4","reception_enabled","1",,
+"SCIF","SCSCR2","REIE","3","requests_disabled","0",,
+"SCIF","SCSCR2","REIE","3","requests_enabled","1",,
+"SCIF","SCSCR2","CKE1","1","sck2_pin_functions_as_input_pin","0",,
+"SCIF","SCSCR2","CKE1","1","sck2_pin_functions_as_clock_input","1",,
+,,,,,,,
+"SCIF","SCFSR2","PER3_0","15-12","number_of_parity_errors",,,
+"SCIF","SCFSR2","FER3_0","11-8","number_of_framing_errors",,,
+"SCIF","SCFSR2","ER","7","no_framing_error_or_parity_error","0",,
+"SCIF","SCFSR2","ER","7","framing_error_or_parity_error","1",,
+"SCIF","SCFSR2","TEND","6","transmission_in_progress","0",,
+"SCIF","SCFSR2","TEND","6","transmission_has_ended","1",,
+"SCIF","SCFSR2","TDFE","5","transmit_data_bytes_does_exceed_trigger","0",,
+"SCIF","SCFSR2","TDFE","5","transmit_data_bytes_does_not_exceed_trigger","1",,
+"SCIF","SCFSR2","BRK","4","break_not_received","0",,
+"SCIF","SCFSR2","BRK","4","break_received","1",,
+"SCIF","SCFSR2","FER","3","no_framing_error","0",,
+"SCIF","SCFSR2","FER","3","framing_error","1",,
+"SCIF","SCFSR2","PER","2","parity_error","0",,
+"SCIF","SCFSR2","PER","2","no_parity_error","1",,
+"SCIF","SCFSR2","RDF","1","receive_data_bytes_less_than_receive_trigger","0",,
+"SCIF","SCFSR2","RDF","1","receive_data_bytes_greater_than_or_equal_receive_trigger","1",,
+"SCIF","SCFSR2","DR","0","reception_is_in_progress","0",,
+"SCIF","SCFSR2","DR","0","no_further_data_has_arrived","1",,
+,,,,,,,
+"SCIF","SCFCR2","RTRG","7-6","trigger_on_1_byte","0b00",,
+"SCIF","SCFCR2","RTRG","7-6","trigger_on_4_bytes","0b01",,
+"SCIF","SCFCR2","RTRG","7-6","trigger_on_8_bytes","0b10",,
+"SCIF","SCFCR2","RTRG","7-6","trigger_on_14_byte","0b11",,
+"SCIF","SCFCR2","TTRG","5-4","trigger_on_8_bytes","0b00",,
+"SCIF","SCFCR2","TTRG","5-4","trigger_on_4_bytes","0b01",,
+"SCIF","SCFCR2","TTRG","5-4","trigger_on_2_bytes","0b10",,
+"SCIF","SCFCR2","TTRG","5-4","trigger_on_1_bytes","0b11",,
+"SCIF","SCFCR2","MCE","3","modem_signals_disabled","0",,
+"SCIF","SCFCR2","MCE","3","modem_signals_enabled","1",,
+"SCIF","SCFCR2","TFRST","2","reset_operation_disabled","0",,
+"SCIF","SCFCR2","TFRST","2","reset_operation_enabled","1",,
+"SCIF","SCFCR2","RFRST","1","reset_operation_disabled","0",,
+"SCIF","SCFCR2","RFRST","1","reset_operation_enabled","1",,
+"SCIF","SCFCR2","LOOP","0","loopback_test_disabled","0",,
+"SCIF","SCFCR2","LOOP","0","loopback_test_enabled","1",,
+,,,,,,,
+"SCIF","SCFDR2",,"12-8","transmit_data_bytes",,,
+"SCIF","SCFDR2",,"4-0","receive_data_bytes",,,
+,,,,,,,
+"SCIF","SCSPTR2","RTSIO","7","rtsdt_not_output_to_rts2","0",,
+"SCIF","SCSPTR2","RTSIO","7","rtsdt_output_to_rts2","1",,
+"SCIF","SCSPTR2","RTSDT","6","input_output_data_is_low_level","0",,
+"SCIF","SCSPTR2","RTSDT","6","input_output_data_is_high_level","1",,
+"SCIF","SCSPTR2","CTSIO","5","ctsdt_is_not_output_to_cts2","0",,
+"SCIF","SCSPTR2","CTSIO","5","ctsdt_is_output_to_cts2","1",,
+"SCIF","SCSPTR2","CTSDT","4","input_output_data_is_low_level","0",,
+"SCIF","SCSPTR2","CTSDT","4","input_output_data_is_high_level","1",,
+"SCIF","SCSPTR2","SPB2IO","1","spb2dt_is_not_output_to_txd2","0",,
+"SCIF","SCSPTR2","SPB2IO","1","spb2dt_is_output_to_txd2","1",,
+"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_low_level","0",,
+"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_high_level","1",,
+,,,,,,,
+"SCIF","SCLSR2","ORER","0","overrun_error_occured","1",,
+,,,,,,,
+"SH","SR",,"30","md","1",,
+"SH","SR",,"29","rb","1",,
+"SH","SR",,"28","bl","1",,
+"SH","SR",,"15","fd","1",,
+"SH","SR",,"9","m","1",,
+"SH","SR",,"8","q","1",,
+"SH","SR",,"7-4","imask",,"0b1111",
+"SH","SR",,"1","s","1",,
+"SH","SR",,"0","t","1",,
+,,,,,,,
+"SH","FPSCR",,"21","fr","1",,
+"SH","FPSCR",,"20","sz","1",,
+"SH","FPSCR",,"19","pr","1",,
+"SH","FPSCR",,"18","dn","1",,
+"SH","FPSCR","CAUSE","17-12","fpu_error","0b100000",,
+"SH","FPSCR","CAUSE","17-12","invalid_operation","0b010000",,
+"SH","FPSCR","CAUSE","17-12","division_by_zero","0b001000",,
+"SH","FPSCR","CAUSE","17-12","overflow","0b000100",,
+"SH","FPSCR","CAUSE","17-12","underflow","0b000010",,
+"SH","FPSCR","CAUSE","17-12","inexact","0b000001",,
+"SH","FPSCR","ENABLED","11-7","invalid_operation","0b10000",,
+"SH","FPSCR","ENABLED","11-7","division_by_zero","0b01000",,
+"SH","FPSCR","ENABLED","11-7","overflow","0b00100",,
+"SH","FPSCR","ENABLED","11-7","underflow","0b00010",,
+"SH","FPSCR","ENABLED","11-7","inexact","0b00001",,
+"SH","FPSCR","FLAG","6-2","invalid_operation","0b10000",,
+"SH","FPSCR","FLAG","6-2","division_by_zero","0b01000",,
+"SH","FPSCR","FLAG","6-2","overflow","0b00100",,
+"SH","FPSCR","FLAG","6-2","underflow","0b00010",,
+"SH","FPSCR","FLAG","6-2","inexact","0b00001",,
+"SH","FPSCR","RM","1-0","round_to_nearest","0b00",,
+"SH","FPSCR","RM","1-0","round_to_zero","0b01",,
+,,,,,,,
+"UBC","BAMRA","BAMA","3,1,0","all_bara_bits_are_included_in_break_conditions","0b0000",,
+"UBC","BAMRA","BAMA","3,1,0","lower_10_bits_of_bara_are_not_included_in_break_conditions","0b0001",,
+"UBC","BAMRA","BAMA","3,1,0","lower_12_bits_of_bara_are_not_included_in_break_conditions","0b0010",,
+"UBC","BAMRA","BAMA","3,1,0","all_bara_bits_are_not_included_in_break_conditions","0b0011",,
+"UBC","BAMRA","BAMA","3,1,0","lower_16_bits_of_bara_are_not_included_in_break_conditions","0b1000",,
+"UBC","BAMRA","BAMA","3,1,0","lower_20_bits_of_bara_are_not_included_in_break_conditions","0b1001",,
+"UBC","BAMRA","BASMA","2","all_basra_bits_are_included_in_break_conditions","0",,
+"UBC","BAMRA","BASMA","2","no_basra_bits_are_included_in_break_conditions","1",,
+,,,,,,,
+"UBC","BBRA","SZA","6,1,0","operand_size_is_not_included_in_break_conditions","0b00",,
+"UBC","BBRA","SZA","6,1,0","byte_access_is_used_as_break_condition","0b01",,
+"UBC","BBRA","SZA","6,1,0","word_access_is_used_as_break_condition","0b10",,
+"UBC","BBRA","SZA","6,1,0","longword_access_is_used_as_break_condition","0b11",,
+"UBC","BBRA","SZA","6,1,0","quadword_access_is_used_as_break_condition","0b1000000",,
+"UBC","BBRA","IDA","5-4","condition_comparison_is_not_performed","0b00",,
+"UBC","BBRA","IDA","5-4","instruction_access_cycle_is_used_as_break_condition","0b01",,
+"UBC","BBRA","IDA","5-4","operand_access_cycle_is_used_as_break_condition","0b10",,
+"UBC","BBRA","IDA","5-4","instruction_access_cycle_or_operand_access_cycle_is_used_as_break_condition","0b11",,
+"UBC","BBRA","RWA","3-2","condition_comparison_is_not_performed","0b00",,
+"UBC","BBRA","RWA","3-2","read_cycle_is_used_as_break_condition","0b01",,
+"UBC","BBRA","RWA","3-2","write_cycle_is_used_as_break_condition","0b10",,
+"UBC","BBRA","RWA","3-2","read_cycle_or_write_cycle_is_used_as_break_condition","0b11",,
+,,,,,,,
+"UBC","BRCR","CMFA","15","channel_a_break_condition_is_not_matched","0",,
+"UBC","BRCR","CMFA","15","channel_a_break_condition_match_has_occured","1",,
+"UBC","BRCR","CMFB","14","channel_b_break_condition_is_not_matched","0",,
+"UBC","BRCR","CMFB","14","channel_b_break_condition_match_has_occured","1",,
+"UBC","BRCR","PCBA","10","channel_a_pc_break_is_effected_before_instruction_execution","0",,
+"UBC","BRCR","PCBA","10","channel_a_pc_break_is_effected_after_instruction_execution","1",,
+"UBC","BRCR","DBEB","7","data_bus_condition_is_not_included_in_channel_b_conditions","0",,
+"UBC","BRCR","DBEB","7","data_bus_condition_is_included_in_channel_b_conditions","1",,
+"UBC","BRCR","PCBB","6","channel_b_pc_break_is_effected_before_instruction_execution","0",,
+"UBC","BRCR","PCBB","6","channel_b_pc_break_is_effected_after_instruction_execution","1",,
+"UBC","BRCR","SEQ","3","channel_a_and_b_comparison_are_performed_as_independent_condition","0",,
+"UBC","BRCR","SEQ","3","channel_a_and_b_comparison_are_performed_as_sequential_condition","1",,
+"UBC","BRCR","UBDE","0","user_break_debug_function_is_not_used","0",,
+"UBC","BRCR","UBDE","0","user_break_debug_function_is_used","1",,

dreamcast2/regs/systembus/systembus.csv

@@ -0,0 +1,163 @@
+"block","address","size","name","r/w","description"
+"SYSTEMBUS","000","4","C2DSTAT","RW","CH2-DMA destination address"
+"SYSTEMBUS","004","4","C2DLEN","RW","CH2-DMA length"
+"SYSTEMBUS","008","4","C2DST","RW","CH2-DMA start"
+,,,,,
+"SYSTEMBUS","010","4","SDSTAW","RW","Sort-DMA start link table address"
+"SYSTEMBUS","014","4","SDBAAW","RW","Sort-DMA link base address"
+"SYSTEMBUS","018","4","SDWLT","RW","Sort-DMA link address bit width"
+"SYSTEMBUS","01c","4","SDLAS","RW","Sort-DMA link address shift control"
+"SYSTEMBUS","020","4","SDST","RW","Sort-DMA start"
+,,,,,
+"SYSTEMBUS","040","4","DBREQM","RW","DBREQ# signal mask control"
+"SYSTEMBUS","044","4","BAVLWC","RW","BAVL# signal wait count"
+"SYSTEMBUS","048","4","C2DPYRC","RW","DMA (TA/Root Bus) priority count"
+"SYSTEMBUS","04c","4","DMAXL","RW","CH2-DMA maximum burst length"
+,,,,,
+"SYSTEMBUS","080","4","TFREM","R","TA FIFO remaining amount"
+"SYSTEMBUS","084","4","LMMODE0","RW","Via TA texture memory bus select 0"
+"SYSTEMBUS","088","4","LMMODE1","RW","Via TA texture memory bus select 1"
+"SYSTEMBUS","08c","4","FFST","R","FIFO status"
+"SYSTEMBUS","090","4","SFRES","W","System reset"
+,,,,,
+"SYSTEMBUS","09c","4","SBREV","R","System bus revision number"
+"SYSTEMBUS","0a0","4","RBSPLT","RW","SH4 Root Bus split enable"
+,,,,,
+"SYSTEMBUS","100","4","ISTNRM","RW","Normal interrupt status"
+"SYSTEMBUS","104","4","ISTEXT","R","External interrupt status"
+"SYSTEMBUS","108","4","ISTERR","RW","Error interrupt status"
+,,,,,
+"SYSTEMBUS","110","4","IML2NRM","RW","Level 2 normal interrupt mask"
+"SYSTEMBUS","114","4","IML2EXT","RW","Level 2 external interrupt mask"
+"SYSTEMBUS","118","4","IML2ERR","RW","Level 2 error interrupt mask"
+,,,,,
+"SYSTEMBUS","120","4","IML4NRM","RW","Level 4 normal interrupt mask"
+"SYSTEMBUS","124","4","IML4EXT","RW","Level 4 external interrupt mask"
+"SYSTEMBUS","128","4","IML4ERR","RW","Level 4 error interrupt mask"
+,,,,,
+"SYSTEMBUS","130","4","IML6NRM","RW","Level 6 normal interrupt mask"
+"SYSTEMBUS","134","4","IML6EXT","RW","Level 6 external interrupt mask"
+"SYSTEMBUS","138","4","IML6ERR","RW","Level 6 error interrupt mask"
+,,,,,
+"SYSTEMBUS","140","4","PDTNRM","RW","Normal interrupt PVR-DMA startup mask"
+"SYSTEMBUS","144","4","PDTEXT","RW","External interrupt PVR-DMA startup mask"
+,,,,,
+"SYSTEMBUS","150","4","G2DTNRM","RW","Normal interrupt G2-DMA startup mask"
+"SYSTEMBUS","154","4","G2DTEXT","RW","External interrupt G2-DMA startup mask"
+,,,,,
+"MAPLE_IF","04","4","MDSTAR","RW","Maple-DMA command table address"
+,,,,,
+"MAPLE_IF","10","4","MDTSEL","RW","Maple-DMA trigger select"
+"MAPLE_IF","14","4","MDEN","RW","Maple-DMA enable"
+"MAPLE_IF","18","4","MDST","RW","Maple-DMA start"
+,,,,,
+"MAPLE_IF","80","4","MSYS","RW","Maple system control"
+"MAPLE_IF","84","4","MST","R","Maple status"
+"MAPLE_IF","88","4","MSHTCL","W","Maple-DMA hard trigger clear"
+"MAPLE_IF","8c","4","MDAPRO","W","Maple-DMA address range"
+,,,,,
+"MAPLE_IF","e8","4","MMSEL","RW","Maple MSP selection"
+,,,,,
+"MAPLE_IF","f4","4","MTXDAD","R","Maple TXD address counter"
+"MAPLE_IF","f8","4","MRXDAD","R","Maple RXD address counter"
+"MAPLE_IF","fc","4","MRXDBD","R","Maple RXD address base"
+,,,,,
+"G1_IF","04","4","GDSTAR","RW","GD-DMA start address"
+"G1_IF","08","4","GDLEN","RW","GD-DMA length"
+"G1_IF","0c","4","GDDIR","RW","GD-DMA direction"
+,,,,,
+"G1_IF","14","4","GDEN","RW","GD-DMA enable"
+"G1_IF","18","4","GDST","RW","GD-DMA start"
+,,,,,
+"G1_IF","80","4","G1RRC","W","System ROM read access timing"
+"G1_IF","84","4","G1RWC","W","System ROM write access timing"
+"G1_IF","88","4","G1FRC","W","Flash ROM read access timing"
+"G1_IF","8c","4","G1FWC","W","Flash ROM write access timing"
+"G1_IF","90","4","G1CRC","W","GD PIO read access timing"
+"G1_IF","94","4","G1CWC","W","GD PIO write access timing"
+,,,,,
+"G1_IF","a0","4","G1GDRC","W","GD-DMA read access timing"
+"G1_IF","a4","4","G1GDWC","W","GD-DMA write access timing"
+,,,,,
+"G1_IF","b0","4","G1SYSM","R","System mode"
+"G1_IF","b4","4","G1CRDYC","W","G1IORDY signal control"
+"G1_IF","b8","4","GDAPRO","W","GD-DMA address range"
+,,,,,
+"G1_IF","e4","4","GDUNLOCK","W","(undocumented unlock register)"
+"G1_IF","f4","4","GDSTARD","R","GD-DMA address count (on Root Bus)"
+"G1_IF","f8","4","GDLEND","R","GD-DMA transfer counter"
+,,,,,
+"G2_IF","00","4","ADSTAG","RW","ACIA:G2-DMA G2 start address"
+"G2_IF","04","4","ADSTAR","RW","ACIA:G2-DMA system memory start address"
+"G2_IF","08","4","ADLEN","RW","ACIA:G2-DMA length"
+"G2_IF","0c","4","ADDIR","RW","ACIA:G2-DMA direction"
+"G2_IF","10","4","ADTSEL","RW","ACIA:G2-DMA trigger select"
+"G2_IF","14","4","ADEN","RW","ACIA:G2-DMA enable"
+"G2_IF","18","4","ADST","RW","ACIA:G2-DMA start"
+"G2_IF","1c","4","ADSUSP","RW","ACIA:G2-DMA suspend"
+,,,,,
+"G2_IF","20","4","E1STAG","RW","Ext1:G2-DMA start address"
+"G2_IF","24","4","E1STAR","RW","Ext1:G2-DMA system memory start address"
+"G2_IF","28","4","E1LEN","RW","Ext1:G2-DMA length"
+"G2_IF","2c","4","E1DIR","RW","Ext1:G2-DMA direction"
+"G2_IF","30","4","E1TSEL","RW","Ext1:G2-DMA trigger select"
+"G2_IF","34","4","E1EN","RW","Ext1:G2-DMA enable"
+"G2_IF","38","4","E1ST","RW","Ext1:G2-DMA start"
+"G2_IF","3c","4","E1SUSP","RW","Ext1:G2-DMA suspend"
+,,,,,
+"G2_IF","40","4","E2STAG","RW","Ext2:G2-DMA start address"
+"G2_IF","44","4","E2STAR","RW","Ext2:G2-DMA system memory start address"
+"G2_IF","48","4","E2LEN","RW","Ext2:G2-DMA length"
+"G2_IF","4c","4","E2DIR","RW","Ext2:G2-DMA direction"
+"G2_IF","50","4","E2TSEL","RW","Ext2:G2-DMA trigger select"
+"G2_IF","54","4","E2EN","RW","Ext2:G2-DMA enable"
+"G2_IF","58","4","E2ST","RW","Ext2:G2-DMA start"
+"G2_IF","5c","4","E2SUSP","RW","Ext2:G2-DMA suspend"
+,,,,,
+"G2_IF","60","4","DDSTAG","RW","Dev:G2-DMA start address"
+"G2_IF","64","4","DDSTAR","RW","Dev:G2-DMA system memory start address"
+"G2_IF","68","4","DDLEN","RW","Dev:G2-DMA length"
+"G2_IF","6c","4","DDDIR","RW","Dev:G2-DMA direction"
+"G2_IF","70","4","DDTSEL","RW","Dev:G2-DMA trigger select"
+"G2_IF","74","4","DDEN","RW","Dev:G2-DMA enable"
+"G2_IF","78","4","DDST","RW","Dev:G2-DMA start"
+"G2_IF","7c","4","DDSUSP","RW","Dev:G2-DMA suspend"
+,,,,,
+"G2_IF","80","4","G2ID","R","G2 bus version"
+,,,,,
+"G2_IF","90","4","G2DSTO","RW","G2/DS timeout"
+"G2_IF","94","4","G2TRTO","RW","G2/TR timeout"
+"G2_IF","98","4","G2MDMTO","RW","Modem unit wait timeout"
+"G2_IF","9c","4","G2MDMW","RW","Modem unit wait time"
+,,,,,
+"G2_IF","bc","4","G2APRO","W","G2-DMA address range"
+,,,,,
+"G2_IF","c0","4","ADSTAGD","R","AICA-DMA address counter (on AICA)"
+"G2_IF","c4","4","ADSTARD","R","AICA-DMA address counter (on root bus)"
+"G2_IF","c8","4","ADLEND","R","AICA-DMA transfer counter"
+,,,,,
+"G2_IF","d0","4","E1STAGD","R","Ext-DMA1 address counter (on Ext)"
+"G2_IF","d4","4","E1STARD","R","Ext-DMA1 address counter (on root bus)"
+"G2_IF","d8","4","E1LEND","R","Ext-DMA1 transfer counter"
+,,,,,
+"G2_IF","e0","4","E2STAGD","R","Ext-DMA2 address counter (on Ext)"
+"G2_IF","e4","4","E2STARD","R","Ext-DMA2 address counter (on root bus)"
+"G2_IF","e8","4","E2LEND","R","Ext-DMA2 transfer counter"
+,,,,,
+"G2_IF","f0","4","DDSTAGD","R","Dev-DMA address counter (on Dev)"
+"G2_IF","f4","4","DDSTARD","R","Dev-DMA address counter (on root bus)"
+"G2_IF","f8","4","DDLEND","R","Dev-DMA transfer counter"
+,,,,,
+"PVR_IF","00","4","PDSTAP","RW","PVR-DMA start address"
+"PVR_IF","04","4","PDSTAR","RW","PVR-DMA system memory start address"
+"PVR_IF","08","4","PDLEN","RW","PVR-DMA length"
+"PVR_IF","0c","4","PDDIR","RW","PVR-DMA direction"
+"PVR_IF","10","4","PDTSEL","RW","PVR-DMA trigger select"
+"PVR_IF","14","4","PDEN","RW","PVR-DMA enable"
+"PVR_IF","18","4","PDST","RW","PVR-DMA start"
+,,,,,
+"PVR_IF","80","4","PDAPRO","W","PVR-DMA address range"
+,,,,,
+"PVR_IF","f0","4","PDSTAPD","R","PVR-DMA address counter (on Ext)"
+"PVR_IF","f4","4","PDSTARD","R","PVR-DMA address counter (on root bus)"
+"PVR_IF","f8","4","PDLEND","R","PVR-DMA transfer counter"

dreamcast2/sh7091/sh7091.hpp

@@ -0,0 +1,379 @@
+#pragma once
+
+#include <cstdint>
+#include <cstddef>
+
+#include "type.hpp"
+
+struct ccn_reg {
+  reg32 PTEH;                /* Page table entry high register */
+  reg32 PTEL;                /* Page table entry low register */
+  reg32 TTB;                 /* Translation table base register */
+  reg32 TEA;                 /* TLB exception address register */
+  reg32 MMUCR;               /* MMU control register */
+  reg8  BASRA;               /* Break ASID register A */
+  reg8  _pad0[3];
+  reg8  BASRB;               /* Break ASID register B */
+  reg8  _pad1[3];
+  reg32 CCR;                 /* Cache control register */
+  reg32 TRA;                 /* TRAPA exception register */
+  reg32 EXPEVT;              /* Exception event register */
+  reg32 INTEVT;              /* Interrupt event register */
+  reg8  _pad2[8];
+  reg32 PTEA;                /* Page table entry assistance register */
+  reg32 QACR0;               /* Queue address control register 0 */
+  reg32 QACR1;               /* Queue address control register 1 */
+};
+
+static_assert((offsetof (struct ccn_reg, PTEH)) == 0x0);
+static_assert((offsetof (struct ccn_reg, PTEL)) == 0x4);
+static_assert((offsetof (struct ccn_reg, TTB)) == 0x8);
+static_assert((offsetof (struct ccn_reg, TEA)) == 0xc);
+static_assert((offsetof (struct ccn_reg, MMUCR)) == 0x10);
+static_assert((offsetof (struct ccn_reg, BASRA)) == 0x14);
+static_assert((offsetof (struct ccn_reg, BASRB)) == 0x18);
+static_assert((offsetof (struct ccn_reg, CCR)) == 0x1c);
+static_assert((offsetof (struct ccn_reg, TRA)) == 0x20);
+static_assert((offsetof (struct ccn_reg, EXPEVT)) == 0x24);
+static_assert((offsetof (struct ccn_reg, INTEVT)) == 0x28);
+static_assert((offsetof (struct ccn_reg, PTEA)) == 0x34);
+static_assert((offsetof (struct ccn_reg, QACR0)) == 0x38);
+static_assert((offsetof (struct ccn_reg, QACR1)) == 0x3c);
+
+struct ubc_reg {
+  reg32 BARA;                /* Break address register A */
+  reg8  BAMRA;               /* Break address mask register A */
+  reg8  _pad0[3];
+  reg16 BBRA;                /* Break bus cycle register A */
+  reg8  _pad1[2];
+  reg32 BARB;                /* Break address register B */
+  reg8  BAMRB;               /* Break address mask register B */
+  reg8  _pad2[3];
+  reg16 BBRB;                /* Break bus cycle register B */
+  reg8  _pad3[2];
+  reg32 BDRB;                /* Break data register B */
+  reg32 BDMRB;               /* Break data mask register B */
+  reg16 BRCR;                /* Break control register */
+};
+
+static_assert((offsetof (struct ubc_reg, BARA)) == 0x0);
+static_assert((offsetof (struct ubc_reg, BAMRA)) == 0x4);
+static_assert((offsetof (struct ubc_reg, BBRA)) == 0x8);
+static_assert((offsetof (struct ubc_reg, BARB)) == 0xc);
+static_assert((offsetof (struct ubc_reg, BAMRB)) == 0x10);
+static_assert((offsetof (struct ubc_reg, BBRB)) == 0x14);
+static_assert((offsetof (struct ubc_reg, BDRB)) == 0x18);
+static_assert((offsetof (struct ubc_reg, BDMRB)) == 0x1c);
+static_assert((offsetof (struct ubc_reg, BRCR)) == 0x20);
+
+struct bsc_reg {
+  reg32 BCR1;                /* Bus control register 1 */
+  reg16 BCR2;                /* Bus control register 2 */
+  reg8  _pad0[2];
+  reg32 WCR1;                /* Wait state control register 1 */
+  reg32 WCR2;                /* Wait state control register 2 */
+  reg32 WCR3;                /* Wait state control register 3 */
+  reg32 MCR;                 /* Memory control register */
+  reg16 PCR;                 /* PCMCIA control register */
+  reg8  _pad1[2];
+  reg16 RTCSR;               /* Refresh timer control/status register */
+  reg8  _pad2[2];
+  reg16 RTCNT;               /* Refresh timer counter */
+  reg8  _pad3[2];
+  reg16 RTCOR;               /* Refresh timer constant counter */
+  reg8  _pad4[2];
+  reg16 RFCR;                /* Refresh count register */
+  reg8  _pad5[2];
+  reg32 PCTRA;               /* Port control register A */
+  reg16 PDTRA;               /* Port data register A */
+  reg8  _pad6[14];
+  reg32 PCTRB;               /* Port control register B */
+  reg16 PDTRB;               /* Port data register B */
+  reg8  _pad7[2];
+  reg16 GPIOIC;              /* GPIO interrupt control register */
+  reg8  _pad8[1048502];
+  reg32 SDMR2[16384];        /* Synchronous DRAM mode registers */
+  reg8  _pad9[196608];
+  reg32 SDMR3[16384];        /* Synchronous DRAM mode registers */
+};
+
+static_assert((offsetof (struct bsc_reg, BCR1)) == 0x0);
+static_assert((offsetof (struct bsc_reg, BCR2)) == 0x4);
+static_assert((offsetof (struct bsc_reg, WCR1)) == 0x8);
+static_assert((offsetof (struct bsc_reg, WCR2)) == 0xc);
+static_assert((offsetof (struct bsc_reg, WCR3)) == 0x10);
+static_assert((offsetof (struct bsc_reg, MCR)) == 0x14);
+static_assert((offsetof (struct bsc_reg, PCR)) == 0x18);
+static_assert((offsetof (struct bsc_reg, RTCSR)) == 0x1c);
+static_assert((offsetof (struct bsc_reg, RTCNT)) == 0x20);
+static_assert((offsetof (struct bsc_reg, RTCOR)) == 0x24);
+static_assert((offsetof (struct bsc_reg, RFCR)) == 0x28);
+static_assert((offsetof (struct bsc_reg, PCTRA)) == 0x2c);
+static_assert((offsetof (struct bsc_reg, PDTRA)) == 0x30);
+static_assert((offsetof (struct bsc_reg, PCTRB)) == 0x40);
+static_assert((offsetof (struct bsc_reg, PDTRB)) == 0x44);
+static_assert((offsetof (struct bsc_reg, GPIOIC)) == 0x48);
+static_assert((offsetof (struct bsc_reg, SDMR2)) == 0x100000);
+static_assert((offsetof (struct bsc_reg, SDMR3)) == 0x140000);
+
+struct dmac_reg {
+  reg32 SAR0;                /* DMA source address register 0 */
+  reg32 DAR0;                /* DMA destination address register 0 */
+  reg32 DMATCR0;             /* DMA transfer count register 0 */
+  reg32 CHCR0;               /* DMA control register 0 */
+  reg32 SAR1;                /* DMA source address register 1 */
+  reg32 DAR1;                /* DMA destination address register 1 */
+  reg32 DMATCR1;             /* DMA transfer count register 1 */
+  reg32 CHCR1;               /* DMA control register 1 */
+  reg32 SAR2;                /* DMA source address register 2 */
+  reg32 DAR2;                /* DMA destination address register 2 */
+  reg32 DMATCR2;             /* DMA transfer count register 2 */
+  reg32 CHCR2;               /* DMA control register 2 */
+  reg32 SAR3;                /* DMA source address register 3 */
+  reg32 DAR3;                /* DMA destination address register 3 */
+  reg32 DMATCR3;             /* DMA transfer count register 3 */
+  reg32 CHCR3;               /* DMA control register 3 */
+  reg32 DMAOR;               /* DMA operation register */
+};
+
+static_assert((offsetof (struct dmac_reg, SAR0)) == 0x0);
+static_assert((offsetof (struct dmac_reg, DAR0)) == 0x4);
+static_assert((offsetof (struct dmac_reg, DMATCR0)) == 0x8);
+static_assert((offsetof (struct dmac_reg, CHCR0)) == 0xc);
+static_assert((offsetof (struct dmac_reg, SAR1)) == 0x10);
+static_assert((offsetof (struct dmac_reg, DAR1)) == 0x14);
+static_assert((offsetof (struct dmac_reg, DMATCR1)) == 0x18);
+static_assert((offsetof (struct dmac_reg, CHCR1)) == 0x1c);
+static_assert((offsetof (struct dmac_reg, SAR2)) == 0x20);
+static_assert((offsetof (struct dmac_reg, DAR2)) == 0x24);
+static_assert((offsetof (struct dmac_reg, DMATCR2)) == 0x28);
+static_assert((offsetof (struct dmac_reg, CHCR2)) == 0x2c);
+static_assert((offsetof (struct dmac_reg, SAR3)) == 0x30);
+static_assert((offsetof (struct dmac_reg, DAR3)) == 0x34);
+static_assert((offsetof (struct dmac_reg, DMATCR3)) == 0x38);
+static_assert((offsetof (struct dmac_reg, CHCR3)) == 0x3c);
+static_assert((offsetof (struct dmac_reg, DMAOR)) == 0x40);
+
+struct cpg_reg {
+  reg16 FRQCR;               /* Frequency control register */
+  reg8  _pad0[2];
+  reg8  STBCR;               /* Standby control register */
+  reg8  _pad1[3];
+  reg16 WTCNT;               /* Watchdog timer counter */
+  reg8  _pad2[2];
+  reg16 WTCSR;               /* Watchdog timer control/status register */
+  reg8  _pad3[2];
+  reg8  STBCR2;              /* Standby control register 2 */
+};
+
+static_assert((offsetof (struct cpg_reg, FRQCR)) == 0x0);
+static_assert((offsetof (struct cpg_reg, STBCR)) == 0x4);
+static_assert((offsetof (struct cpg_reg, WTCNT)) == 0x8);
+static_assert((offsetof (struct cpg_reg, WTCSR)) == 0xc);
+static_assert((offsetof (struct cpg_reg, STBCR2)) == 0x10);
+
+struct rtc_reg {
+  reg8  R64CNT;              /* 64 Hz counter */
+  reg8  _pad0[3];
+  reg8  RSECCNT;             /* Second counter */
+  reg8  _pad1[3];
+  reg8  RMINCNT;             /* Minute counter */
+  reg8  _pad2[3];
+  reg8  RHRCNT;              /* Hour counter */
+  reg8  _pad3[3];
+  reg8  RWKCNT;              /* Day-of-week counter */
+  reg8  _pad4[3];
+  reg8  RDAYCNT;             /* Day counter */
+  reg8  _pad5[3];
+  reg8  RMONCNT;             /* Month counter */
+  reg8  _pad6[3];
+  reg16 RYRCNT;              /* Year counter */
+  reg8  _pad7[2];
+  reg8  RSECAR;              /* Second alarm register */
+  reg8  _pad8[3];
+  reg8  RMINAR;              /* Minute alarm register */
+  reg8  _pad9[3];
+  reg8  RHRAR;               /* Hour alarm register */
+  reg8  _pad10[3];
+  reg8  RWKAR;               /* Day-of-week alarm register */
+  reg8  _pad11[3];
+  reg8  RDAYAR;              /* Day alarm register */
+  reg8  _pad12[3];
+  reg8  RMONAR;              /* Month alarm register */
+  reg8  _pad13[3];
+  reg8  RCR1;                /* RTC control register 1 */
+  reg8  _pad14[3];
+  reg8  RCR2;                /* RTC control register 2 */
+};
+
+static_assert((offsetof (struct rtc_reg, R64CNT)) == 0x0);
+static_assert((offsetof (struct rtc_reg, RSECCNT)) == 0x4);
+static_assert((offsetof (struct rtc_reg, RMINCNT)) == 0x8);
+static_assert((offsetof (struct rtc_reg, RHRCNT)) == 0xc);
+static_assert((offsetof (struct rtc_reg, RWKCNT)) == 0x10);
+static_assert((offsetof (struct rtc_reg, RDAYCNT)) == 0x14);
+static_assert((offsetof (struct rtc_reg, RMONCNT)) == 0x18);
+static_assert((offsetof (struct rtc_reg, RYRCNT)) == 0x1c);
+static_assert((offsetof (struct rtc_reg, RSECAR)) == 0x20);
+static_assert((offsetof (struct rtc_reg, RMINAR)) == 0x24);
+static_assert((offsetof (struct rtc_reg, RHRAR)) == 0x28);
+static_assert((offsetof (struct rtc_reg, RWKAR)) == 0x2c);
+static_assert((offsetof (struct rtc_reg, RDAYAR)) == 0x30);
+static_assert((offsetof (struct rtc_reg, RMONAR)) == 0x34);
+static_assert((offsetof (struct rtc_reg, RCR1)) == 0x38);
+static_assert((offsetof (struct rtc_reg, RCR2)) == 0x3c);
+
+struct intc_reg {
+  reg16 ICR;                 /* Interrupt control register */
+  reg8  _pad0[2];
+  reg16 IPRA;                /* Interrupt priority register A */
+  reg8  _pad1[2];
+  reg16 IPRB;                /* Interrupt priority register B */
+  reg8  _pad2[2];
+  reg16 IPRC;                /* Interrupt priority register C */
+};
+
+static_assert((offsetof (struct intc_reg, ICR)) == 0x0);
+static_assert((offsetof (struct intc_reg, IPRA)) == 0x4);
+static_assert((offsetof (struct intc_reg, IPRB)) == 0x8);
+static_assert((offsetof (struct intc_reg, IPRC)) == 0xc);
+
+struct tmu_reg {
+  reg8  TOCR;                /* Timer output control register */
+  reg8  _pad0[3];
+  reg8  TSTR;                /* Timer start register */
+  reg8  _pad1[3];
+  reg32 TCOR0;               /* Timer constant register 0 */
+  reg32 TCNT0;               /* Timer counter 0 */
+  reg16 TCR0;                /* Timer control register 0 */
+  reg8  _pad2[2];
+  reg32 TCOR1;               /* Timer constant register 1 */
+  reg32 TCNT1;               /* Timer counter 1 */
+  reg16 TCR1;                /* Timer control register 1 */
+  reg8  _pad3[2];
+  reg32 TCOR2;               /* Timer constant register 2 */
+  reg32 TCNT2;               /* Timer counter 2 */
+  reg16 TCR2;                /* Timer control register 2 */
+  reg8  _pad4[2];
+  reg32 TCPR2;               /* Timer input capture register 2 */
+};
+
+static_assert((offsetof (struct tmu_reg, TOCR)) == 0x0);
+static_assert((offsetof (struct tmu_reg, TSTR)) == 0x4);
+static_assert((offsetof (struct tmu_reg, TCOR0)) == 0x8);
+static_assert((offsetof (struct tmu_reg, TCNT0)) == 0xc);
+static_assert((offsetof (struct tmu_reg, TCR0)) == 0x10);
+static_assert((offsetof (struct tmu_reg, TCOR1)) == 0x14);
+static_assert((offsetof (struct tmu_reg, TCNT1)) == 0x18);
+static_assert((offsetof (struct tmu_reg, TCR1)) == 0x1c);
+static_assert((offsetof (struct tmu_reg, TCOR2)) == 0x20);
+static_assert((offsetof (struct tmu_reg, TCNT2)) == 0x24);
+static_assert((offsetof (struct tmu_reg, TCR2)) == 0x28);
+static_assert((offsetof (struct tmu_reg, TCPR2)) == 0x2c);
+
+struct sci_reg {
+  reg8  SCSMR1;              /* Serial mode register 1 */
+  reg8  _pad0[3];
+  reg8  SCBRR1;              /* Bit rate register 1 */
+  reg8  _pad1[3];
+  reg8  SCSCR1;              /* Serial control register 1 */
+  reg8  _pad2[3];
+  reg8  SCTDR1;              /* Transmit data register 1 */
+  reg8  _pad3[3];
+  reg8  SCSSR1;              /* Serial status register 1 */
+  reg8  _pad4[3];
+  reg8  SCRDR1;              /* Receive data register 1 */
+  reg8  _pad5[3];
+  reg8  SCSCMR1;             /* Smart card mode register 1 */
+  reg8  _pad6[3];
+  reg8  SCSPTR1;             /* Serial port register */
+};
+
+static_assert((offsetof (struct sci_reg, SCSMR1)) == 0x0);
+static_assert((offsetof (struct sci_reg, SCBRR1)) == 0x4);
+static_assert((offsetof (struct sci_reg, SCSCR1)) == 0x8);
+static_assert((offsetof (struct sci_reg, SCTDR1)) == 0xc);
+static_assert((offsetof (struct sci_reg, SCSSR1)) == 0x10);
+static_assert((offsetof (struct sci_reg, SCRDR1)) == 0x14);
+static_assert((offsetof (struct sci_reg, SCSCMR1)) == 0x18);
+static_assert((offsetof (struct sci_reg, SCSPTR1)) == 0x1c);
+
+struct scif_reg {
+  reg16 SCSMR2;              /* Serial mode register 2 */
+  reg8  _pad0[2];
+  reg8  SCBRR2;              /* Bit rate register 2 */
+  reg8  _pad1[3];
+  reg16 SCSCR2;              /* Serial control register 2 */
+  reg8  _pad2[2];
+  reg8  SCFTDR2;             /* Transmit FIFO data register 2 */
+  reg8  _pad3[3];
+  reg16 SCFSR2;              /* Serial status register 2 */
+  reg8  _pad4[2];
+  reg8  SCFRDR2;             /* Receive FIFO data register 2 */
+  reg8  _pad5[3];
+  reg16 SCFCR2;              /* FIFO control register */
+  reg8  _pad6[2];
+  reg16 SCFDR2;              /* FIFO data count register */
+  reg8  _pad7[2];
+  reg16 SCSPTR2;             /* Serial port register 2 */
+  reg8  _pad8[2];
+  reg16 SCLSR2;              /* Line status register 2 */
+};
+
+static_assert((offsetof (struct scif_reg, SCSMR2)) == 0x0);
+static_assert((offsetof (struct scif_reg, SCBRR2)) == 0x4);
+static_assert((offsetof (struct scif_reg, SCSCR2)) == 0x8);
+static_assert((offsetof (struct scif_reg, SCFTDR2)) == 0xc);
+static_assert((offsetof (struct scif_reg, SCFSR2)) == 0x10);
+static_assert((offsetof (struct scif_reg, SCFRDR2)) == 0x14);
+static_assert((offsetof (struct scif_reg, SCFCR2)) == 0x18);
+static_assert((offsetof (struct scif_reg, SCFDR2)) == 0x1c);
+static_assert((offsetof (struct scif_reg, SCSPTR2)) == 0x20);
+static_assert((offsetof (struct scif_reg, SCLSR2)) == 0x24);
+
+struct udi_reg {
+  reg16 SDIR;                /* Instruction register */
+  reg8  _pad0[6];
+  reg32 SDDR;                /* Data register */
+};
+
+static_assert((offsetof (struct udi_reg, SDIR)) == 0x0);
+static_assert((offsetof (struct udi_reg, SDDR)) == 0x8);
+
+struct sh7091_reg {
+  struct ccn_reg CCN;
+  reg8  _pad0[0x200000 - (sizeof (struct ccn_reg))];
+  struct ubc_reg UBC;
+  reg8  _pad1[0x600000 - (sizeof (struct ubc_reg))];
+  struct bsc_reg BSC;
+  reg8  _pad2[0x200000 - (sizeof (struct bsc_reg))];
+  struct dmac_reg DMAC;
+  reg8  _pad3[0x200000 - (sizeof (struct dmac_reg))];
+  struct cpg_reg CPG;
+  reg8  _pad4[0x80000 - (sizeof (struct cpg_reg))];
+  struct rtc_reg RTC;
+  reg8  _pad5[0x80000 - (sizeof (struct rtc_reg))];
+  struct intc_reg INTC;
+  reg8  _pad6[0x80000 - (sizeof (struct intc_reg))];
+  struct tmu_reg TMU;
+  reg8  _pad7[0x80000 - (sizeof (struct tmu_reg))];
+  struct sci_reg SCI;
+  reg8  _pad8[0x80000 - (sizeof (struct sci_reg))];
+  struct scif_reg SCIF;
+  reg8  _pad9[0x80000 - (sizeof (struct scif_reg))];
+  struct udi_reg UDI;
+};
+
+static_assert((offsetof (struct sh7091_reg, CCN)) == 0x0);
+static_assert((offsetof (struct sh7091_reg, UBC)) == 0x200000);
+static_assert((offsetof (struct sh7091_reg, BSC)) == 0x800000);
+static_assert((offsetof (struct sh7091_reg, DMAC)) == 0xa00000);
+static_assert((offsetof (struct sh7091_reg, CPG)) == 0xc00000);
+static_assert((offsetof (struct sh7091_reg, RTC)) == 0xc80000);
+static_assert((offsetof (struct sh7091_reg, INTC)) == 0xd00000);
+static_assert((offsetof (struct sh7091_reg, TMU)) == 0xd80000);
+static_assert((offsetof (struct sh7091_reg, SCI)) == 0xe00000);
+static_assert((offsetof (struct sh7091_reg, SCIF)) == 0xe80000);
+static_assert((offsetof (struct sh7091_reg, UDI)) == 0xf00000);
+
+extern struct sh7091_reg sh7091 __asm("sh7091");

dreamcast2/sh7091/sh7091_bits.hpp

@@ -0,0 +1,994 @@
+#pragma once
+
+#include <cstdint>
+
+namespace sh7091 {
+  namespace ccn {
+    namespace pteh {
+      constexpr uint32_t VPN(uint32_t reg) { return (reg >> 10) & 0x3fffff; }
+      constexpr uint32_t ASID(uint32_t reg) { return (reg >> 0) & 0xff; }
+    }
+
+    namespace ptel {
+      constexpr uint32_t PPN(uint32_t reg) { return (reg >> 10) & 0x7ffff; }
+
+      namespace v {
+        constexpr uint32_t invalid = 0 << 8;
+        constexpr uint32_t valid = 1 << 8;
+
+        constexpr uint32_t bit_mask = 0x1 << 8;
+      }
+
+      namespace sz {
+        constexpr uint32_t _1_kbyte_page = 0b0000 << 4;
+        constexpr uint32_t _4_kbyte_page = 0b0001 << 4;
+        constexpr uint32_t _64_kbyte_page = 0b1000 << 4;
+        constexpr uint32_t _1_mbyte_page = 0b1001 << 4;
+
+        constexpr uint32_t bit_mask = 0x9 << 4;
+      }
+
+      namespace pr {
+        constexpr uint32_t read_only_in_privileged_mode = 0b00 << 5;
+        constexpr uint32_t read_write_in_privileged_mode = 0b01 << 5;
+        constexpr uint32_t read_only_in_privileged_and_user_mode = 0b10 << 5;
+        constexpr uint32_t read_write_in_privileged_and_user_mode = 0b11 << 5;
+
+        constexpr uint32_t bit_mask = 0x3 << 5;
+      }
+
+      namespace c {
+        constexpr uint32_t not_cacheable = 0 << 3;
+        constexpr uint32_t cacheable = 1 << 3;
+
+        constexpr uint32_t bit_mask = 0x1 << 3;
+      }
+
+      namespace d {
+        constexpr uint32_t write_has_not_been_performed = 0 << 2;
+        constexpr uint32_t write_has_been_performed = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+
+      namespace sh {
+        constexpr uint32_t pages_are_shared_by_processes = 0 << 1;
+        constexpr uint32_t pages_are_not_shared_by_processes = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+
+      namespace wt {
+        constexpr uint32_t copy_back_mode = 0 << 0;
+        constexpr uint32_t write_through_mode = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace mmucr {
+      constexpr uint32_t LRUI(uint32_t reg) { return (reg >> 26) & 0x3f; }
+      constexpr uint32_t URB(uint32_t reg) { return (reg >> 18) & 0x3f; }
+      constexpr uint32_t URC(uint32_t reg) { return (reg >> 10) & 0x3f; }
+
+      namespace sqmd {
+        constexpr uint32_t user_privileged_access_possible = 0 << 9;
+        constexpr uint32_t privileged_access_possible = 1 << 9;
+
+        constexpr uint32_t bit_mask = 0x1 << 9;
+      }
+
+      namespace sv {
+        constexpr uint32_t multiple_virtual_memory_mode = 0 << 8;
+        constexpr uint32_t single_virtual_memory_mode = 1 << 8;
+
+        constexpr uint32_t bit_mask = 0x1 << 8;
+      }
+
+      namespace ti {
+        constexpr uint32_t invalidate_all_utlb_itlb_bits = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+
+      namespace at {
+        constexpr uint32_t mmu_disabled = 0 << 0;
+        constexpr uint32_t mmu_enabled = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace basra {
+      constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
+    }
+
+    namespace basrb {
+      constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
+    }
+
+    namespace ccr {
+      namespace iix {
+        constexpr uint32_t address_bits_12_5_used_for_ic_entry_selection = 0 << 15;
+        constexpr uint32_t address_bits_25_and_11_5_used_for_ic_entry_selection = 1 << 15;
+
+        constexpr uint32_t bit_mask = 0x1 << 15;
+      }
+
+      namespace ici {
+        constexpr uint32_t clear_v_bits_of_all_ic_entries = 1 << 11;
+
+        constexpr uint32_t bit_mask = 0x1 << 11;
+      }
+
+      namespace ice {
+        constexpr uint32_t ic_not_used = 0 << 8;
+        constexpr uint32_t ic_used = 1 << 8;
+
+        constexpr uint32_t bit_mask = 0x1 << 8;
+      }
+
+      namespace oix {
+        constexpr uint32_t address_bits_13_5_used_for_oc_entry_selection = 0 << 7;
+        constexpr uint32_t address_bits_25_and_12_5_used_for_oc_entry_selection = 1 << 7;
+
+        constexpr uint32_t bit_mask = 0x1 << 7;
+      }
+
+      namespace ora {
+        constexpr uint32_t _16_kbytes_used_as_cache = 0 << 5;
+        constexpr uint32_t _8_kbytes_used_as_cache_8_kbytes_used_as_ram = 1 << 5;
+
+        constexpr uint32_t bit_mask = 0x1 << 5;
+      }
+
+      namespace oci {
+        constexpr uint32_t clear_v_and_u_bits_of_all_oc_entries = 1 << 3;
+
+        constexpr uint32_t bit_mask = 0x1 << 3;
+      }
+
+      namespace cb {
+        constexpr uint32_t write_through_mode = 0 << 2;
+        constexpr uint32_t copy_back_mode = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+
+      namespace wt {
+        constexpr uint32_t copy_back_mode = 0 << 1;
+        constexpr uint32_t write_through_mode = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+
+      namespace oce {
+        constexpr uint32_t oc_not_used = 0 << 0;
+        constexpr uint32_t oc_used = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace tra {
+      constexpr uint32_t imm(uint32_t reg) { return (reg >> 2) & 0xff; }
+    }
+
+    namespace expevt {
+      constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
+    }
+
+    namespace intevt {
+      constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
+    }
+
+    namespace ptea {
+      namespace tc {
+        constexpr uint32_t area_5_is_used = 0 << 3;
+        constexpr uint32_t area_6_is_used = 1 << 3;
+
+        constexpr uint32_t bit_mask = 0x1 << 3;
+      }
+
+      namespace sa {
+        constexpr uint32_t undefined = 0b000 << 0;
+        constexpr uint32_t variable_size_io_space = 0b001 << 0;
+        constexpr uint32_t _8_bit_io_space = 0b010 << 0;
+        constexpr uint32_t _16_bit_io_space = 0b011 << 0;
+        constexpr uint32_t _8_bit_common_memory_space = 0b100 << 0;
+        constexpr uint32_t _16_bit_common_memory_space = 0b101 << 0;
+        constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 0;
+        constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 0;
+
+        constexpr uint32_t bit_mask = 0x7 << 0;
+      }
+    }
+
+    namespace qacr0 {
+      constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
+    }
+
+    namespace qacr1 {
+      constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
+    }
+
+  }
+
+  namespace dmac {
+    namespace dmatcr {
+      constexpr uint32_t transfer_count(uint32_t num) { return (num & 0xffffff) << 0; }
+    }
+
+    namespace chcr {
+      namespace ssa {
+        constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 29;
+        constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 29;
+        constexpr uint32_t _8_bit_io_space = 0b010 << 29;
+        constexpr uint32_t _16_bit_io_space = 0b011 << 29;
+        constexpr uint32_t _8_bit_common_memory_space = 0b100 << 29;
+        constexpr uint32_t _16_bit_common_memory_space = 0b101 << 29;
+        constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 29;
+        constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 29;
+
+        constexpr uint32_t bit_mask = 0x7 << 29;
+      }
+
+      namespace stc {
+        constexpr uint32_t c5_space_wait_cycle_selection = 0 << 28;
+        constexpr uint32_t c6_space_wait_cycle_selection = 1 << 28;
+
+        constexpr uint32_t bit_mask = 0x1 << 28;
+      }
+
+      namespace dsa {
+        constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 25;
+        constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 25;
+        constexpr uint32_t _8_bit_io_space = 0b010 << 25;
+        constexpr uint32_t _16_bit_io_space = 0b011 << 25;
+        constexpr uint32_t _8_bit_common_memory_space = 0b100 << 25;
+        constexpr uint32_t _16_bit_common_memory_space = 0b101 << 25;
+        constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 25;
+        constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 25;
+
+        constexpr uint32_t bit_mask = 0x7 << 25;
+      }
+
+      namespace dtc {
+        constexpr uint32_t c5_space_wait_cycle_selection = 0 << 24;
+        constexpr uint32_t c6_space_wait_cycle_selection = 1 << 24;
+
+        constexpr uint32_t bit_mask = 0x1 << 24;
+      }
+
+      namespace ds {
+        constexpr uint32_t low_level_detection = 0 << 19;
+        constexpr uint32_t falling_edge_detection = 1 << 19;
+
+        constexpr uint32_t bit_mask = 0x1 << 19;
+      }
+
+      namespace rl {
+        constexpr uint32_t drak_is_an_active_high = 0 << 18;
+        constexpr uint32_t drak_is_an_active_low = 1 << 18;
+
+        constexpr uint32_t bit_mask = 0x1 << 18;
+      }
+
+      namespace am {
+        constexpr uint32_t dack_is_output_in_read_cycle = 0 << 17;
+        constexpr uint32_t dack_is_output_in_write_cycle = 1 << 17;
+
+        constexpr uint32_t bit_mask = 0x1 << 17;
+      }
+
+      namespace al {
+        constexpr uint32_t active_high_output = 0 << 16;
+        constexpr uint32_t active_low_output = 1 << 16;
+
+        constexpr uint32_t bit_mask = 0x1 << 16;
+      }
+
+      namespace dm {
+        constexpr uint32_t destination_address_fixed = 0b00 << 14;
+        constexpr uint32_t destination_address_incremented = 0b01 << 14;
+        constexpr uint32_t destination_address_decremented = 0b10 << 14;
+
+        constexpr uint32_t bit_mask = 0x3 << 14;
+      }
+
+      namespace sm {
+        constexpr uint32_t source_address_fixed = 0b00 << 12;
+        constexpr uint32_t source_address_incremented = 0b01 << 12;
+        constexpr uint32_t source_address_decremented = 0b10 << 12;
+
+        constexpr uint32_t bit_mask = 0x3 << 12;
+      }
+
+      namespace rs {
+        constexpr uint32_t resource_select(uint32_t num) { return (num & 0xf) << 8; }
+
+        constexpr uint32_t bit_mask = 0xf << 8;
+      }
+
+      namespace tm {
+        constexpr uint32_t cycle_steal_mode = 0 << 7;
+        constexpr uint32_t cycle_burst_mode = 1 << 7;
+
+        constexpr uint32_t bit_mask = 0x1 << 7;
+      }
+
+      namespace ts {
+        constexpr uint32_t _64_bit = 0b000 << 4;
+        constexpr uint32_t _8_bit = 0b001 << 4;
+        constexpr uint32_t _16_bit = 0b010 << 4;
+        constexpr uint32_t _32_bit = 0b011 << 4;
+        constexpr uint32_t _32_byte = 0b100 << 4;
+
+        constexpr uint32_t bit_mask = 0x7 << 4;
+      }
+
+      namespace ie {
+        constexpr uint32_t interrupt_request_not_generated = 0 << 2;
+        constexpr uint32_t interrupt_request_generated = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+
+      namespace te {
+        constexpr uint32_t transfers_not_completed = 0 << 1;
+        constexpr uint32_t transfers_completed = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+
+      namespace de {
+        constexpr uint32_t channel_operation_disabled = 0 << 0;
+        constexpr uint32_t channel_operation_enabled = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace dmaor {
+      namespace ddt {
+        constexpr uint32_t normal_dma_mode = 0 << 15;
+        constexpr uint32_t on_demand_data_transfer_mode = 1 << 15;
+
+        constexpr uint32_t bit_mask = 0x1 << 15;
+      }
+
+      namespace pr {
+        constexpr uint32_t ch0_ch1_ch2_ch3 = 0b00 << 8;
+        constexpr uint32_t ch0_ch2_ch3_ch1 = 0b01 << 8;
+        constexpr uint32_t ch2_ch0_ch1_ch3 = 0b10 << 8;
+        constexpr uint32_t round_robin = 0b11 << 8;
+
+        constexpr uint32_t bit_mask = 0x3 << 8;
+      }
+
+      namespace ae {
+        constexpr uint32_t no_address_error__dma_transfer_enabled = 0 << 2;
+        constexpr uint32_t address_error__dma_transfer_disabled = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+
+      namespace nmif {
+        constexpr uint32_t no_nmi__dma_transfer_enabled = 0 << 1;
+        constexpr uint32_t nmi__dma_transfer_disabled = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+
+      namespace dme {
+        constexpr uint32_t operation_disabled_on_all_channels = 0 << 0;
+        constexpr uint32_t operation_enabled_on_all_channels = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+  }
+
+  namespace intc {
+    namespace icr {
+      namespace nmil {
+        constexpr uint32_t pin_input_level_is_low = 0 << 15;
+        constexpr uint32_t pin_input_level_is_high = 1 << 15;
+
+        constexpr uint32_t bit_mask = 0x1 << 15;
+      }
+
+      namespace mai {
+        constexpr uint32_t interrupts_enabled_while_nmi_pin_is_low = 0 << 14;
+        constexpr uint32_t interrupts_disabled_while_nmi_pin_is_low = 1 << 14;
+
+        constexpr uint32_t bit_mask = 0x1 << 14;
+      }
+
+      namespace nmib {
+        constexpr uint32_t interrupt_requests_witheld = 0 << 9;
+        constexpr uint32_t interrupt_requests_detected = 1 << 9;
+
+        constexpr uint32_t bit_mask = 0x1 << 9;
+      }
+
+      namespace nmie {
+        constexpr uint32_t interrupt_on_falling_edge_of_nmi = 0 << 8;
+        constexpr uint32_t interrupt_on_rising_edge_of_nmi = 1 << 8;
+
+        constexpr uint32_t bit_mask = 0x1 << 8;
+      }
+
+      namespace irlm {
+        constexpr uint32_t level_encoded_interrupt_requests = 0 << 7;
+        constexpr uint32_t independent_interrupt_request = 1 << 7;
+
+        constexpr uint32_t bit_mask = 0x1 << 7;
+      }
+    }
+
+    namespace ipra {
+      constexpr uint32_t TMU0(uint32_t num) { return (num & 0xf) << 12; }
+      constexpr uint32_t TMU1(uint32_t num) { return (num & 0xf) << 8; }
+      constexpr uint32_t TMU2(uint32_t num) { return (num & 0xf) << 4; }
+      constexpr uint32_t RTC(uint32_t num) { return (num & 0xf) << 0; }
+    }
+
+    namespace iprb {
+      constexpr uint32_t WDT(uint32_t num) { return (num & 0xf) << 12; }
+      constexpr uint32_t REF(uint32_t num) { return (num & 0xf) << 8; }
+      constexpr uint32_t SCI1(uint32_t num) { return (num & 0xf) << 4; }
+    }
+
+    namespace iprc {
+      constexpr uint32_t GPIO(uint32_t num) { return (num & 0xf) << 12; }
+      constexpr uint32_t DMAC(uint32_t num) { return (num & 0xf) << 8; }
+      constexpr uint32_t SCIF(uint32_t num) { return (num & 0xf) << 4; }
+      constexpr uint32_t UDI(uint32_t num) { return (num & 0xf) << 0; }
+    }
+
+  }
+
+  namespace tmu {
+    namespace tocr {
+      namespace tcoe {
+        constexpr uint32_t tclk_is_external_clock_or_input_capture = 0 << 0;
+        constexpr uint32_t tclk_is_on_chip_rtc = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace tstr {
+      namespace str2 {
+        constexpr uint32_t counter_start = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+
+      namespace str1 {
+        constexpr uint32_t counter_start = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+
+      namespace str0 {
+        constexpr uint32_t counter_start = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace tcr0 {
+      constexpr uint32_t UNF = 1 << 8;
+      constexpr uint32_t UNIE = 1 << 5;
+
+      namespace ckeg {
+        constexpr uint32_t rising = 0b00 << 3;
+        constexpr uint32_t falling = 0b01 << 3;
+        constexpr uint32_t rising_falling = 0b10 << 3;
+
+        constexpr uint32_t bit_mask = 0x3 << 3;
+      }
+
+      namespace tpsc {
+        constexpr uint32_t p_phi_4 = 0b000 << 0;
+        constexpr uint32_t p_phi_16 = 0b001 << 0;
+        constexpr uint32_t p_phi_64 = 0b010 << 0;
+        constexpr uint32_t p_phi_256 = 0b011 << 0;
+        constexpr uint32_t p_phi_1024 = 0b100 << 0;
+        constexpr uint32_t rtc_output = 0b110 << 0;
+        constexpr uint32_t external = 0b111 << 0;
+
+        constexpr uint32_t bit_mask = 0x7 << 0;
+      }
+    }
+
+    namespace tcr1 {
+      constexpr uint32_t UNF = 1 << 8;
+      constexpr uint32_t UNIE = 1 << 5;
+
+      namespace ckeg {
+        constexpr uint32_t rising = 0b00 << 3;
+        constexpr uint32_t falling = 0b01 << 3;
+        constexpr uint32_t rising_falling = 0b10 << 3;
+
+        constexpr uint32_t bit_mask = 0x3 << 3;
+      }
+
+      namespace tpsc {
+        constexpr uint32_t p_phi_4 = 0b000 << 0;
+        constexpr uint32_t p_phi_16 = 0b001 << 0;
+        constexpr uint32_t p_phi_64 = 0b010 << 0;
+        constexpr uint32_t p_phi_256 = 0b011 << 0;
+        constexpr uint32_t p_phi_1024 = 0b100 << 0;
+        constexpr uint32_t rtc_output = 0b110 << 0;
+        constexpr uint32_t external = 0b111 << 0;
+
+        constexpr uint32_t bit_mask = 0x7 << 0;
+      }
+    }
+
+    namespace tcr2 {
+      constexpr uint32_t ICPF = 1 << 9;
+      constexpr uint32_t UNF = 1 << 8;
+
+      namespace icpe {
+        constexpr uint32_t disabled = 0b00 << 6;
+        constexpr uint32_t enabled = 0b10 << 6;
+        constexpr uint32_t enabled_with_interrupts = 0b11 << 6;
+
+        constexpr uint32_t bit_mask = 0x3 << 6;
+      }
+
+      constexpr uint32_t UNIE = 1 << 5;
+
+      namespace ckeg {
+        constexpr uint32_t rising = 0b00 << 3;
+        constexpr uint32_t falling = 0b01 << 3;
+        constexpr uint32_t rising_falling = 0b10 << 3;
+
+        constexpr uint32_t bit_mask = 0x3 << 3;
+      }
+
+      namespace tpsc {
+        constexpr uint32_t p_phi_4 = 0b000 << 0;
+        constexpr uint32_t p_phi_16 = 0b001 << 0;
+        constexpr uint32_t p_phi_64 = 0b010 << 0;
+        constexpr uint32_t p_phi_256 = 0b011 << 0;
+        constexpr uint32_t p_phi_1024 = 0b100 << 0;
+        constexpr uint32_t rtc_output = 0b110 << 0;
+        constexpr uint32_t external = 0b111 << 0;
+
+        constexpr uint32_t bit_mask = 0x7 << 0;
+      }
+    }
+
+  }
+
+  namespace scif {
+    namespace scsmr2 {
+      namespace chr {
+        constexpr uint32_t _8_bit_data = 0 << 6;
+        constexpr uint32_t _7_bit_data = 1 << 6;
+
+        constexpr uint32_t bit_mask = 0x1 << 6;
+      }
+
+      namespace pe {
+        constexpr uint32_t parity_disabled = 0 << 5;
+        constexpr uint32_t parity_enabled = 1 << 5;
+
+        constexpr uint32_t bit_mask = 0x1 << 5;
+      }
+
+      namespace oe {
+        constexpr uint32_t even_parity = 0 << 4;
+        constexpr uint32_t odd_parity = 1 << 4;
+
+        constexpr uint32_t bit_mask = 0x1 << 4;
+      }
+
+      namespace stop {
+        constexpr uint32_t _1_stop_bit = 0 << 3;
+        constexpr uint32_t _2_stop_bits = 1 << 3;
+
+        constexpr uint32_t bit_mask = 0x1 << 3;
+      }
+
+      namespace cks {
+        constexpr uint32_t p_phi_clock = 0b00 << 0;
+        constexpr uint32_t p_phi_4_clock = 0b01 << 0;
+        constexpr uint32_t p_phi_16_clock = 0b10 << 0;
+        constexpr uint32_t p_phi_64_clock = 0b11 << 0;
+
+        constexpr uint32_t bit_mask = 0x3 << 0;
+      }
+    }
+
+    namespace scscr2 {
+      namespace tie {
+        constexpr uint32_t transmit_fifo_data_empty_interrupt_disabled = 0 << 7;
+        constexpr uint32_t transmit_fifo_data_empty_interrupt_enabled = 1 << 7;
+
+        constexpr uint32_t bit_mask = 0x1 << 7;
+      }
+
+      namespace rie {
+        constexpr uint32_t request_disabled = 0 << 6;
+        constexpr uint32_t request_enabled = 1 << 6;
+
+        constexpr uint32_t bit_mask = 0x1 << 6;
+      }
+
+      namespace te {
+        constexpr uint32_t transmission_disabled = 0 << 5;
+        constexpr uint32_t transmission_enabled = 1 << 5;
+
+        constexpr uint32_t bit_mask = 0x1 << 5;
+      }
+
+      namespace re {
+        constexpr uint32_t reception_disabled = 0 << 4;
+        constexpr uint32_t reception_enabled = 1 << 4;
+
+        constexpr uint32_t bit_mask = 0x1 << 4;
+      }
+
+      namespace reie {
+        constexpr uint32_t requests_disabled = 0 << 3;
+        constexpr uint32_t requests_enabled = 1 << 3;
+
+        constexpr uint32_t bit_mask = 0x1 << 3;
+      }
+
+      namespace cke1 {
+        constexpr uint32_t sck2_pin_functions_as_input_pin = 0 << 1;
+        constexpr uint32_t sck2_pin_functions_as_clock_input = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+    }
+
+    namespace scfsr2 {
+      namespace per3_0 {
+        constexpr uint32_t number_of_parity_errors(uint32_t reg) { return (reg >> 12) & 0xf; }
+
+        constexpr uint32_t bit_mask = 0xf << 12;
+      }
+
+      namespace fer3_0 {
+        constexpr uint32_t number_of_framing_errors(uint32_t reg) { return (reg >> 8) & 0xf; }
+
+        constexpr uint32_t bit_mask = 0xf << 8;
+      }
+
+      namespace er {
+        constexpr uint32_t no_framing_error_or_parity_error = 0 << 7;
+        constexpr uint32_t framing_error_or_parity_error = 1 << 7;
+
+        constexpr uint32_t bit_mask = 0x1 << 7;
+      }
+
+      namespace tend {
+        constexpr uint32_t transmission_in_progress = 0 << 6;
+        constexpr uint32_t transmission_has_ended = 1 << 6;
+
+        constexpr uint32_t bit_mask = 0x1 << 6;
+      }
+
+      namespace tdfe {
+        constexpr uint32_t transmit_data_bytes_does_exceed_trigger = 0 << 5;
+        constexpr uint32_t transmit_data_bytes_does_not_exceed_trigger = 1 << 5;
+
+        constexpr uint32_t bit_mask = 0x1 << 5;
+      }
+
+      namespace brk {
+        constexpr uint32_t break_not_received = 0 << 4;
+        constexpr uint32_t break_received = 1 << 4;
+
+        constexpr uint32_t bit_mask = 0x1 << 4;
+      }
+
+      namespace fer {
+        constexpr uint32_t no_framing_error = 0 << 3;
+        constexpr uint32_t framing_error = 1 << 3;
+
+        constexpr uint32_t bit_mask = 0x1 << 3;
+      }
+
+      namespace per {
+        constexpr uint32_t parity_error = 0 << 2;
+        constexpr uint32_t no_parity_error = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+
+      namespace rdf {
+        constexpr uint32_t receive_data_bytes_less_than_receive_trigger = 0 << 1;
+        constexpr uint32_t receive_data_bytes_greater_than_or_equal_receive_trigger = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+
+      namespace dr {
+        constexpr uint32_t reception_is_in_progress = 0 << 0;
+        constexpr uint32_t no_further_data_has_arrived = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace scfcr2 {
+      namespace rtrg {
+        constexpr uint32_t trigger_on_1_byte = 0b00 << 6;
+        constexpr uint32_t trigger_on_4_bytes = 0b01 << 6;
+        constexpr uint32_t trigger_on_8_bytes = 0b10 << 6;
+        constexpr uint32_t trigger_on_14_byte = 0b11 << 6;
+
+        constexpr uint32_t bit_mask = 0x3 << 6;
+      }
+
+      namespace ttrg {
+        constexpr uint32_t trigger_on_8_bytes = 0b00 << 4;
+        constexpr uint32_t trigger_on_4_bytes = 0b01 << 4;
+        constexpr uint32_t trigger_on_2_bytes = 0b10 << 4;
+        constexpr uint32_t trigger_on_1_bytes = 0b11 << 4;
+
+        constexpr uint32_t bit_mask = 0x3 << 4;
+      }
+
+      namespace mce {
+        constexpr uint32_t modem_signals_disabled = 0 << 3;
+        constexpr uint32_t modem_signals_enabled = 1 << 3;
+
+        constexpr uint32_t bit_mask = 0x1 << 3;
+      }
+
+      namespace tfrst {
+        constexpr uint32_t reset_operation_disabled = 0 << 2;
+        constexpr uint32_t reset_operation_enabled = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+
+      namespace rfrst {
+        constexpr uint32_t reset_operation_disabled = 0 << 1;
+        constexpr uint32_t reset_operation_enabled = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+
+      namespace loop {
+        constexpr uint32_t loopback_test_disabled = 0 << 0;
+        constexpr uint32_t loopback_test_enabled = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace scfdr2 {
+      constexpr uint32_t transmit_data_bytes(uint32_t reg) { return (reg >> 8) & 0x1f; }
+      constexpr uint32_t receive_data_bytes(uint32_t reg) { return (reg >> 0) & 0x1f; }
+    }
+
+    namespace scsptr2 {
+      namespace rtsio {
+        constexpr uint32_t rtsdt_not_output_to_rts2 = 0 << 7;
+        constexpr uint32_t rtsdt_output_to_rts2 = 1 << 7;
+
+        constexpr uint32_t bit_mask = 0x1 << 7;
+      }
+
+      namespace rtsdt {
+        constexpr uint32_t input_output_data_is_low_level = 0 << 6;
+        constexpr uint32_t input_output_data_is_high_level = 1 << 6;
+
+        constexpr uint32_t bit_mask = 0x1 << 6;
+      }
+
+      namespace ctsio {
+        constexpr uint32_t ctsdt_is_not_output_to_cts2 = 0 << 5;
+        constexpr uint32_t ctsdt_is_output_to_cts2 = 1 << 5;
+
+        constexpr uint32_t bit_mask = 0x1 << 5;
+      }
+
+      namespace ctsdt {
+        constexpr uint32_t input_output_data_is_low_level = 0 << 4;
+        constexpr uint32_t input_output_data_is_high_level = 1 << 4;
+
+        constexpr uint32_t bit_mask = 0x1 << 4;
+      }
+
+      namespace spb2io {
+        constexpr uint32_t spb2dt_is_not_output_to_txd2 = 0 << 1;
+        constexpr uint32_t spb2dt_is_output_to_txd2 = 1 << 1;
+
+        constexpr uint32_t bit_mask = 0x1 << 1;
+      }
+
+      namespace spb2dt {
+        constexpr uint32_t input_output_data_is_low_level = 0 << 0;
+        constexpr uint32_t input_output_data_is_high_level = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+    namespace sclsr2 {
+      namespace orer {
+        constexpr uint32_t overrun_error_occured = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+  }
+
+  namespace sh {
+    namespace sr {
+      constexpr uint32_t md = 1 << 30;
+      constexpr uint32_t rb = 1 << 29;
+      constexpr uint32_t bl = 1 << 28;
+      constexpr uint32_t fd = 1 << 15;
+      constexpr uint32_t m = 1 << 9;
+      constexpr uint32_t q = 1 << 8;
+      constexpr uint32_t imask(uint32_t num) { return (num & 0xf) << 4; }
+      constexpr uint32_t s = 1 << 1;
+      constexpr uint32_t t = 1 << 0;
+    }
+
+    namespace fpscr {
+      constexpr uint32_t fr = 1 << 21;
+      constexpr uint32_t sz = 1 << 20;
+      constexpr uint32_t pr = 1 << 19;
+      constexpr uint32_t dn = 1 << 18;
+
+      namespace cause {
+        constexpr uint32_t fpu_error = 0b100000 << 12;
+        constexpr uint32_t invalid_operation = 0b010000 << 12;
+        constexpr uint32_t division_by_zero = 0b001000 << 12;
+        constexpr uint32_t overflow = 0b000100 << 12;
+        constexpr uint32_t underflow = 0b000010 << 12;
+        constexpr uint32_t inexact = 0b000001 << 12;
+
+        constexpr uint32_t bit_mask = 0x3f << 12;
+      }
+
+      namespace enabled {
+        constexpr uint32_t invalid_operation = 0b10000 << 7;
+        constexpr uint32_t division_by_zero = 0b01000 << 7;
+        constexpr uint32_t overflow = 0b00100 << 7;
+        constexpr uint32_t underflow = 0b00010 << 7;
+        constexpr uint32_t inexact = 0b00001 << 7;
+
+        constexpr uint32_t bit_mask = 0x1f << 7;
+      }
+
+      namespace flag {
+        constexpr uint32_t invalid_operation = 0b10000 << 2;
+        constexpr uint32_t division_by_zero = 0b01000 << 2;
+        constexpr uint32_t overflow = 0b00100 << 2;
+        constexpr uint32_t underflow = 0b00010 << 2;
+        constexpr uint32_t inexact = 0b00001 << 2;
+
+        constexpr uint32_t bit_mask = 0x1f << 2;
+      }
+
+      namespace rm {
+        constexpr uint32_t round_to_nearest = 0b00 << 0;
+        constexpr uint32_t round_to_zero = 0b01 << 0;
+
+        constexpr uint32_t bit_mask = 0x3 << 0;
+      }
+    }
+
+  }
+
+  namespace ubc {
+    namespace bamra {
+      namespace bama {
+        constexpr uint32_t all_bara_bits_are_included_in_break_conditions = 0b0000 << 0;
+        constexpr uint32_t lower_10_bits_of_bara_are_not_included_in_break_conditions = 0b0001 << 0;
+        constexpr uint32_t lower_12_bits_of_bara_are_not_included_in_break_conditions = 0b0010 << 0;
+        constexpr uint32_t all_bara_bits_are_not_included_in_break_conditions = 0b0011 << 0;
+        constexpr uint32_t lower_16_bits_of_bara_are_not_included_in_break_conditions = 0b1000 << 0;
+        constexpr uint32_t lower_20_bits_of_bara_are_not_included_in_break_conditions = 0b1001 << 0;
+
+        constexpr uint32_t bit_mask = 0xb << 0;
+      }
+
+      namespace basma {
+        constexpr uint32_t all_basra_bits_are_included_in_break_conditions = 0 << 2;
+        constexpr uint32_t no_basra_bits_are_included_in_break_conditions = 1 << 2;
+
+        constexpr uint32_t bit_mask = 0x1 << 2;
+      }
+    }
+
+    namespace bbra {
+      namespace sza {
+        constexpr uint32_t operand_size_is_not_included_in_break_conditions = 0b00 << 0;
+        constexpr uint32_t byte_access_is_used_as_break_condition = 0b01 << 0;
+        constexpr uint32_t word_access_is_used_as_break_condition = 0b10 << 0;
+        constexpr uint32_t longword_access_is_used_as_break_condition = 0b11 << 0;
+        constexpr uint32_t quadword_access_is_used_as_break_condition = 0b1000000 << 0;
+
+        constexpr uint32_t bit_mask = 0x43 << 0;
+      }
+
+      namespace ida {
+        constexpr uint32_t condition_comparison_is_not_performed = 0b00 << 4;
+        constexpr uint32_t instruction_access_cycle_is_used_as_break_condition = 0b01 << 4;
+        constexpr uint32_t operand_access_cycle_is_used_as_break_condition = 0b10 << 4;
+        constexpr uint32_t instruction_access_cycle_or_operand_access_cycle_is_used_as_break_condition = 0b11 << 4;
+
+        constexpr uint32_t bit_mask = 0x3 << 4;
+      }
+
+      namespace rwa {
+        constexpr uint32_t condition_comparison_is_not_performed = 0b00 << 2;
+        constexpr uint32_t read_cycle_is_used_as_break_condition = 0b01 << 2;
+        constexpr uint32_t write_cycle_is_used_as_break_condition = 0b10 << 2;
+        constexpr uint32_t read_cycle_or_write_cycle_is_used_as_break_condition = 0b11 << 2;
+
+        constexpr uint32_t bit_mask = 0x3 << 2;
+      }
+    }
+
+    namespace brcr {
+      namespace cmfa {
+        constexpr uint32_t channel_a_break_condition_is_not_matched = 0 << 15;
+        constexpr uint32_t channel_a_break_condition_match_has_occured = 1 << 15;
+
+        constexpr uint32_t bit_mask = 0x1 << 15;
+      }
+
+      namespace cmfb {
+        constexpr uint32_t channel_b_break_condition_is_not_matched = 0 << 14;
+        constexpr uint32_t channel_b_break_condition_match_has_occured = 1 << 14;
+
+        constexpr uint32_t bit_mask = 0x1 << 14;
+      }
+
+      namespace pcba {
+        constexpr uint32_t channel_a_pc_break_is_effected_before_instruction_execution = 0 << 10;
+        constexpr uint32_t channel_a_pc_break_is_effected_after_instruction_execution = 1 << 10;
+
+        constexpr uint32_t bit_mask = 0x1 << 10;
+      }
+
+      namespace dbeb {
+        constexpr uint32_t data_bus_condition_is_not_included_in_channel_b_conditions = 0 << 7;
+        constexpr uint32_t data_bus_condition_is_included_in_channel_b_conditions = 1 << 7;
+
+        constexpr uint32_t bit_mask = 0x1 << 7;
+      }
+
+      namespace pcbb {
+        constexpr uint32_t channel_b_pc_break_is_effected_before_instruction_execution = 0 << 6;
+        constexpr uint32_t channel_b_pc_break_is_effected_after_instruction_execution = 1 << 6;
+
+        constexpr uint32_t bit_mask = 0x1 << 6;
+      }
+
+      namespace seq {
+        constexpr uint32_t channel_a_and_b_comparison_are_performed_as_independent_condition = 0 << 3;
+        constexpr uint32_t channel_a_and_b_comparison_are_performed_as_sequential_condition = 1 << 3;
+
+        constexpr uint32_t bit_mask = 0x1 << 3;
+      }
+
+      namespace ubde {
+        constexpr uint32_t user_break_debug_function_is_not_used = 0 << 0;
+        constexpr uint32_t user_break_debug_function_is_used = 1 << 0;
+
+        constexpr uint32_t bit_mask = 0x1 << 0;
+      }
+    }
+
+  }
+}

dreamcast2/sh7091/store_queue_transfer.hpp

@@ -0,0 +1,70 @@
+#pragma once
+
+#include "sh7091/sh7091.hpp"
+#include "memorymap.hpp"
+
+namespace sh7091 {
+  namespace store_queue_transfer {
+
+    static inline void copy(void * out_addr,
+                            const void * src,
+                            int length)
+    {
+      uint32_t out = reinterpret_cast<uint32_t>(out_addr);
+      sh7091.CCN.QACR0 = ((out >> 24) & 0b11100);
+      sh7091.CCN.QACR1 = ((out >> 24) & 0b11100);
+
+      volatile uint32_t * base = &store_queue[(out & 0x03ffffe0)];
+      const uint32_t * src32 = reinterpret_cast<const uint32_t *>(src);
+
+      length = (length + 31) & ~31; // round up to nearest multiple of 32
+      while (length > 0) {
+        base[0] = src32[0];
+        base[1] = src32[1];
+        base[2] = src32[2];
+        base[3] = src32[3];
+        base[4] = src32[4];
+        base[5] = src32[5];
+        base[6] = src32[6];
+        base[7] = src32[7];
+        asm volatile ("pref @%0"
+                      :                // output
+                      : "r" (&base[0]) // input
+                      : "memory");
+        length -= 32;
+        base += 8;
+        src32 += 8;
+      }
+    }
+
+
+    static inline void zeroize(void * out_addr,
+                               int length,
+                               const uint32_t value)
+    {
+      uint32_t out = reinterpret_cast<uint32_t>(out_addr);
+      sh7091.CCN.QACR0 = ((out >> 24) & 0b11100);
+      sh7091.CCN.QACR1 = ((out >> 24) & 0b11100);
+
+      volatile uint32_t * base = &store_queue[(out & 0x03ffffe0)];
+
+      length = (length + 31) & ~31; // round up to nearest multiple of 32
+      while (length > 0) {
+        base[0] = value;
+        base[1] = value;
+        base[2] = value;
+        base[3] = value;
+        base[4] = value;
+        base[5] = value;
+        base[6] = value;
+        base[7] = value;
+        asm volatile ("pref @%0"
+                      :                // output
+                      : "r" (&base[0]) // input
+                      : "memory");
+        length -= 32;
+        base += 8;
+      }
+    }
+  }
+}

dreamcast2/systembus/systembus.hpp

@@ -0,0 +1,308 @@
+#pragma once
+
+#include "reg.hpp"
+
+struct systembus_reg {
+  reg32 C2DSTAT;             /* CH2-DMA destination address */
+  reg32 C2DLEN;              /* CH2-DMA length */
+  reg32 C2DST;               /* CH2-DMA start */
+  reg8  _pad0[4];
+  reg32 SDSTAW;              /* Sort-DMA start link table address */
+  reg32 SDBAAW;              /* Sort-DMA link base address */
+  reg32 SDWLT;               /* Sort-DMA link address bit width */
+  reg32 SDLAS;               /* Sort-DMA link address shift control */
+  reg32 SDST;                /* Sort-DMA start */
+  reg8  _pad1[28];
+  reg32 DBREQM;              /* DBREQ# signal mask control */
+  reg32 BAVLWC;              /* BAVL# signal wait count */
+  reg32 C2DPYRC;             /* DMA (TA/Root Bus) priority count */
+  reg32 DMAXL;               /* CH2-DMA maximum burst length */
+  reg8  _pad2[48];
+  reg32 TFREM;               /* TA FIFO remaining amount */
+  reg32 LMMODE0;             /* Via TA texture memory bus select 0 */
+  reg32 LMMODE1;             /* Via TA texture memory bus select 1 */
+  reg32 FFST;                /* FIFO status */
+  reg32 SFRES;               /* System reset */
+  reg8  _pad3[8];
+  reg32 SBREV;               /* System bus revision number */
+  reg32 RBSPLT;              /* SH4 Root Bus split enable */
+  reg8  _pad4[92];
+  reg32 ISTNRM;              /* Normal interrupt status */
+  reg32 ISTEXT;              /* External interrupt status */
+  reg32 ISTERR;              /* Error interrupt status */
+  reg8  _pad5[4];
+  reg32 IML2NRM;             /* Level 2 normal interrupt mask */
+  reg32 IML2EXT;             /* Level 2 external interrupt mask */
+  reg32 IML2ERR;             /* Level 2 error interrupt mask */
+  reg8  _pad6[4];
+  reg32 IML4NRM;             /* Level 4 normal interrupt mask */
+  reg32 IML4EXT;             /* Level 4 external interrupt mask */
+  reg32 IML4ERR;             /* Level 4 error interrupt mask */
+  reg8  _pad7[4];
+  reg32 IML6NRM;             /* Level 6 normal interrupt mask */
+  reg32 IML6EXT;             /* Level 6 external interrupt mask */
+  reg32 IML6ERR;             /* Level 6 error interrupt mask */
+  reg8  _pad8[4];
+  reg32 PDTNRM;              /* Normal interrupt PVR-DMA startup mask */
+  reg32 PDTEXT;              /* External interrupt PVR-DMA startup mask */
+  reg8  _pad9[8];
+  reg32 G2DTNRM;             /* Normal interrupt G2-DMA startup mask */
+  reg32 G2DTEXT;             /* External interrupt G2-DMA startup mask */
+};
+
+static_assert((offsetof (struct systembus_reg, C2DSTAT)) == 0x0);
+static_assert((offsetof (struct systembus_reg, C2DLEN)) == 0x4);
+static_assert((offsetof (struct systembus_reg, C2DST)) == 0x8);
+static_assert((offsetof (struct systembus_reg, SDSTAW)) == 0x10);
+static_assert((offsetof (struct systembus_reg, SDBAAW)) == 0x14);
+static_assert((offsetof (struct systembus_reg, SDWLT)) == 0x18);
+static_assert((offsetof (struct systembus_reg, SDLAS)) == 0x1c);
+static_assert((offsetof (struct systembus_reg, SDST)) == 0x20);
+static_assert((offsetof (struct systembus_reg, DBREQM)) == 0x40);
+static_assert((offsetof (struct systembus_reg, BAVLWC)) == 0x44);
+static_assert((offsetof (struct systembus_reg, C2DPYRC)) == 0x48);
+static_assert((offsetof (struct systembus_reg, DMAXL)) == 0x4c);
+static_assert((offsetof (struct systembus_reg, TFREM)) == 0x80);
+static_assert((offsetof (struct systembus_reg, LMMODE0)) == 0x84);
+static_assert((offsetof (struct systembus_reg, LMMODE1)) == 0x88);
+static_assert((offsetof (struct systembus_reg, FFST)) == 0x8c);
+static_assert((offsetof (struct systembus_reg, SFRES)) == 0x90);
+static_assert((offsetof (struct systembus_reg, SBREV)) == 0x9c);
+static_assert((offsetof (struct systembus_reg, RBSPLT)) == 0xa0);
+static_assert((offsetof (struct systembus_reg, ISTNRM)) == 0x100);
+static_assert((offsetof (struct systembus_reg, ISTEXT)) == 0x104);
+static_assert((offsetof (struct systembus_reg, ISTERR)) == 0x108);
+static_assert((offsetof (struct systembus_reg, IML2NRM)) == 0x110);
+static_assert((offsetof (struct systembus_reg, IML2EXT)) == 0x114);
+static_assert((offsetof (struct systembus_reg, IML2ERR)) == 0x118);
+static_assert((offsetof (struct systembus_reg, IML4NRM)) == 0x120);
+static_assert((offsetof (struct systembus_reg, IML4EXT)) == 0x124);
+static_assert((offsetof (struct systembus_reg, IML4ERR)) == 0x128);
+static_assert((offsetof (struct systembus_reg, IML6NRM)) == 0x130);
+static_assert((offsetof (struct systembus_reg, IML6EXT)) == 0x134);
+static_assert((offsetof (struct systembus_reg, IML6ERR)) == 0x138);
+static_assert((offsetof (struct systembus_reg, PDTNRM)) == 0x140);
+static_assert((offsetof (struct systembus_reg, PDTEXT)) == 0x144);
+static_assert((offsetof (struct systembus_reg, G2DTNRM)) == 0x150);
+static_assert((offsetof (struct systembus_reg, G2DTEXT)) == 0x154);
+
+struct maple_if_reg {
+  reg8  _pad0[4];
+  reg32 MDSTAR;              /* Maple-DMA command table address */
+  reg8  _pad1[8];
+  reg32 MDTSEL;              /* Maple-DMA trigger select */
+  reg32 MDEN;                /* Maple-DMA enable */
+  reg32 MDST;                /* Maple-DMA start */
+  reg8  _pad2[100];
+  reg32 MSYS;                /* Maple system control */
+  reg32 MST;                 /* Maple status */
+  reg32 MSHTCL;              /* Maple-DMA hard trigger clear */
+  reg32 MDAPRO;              /* Maple-DMA address range */
+  reg8  _pad3[88];
+  reg32 MMSEL;               /* Maple MSP selection */
+  reg8  _pad4[8];
+  reg32 MTXDAD;              /* Maple TXD address counter */
+  reg32 MRXDAD;              /* Maple RXD address counter */
+  reg32 MRXDBD;              /* Maple RXD address base */
+};
+
+static_assert((offsetof (struct maple_if_reg, MDSTAR)) == 0x4);
+static_assert((offsetof (struct maple_if_reg, MDTSEL)) == 0x10);
+static_assert((offsetof (struct maple_if_reg, MDEN)) == 0x14);
+static_assert((offsetof (struct maple_if_reg, MDST)) == 0x18);
+static_assert((offsetof (struct maple_if_reg, MSYS)) == 0x80);
+static_assert((offsetof (struct maple_if_reg, MST)) == 0x84);
+static_assert((offsetof (struct maple_if_reg, MSHTCL)) == 0x88);
+static_assert((offsetof (struct maple_if_reg, MDAPRO)) == 0x8c);
+static_assert((offsetof (struct maple_if_reg, MMSEL)) == 0xe8);
+static_assert((offsetof (struct maple_if_reg, MTXDAD)) == 0xf4);
+static_assert((offsetof (struct maple_if_reg, MRXDAD)) == 0xf8);
+static_assert((offsetof (struct maple_if_reg, MRXDBD)) == 0xfc);
+
+struct g1_if_reg {
+  reg8  _pad0[4];
+  reg32 GDSTAR;              /* GD-DMA start address */
+  reg32 GDLEN;               /* GD-DMA length */
+  reg32 GDDIR;               /* GD-DMA direction */
+  reg8  _pad1[4];
+  reg32 GDEN;                /* GD-DMA enable */
+  reg32 GDST;                /* GD-DMA start */
+  reg8  _pad2[100];
+  reg32 G1RRC;               /* System ROM read access timing */
+  reg32 G1RWC;               /* System ROM write access timing */
+  reg32 G1FRC;               /* Flash ROM read access timing */
+  reg32 G1FWC;               /* Flash ROM write access timing */
+  reg32 G1CRC;               /* GD PIO read access timing */
+  reg32 G1CWC;               /* GD PIO write access timing */
+  reg8  _pad3[8];
+  reg32 G1GDRC;              /* GD-DMA read access timing */
+  reg32 G1GDWC;              /* GD-DMA write access timing */
+  reg8  _pad4[8];
+  reg32 G1SYSM;              /* System mode */
+  reg32 G1CRDYC;             /* G1IORDY signal control */
+  reg32 GDAPRO;              /* GD-DMA address range */
+  reg8  _pad5[40];
+  reg32 GDUNLOCK;            /* (undocumented unlock register) */
+  reg8  _pad6[12];
+  reg32 GDSTARD;             /* GD-DMA address count (on Root Bus) */
+  reg32 GDLEND;              /* GD-DMA transfer counter */
+};
+
+static_assert((offsetof (struct g1_if_reg, GDSTAR)) == 0x4);
+static_assert((offsetof (struct g1_if_reg, GDLEN)) == 0x8);
+static_assert((offsetof (struct g1_if_reg, GDDIR)) == 0xc);
+static_assert((offsetof (struct g1_if_reg, GDEN)) == 0x14);
+static_assert((offsetof (struct g1_if_reg, GDST)) == 0x18);
+static_assert((offsetof (struct g1_if_reg, G1RRC)) == 0x80);
+static_assert((offsetof (struct g1_if_reg, G1RWC)) == 0x84);
+static_assert((offsetof (struct g1_if_reg, G1FRC)) == 0x88);
+static_assert((offsetof (struct g1_if_reg, G1FWC)) == 0x8c);
+static_assert((offsetof (struct g1_if_reg, G1CRC)) == 0x90);
+static_assert((offsetof (struct g1_if_reg, G1CWC)) == 0x94);
+static_assert((offsetof (struct g1_if_reg, G1GDRC)) == 0xa0);
+static_assert((offsetof (struct g1_if_reg, G1GDWC)) == 0xa4);
+static_assert((offsetof (struct g1_if_reg, G1SYSM)) == 0xb0);
+static_assert((offsetof (struct g1_if_reg, G1CRDYC)) == 0xb4);
+static_assert((offsetof (struct g1_if_reg, GDAPRO)) == 0xb8);
+static_assert((offsetof (struct g1_if_reg, GDUNLOCK)) == 0xe4);
+static_assert((offsetof (struct g1_if_reg, GDSTARD)) == 0xf4);
+static_assert((offsetof (struct g1_if_reg, GDLEND)) == 0xf8);
+
+struct g2_if_reg {
+  reg32 ADSTAG;              /* ACIA:G2-DMA G2 start address */
+  reg32 ADSTAR;              /* ACIA:G2-DMA system memory start address */
+  reg32 ADLEN;               /* ACIA:G2-DMA length */
+  reg32 ADDIR;               /* ACIA:G2-DMA direction */
+  reg32 ADTSEL;              /* ACIA:G2-DMA trigger select */
+  reg32 ADEN;                /* ACIA:G2-DMA enable */
+  reg32 ADST;                /* ACIA:G2-DMA start */
+  reg32 ADSUSP;              /* ACIA:G2-DMA suspend */
+  reg32 E1STAG;              /* Ext1:G2-DMA start address */
+  reg32 E1STAR;              /* Ext1:G2-DMA system memory start address */
+  reg32 E1LEN;               /* Ext1:G2-DMA length */
+  reg32 E1DIR;               /* Ext1:G2-DMA direction */
+  reg32 E1TSEL;              /* Ext1:G2-DMA trigger select */
+  reg32 E1EN;                /* Ext1:G2-DMA enable */
+  reg32 E1ST;                /* Ext1:G2-DMA start */
+  reg32 E1SUSP;              /* Ext1:G2-DMA suspend */
+  reg32 E2STAG;              /* Ext2:G2-DMA start address */
+  reg32 E2STAR;              /* Ext2:G2-DMA system memory start address */
+  reg32 E2LEN;               /* Ext2:G2-DMA length */
+  reg32 E2DIR;               /* Ext2:G2-DMA direction */
+  reg32 E2TSEL;              /* Ext2:G2-DMA trigger select */
+  reg32 E2EN;                /* Ext2:G2-DMA enable */
+  reg32 E2ST;                /* Ext2:G2-DMA start */
+  reg32 E2SUSP;              /* Ext2:G2-DMA suspend */
+  reg32 DDSTAG;              /* Dev:G2-DMA start address */
+  reg32 DDSTAR;              /* Dev:G2-DMA system memory start address */
+  reg32 DDLEN;               /* Dev:G2-DMA length */
+  reg32 DDDIR;               /* Dev:G2-DMA direction */
+  reg32 DDTSEL;              /* Dev:G2-DMA trigger select */
+  reg32 DDEN;                /* Dev:G2-DMA enable */
+  reg32 DDST;                /* Dev:G2-DMA start */
+  reg32 DDSUSP;              /* Dev:G2-DMA suspend */
+  reg32 G2ID;                /* G2 bus version */
+  reg8  _pad0[12];
+  reg32 G2DSTO;              /* G2/DS timeout */
+  reg32 G2TRTO;              /* G2/TR timeout */
+  reg32 G2MDMTO;             /* Modem unit wait timeout */
+  reg32 G2MDMW;              /* Modem unit wait time */
+  reg8  _pad1[28];
+  reg32 G2APRO;              /* G2-DMA address range */
+  reg32 ADSTAGD;             /* AICA-DMA address counter (on AICA) */
+  reg32 ADSTARD;             /* AICA-DMA address counter (on root bus) */
+  reg32 ADLEND;              /* AICA-DMA transfer counter */
+  reg8  _pad2[4];
+  reg32 E1STAGD;             /* Ext-DMA1 address counter (on Ext) */
+  reg32 E1STARD;             /* Ext-DMA1 address counter (on root bus) */
+  reg32 E1LEND;              /* Ext-DMA1 transfer counter */
+  reg8  _pad3[4];
+  reg32 E2STAGD;             /* Ext-DMA2 address counter (on Ext) */
+  reg32 E2STARD;             /* Ext-DMA2 address counter (on root bus) */
+  reg32 E2LEND;              /* Ext-DMA2 transfer counter */
+  reg8  _pad4[4];
+  reg32 DDSTAGD;             /* Dev-DMA address counter (on Dev) */
+  reg32 DDSTARD;             /* Dev-DMA address counter (on root bus) */
+  reg32 DDLEND;              /* Dev-DMA transfer counter */
+};
+
+static_assert((offsetof (struct g2_if_reg, ADSTAG)) == 0x0);
+static_assert((offsetof (struct g2_if_reg, ADSTAR)) == 0x4);
+static_assert((offsetof (struct g2_if_reg, ADLEN)) == 0x8);
+static_assert((offsetof (struct g2_if_reg, ADDIR)) == 0xc);
+static_assert((offsetof (struct g2_if_reg, ADTSEL)) == 0x10);
+static_assert((offsetof (struct g2_if_reg, ADEN)) == 0x14);
+static_assert((offsetof (struct g2_if_reg, ADST)) == 0x18);
+static_assert((offsetof (struct g2_if_reg, ADSUSP)) == 0x1c);
+static_assert((offsetof (struct g2_if_reg, E1STAG)) == 0x20);
+static_assert((offsetof (struct g2_if_reg, E1STAR)) == 0x24);
+static_assert((offsetof (struct g2_if_reg, E1LEN)) == 0x28);
+static_assert((offsetof (struct g2_if_reg, E1DIR)) == 0x2c);
+static_assert((offsetof (struct g2_if_reg, E1TSEL)) == 0x30);
+static_assert((offsetof (struct g2_if_reg, E1EN)) == 0x34);
+static_assert((offsetof (struct g2_if_reg, E1ST)) == 0x38);
+static_assert((offsetof (struct g2_if_reg, E1SUSP)) == 0x3c);
+static_assert((offsetof (struct g2_if_reg, E2STAG)) == 0x40);
+static_assert((offsetof (struct g2_if_reg, E2STAR)) == 0x44);
+static_assert((offsetof (struct g2_if_reg, E2LEN)) == 0x48);
+static_assert((offsetof (struct g2_if_reg, E2DIR)) == 0x4c);
+static_assert((offsetof (struct g2_if_reg, E2TSEL)) == 0x50);
+static_assert((offsetof (struct g2_if_reg, E2EN)) == 0x54);
+static_assert((offsetof (struct g2_if_reg, E2ST)) == 0x58);
+static_assert((offsetof (struct g2_if_reg, E2SUSP)) == 0x5c);
+static_assert((offsetof (struct g2_if_reg, DDSTAG)) == 0x60);
+static_assert((offsetof (struct g2_if_reg, DDSTAR)) == 0x64);
+static_assert((offsetof (struct g2_if_reg, DDLEN)) == 0x68);
+static_assert((offsetof (struct g2_if_reg, DDDIR)) == 0x6c);
+static_assert((offsetof (struct g2_if_reg, DDTSEL)) == 0x70);
+static_assert((offsetof (struct g2_if_reg, DDEN)) == 0x74);
+static_assert((offsetof (struct g2_if_reg, DDST)) == 0x78);
+static_assert((offsetof (struct g2_if_reg, DDSUSP)) == 0x7c);
+static_assert((offsetof (struct g2_if_reg, G2ID)) == 0x80);
+static_assert((offsetof (struct g2_if_reg, G2DSTO)) == 0x90);
+static_assert((offsetof (struct g2_if_reg, G2TRTO)) == 0x94);
+static_assert((offsetof (struct g2_if_reg, G2MDMTO)) == 0x98);
+static_assert((offsetof (struct g2_if_reg, G2MDMW)) == 0x9c);
+static_assert((offsetof (struct g2_if_reg, G2APRO)) == 0xbc);
+static_assert((offsetof (struct g2_if_reg, ADSTAGD)) == 0xc0);
+static_assert((offsetof (struct g2_if_reg, ADSTARD)) == 0xc4);
+static_assert((offsetof (struct g2_if_reg, ADLEND)) == 0xc8);
+static_assert((offsetof (struct g2_if_reg, E1STAGD)) == 0xd0);
+static_assert((offsetof (struct g2_if_reg, E1STARD)) == 0xd4);
+static_assert((offsetof (struct g2_if_reg, E1LEND)) == 0xd8);
+static_assert((offsetof (struct g2_if_reg, E2STAGD)) == 0xe0);
+static_assert((offsetof (struct g2_if_reg, E2STARD)) == 0xe4);
+static_assert((offsetof (struct g2_if_reg, E2LEND)) == 0xe8);
+static_assert((offsetof (struct g2_if_reg, DDSTAGD)) == 0xf0);
+static_assert((offsetof (struct g2_if_reg, DDSTARD)) == 0xf4);
+static_assert((offsetof (struct g2_if_reg, DDLEND)) == 0xf8);
+
+struct pvr_if_reg {
+  reg32 PDSTAP;              /* PVR-DMA start address */
+  reg32 PDSTAR;              /* PVR-DMA system memory start address */
+  reg32 PDLEN;               /* PVR-DMA length */
+  reg32 PDDIR;               /* PVR-DMA direction */
+  reg32 PDTSEL;              /* PVR-DMA trigger select */
+  reg32 PDEN;                /* PVR-DMA enable */
+  reg32 PDST;                /* PVR-DMA start */
+  reg8  _pad0[100];
+  reg32 PDAPRO;              /* PVR-DMA address range */
+  reg8  _pad1[108];
+  reg32 PDSTAPD;             /* PVR-DMA address counter (on Ext) */
+  reg32 PDSTARD;             /* PVR-DMA address counter (on root bus) */
+  reg32 PDLEND;              /* PVR-DMA transfer counter */
+};
+
+static_assert((offsetof (struct pvr_if_reg, PDSTAP)) == 0x0);
+static_assert((offsetof (struct pvr_if_reg, PDSTAR)) == 0x4);
+static_assert((offsetof (struct pvr_if_reg, PDLEN)) == 0x8);
+static_assert((offsetof (struct pvr_if_reg, PDDIR)) == 0xc);
+static_assert((offsetof (struct pvr_if_reg, PDTSEL)) == 0x10);
+static_assert((offsetof (struct pvr_if_reg, PDEN)) == 0x14);
+static_assert((offsetof (struct pvr_if_reg, PDST)) == 0x18);
+static_assert((offsetof (struct pvr_if_reg, PDAPRO)) == 0x80);
+static_assert((offsetof (struct pvr_if_reg, PDSTAPD)) == 0xf0);
+static_assert((offsetof (struct pvr_if_reg, PDSTARD)) == 0xf4);
+static_assert((offsetof (struct pvr_if_reg, PDLEND)) == 0xf8);
+
+extern struct holly_reg holly __asm("holly");