diff --git a/.gitignore b/.gitignore
index a610673..fbee810 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,5 +9,6 @@ __pycache__
 *.cdi
 *.o
 *.out
+*.gch
 scramble
 cdi4dc
diff --git a/addresses.lds b/addresses.lds
index e4e20d5..a49809a 100644
--- a/addresses.lds
+++ b/addresses.lds
@@ -1,8 +1,4 @@
-sh7091_ic_a = 0xf0000000;
-sh7091_ic_d = 0xf1000000;
-sh7091_oc_a = 0xf4000000;
-sh7091_oc_d = 0xf5000000;
-sh7091 = 0xff000000;
+system_boot_rom = 0xa0000000;
 
 system = 0xa05f6800;
 maple_if = 0xa05f6c00;
@@ -12,8 +8,9 @@ g2_if = 0xa05f7800;
 pvr_if = 0xa05f7c00;
 holly = 0xa05f8000;
 modem = 0xa0600000;
+aica = 0xa0700000;
+aica_rtc = 0xa0710000;
 
-system_boot_rom = 0xa0000000;
 aica_wave_memory = 0xa0800000;
 texture_memory = 0xa5000000;
 system_memory = 0xac000000;
@@ -24,3 +21,9 @@ ta_fifo_polygon_converter_mirror = 0x12000000;
 ta_fifo_yuv_converter_mirror = 0x12800000;
 ta_fifo_texture_memory_mirror = 0x13000000;
 store_queue = 0xe0000000;
+
+sh7091_ic_a = 0xf0000000;
+sh7091_ic_d = 0xf1000000;
+sh7091_oc_a = 0xf4000000;
+sh7091_oc_d = 0xf5000000;
+sh7091 = 0xff000000;
diff --git a/aica.h b/aica.h
new file mode 100644
index 0000000..64b856f
--- /dev/null
+++ b/aica.h
@@ -0,0 +1 @@
+extern reg32 aica[0x8000] __asm("aica");
diff --git a/holly/core_bits.h b/holly/core_bits.h
new file mode 100644
index 0000000..f114bd5
--- /dev/null
+++ b/holly/core_bits.h
@@ -0,0 +1,453 @@
+#include <cstdint>
+
+#include "float_uint32.h"
+
+namespace id {
+  constexpr uint32_t device_id(uint32_t reg) { return (reg >> 16) & 0xffff; }
+  constexpr uint32_t vendor_id(uint32_t reg) { return (reg >> 0) & 0xffff; }
+}
+
+namespace revision {
+  constexpr uint32_t chip_revision(uint32_t reg) { return (reg >> 0) & 0xffff; }
+}
+
+namespace softreset {
+  constexpr uint32_t sdram_if_soft_reset = 1 << 2;
+  constexpr uint32_t pipeline_soft_reset = 1 << 1;
+  constexpr uint32_t ta_soft_reset = 1 << 0;
+}
+
+namespace startrender {
+  constexpr uint32_t start_render = 1 << 0;
+}
+
+namespace test_select {
+  constexpr uint32_t diagdb_data(uint32_t reg) { return (reg >> 5) & 0x1f; }
+  constexpr uint32_t diagda_data(uint32_t reg) { return (reg >> 0) & 0x1f; }
+}
+
+namespace param_base {
+  constexpr uint32_t base_address(uint32_t num) { return (num & 0xf00000) << 0; }
+}
+
+namespace region_base {
+  constexpr uint32_t base_address(uint32_t num) { return (num & 0xfffffc) << 0; }
+}
+
+namespace span_sort_cfg {
+  constexpr uint32_t cache_bypass = 1 << 16;
+  constexpr uint32_t offset_sort_enable = 1 << 8;
+  constexpr uint32_t span_sort_enable = 1 << 0;
+}
+
+namespace vo_border_col {
+  constexpr uint32_t chroma(uint32_t num) { return (num & 0x1) << 24; }
+  constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+  constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace fb_r_ctrl {
+  namespace vclk_div {
+    constexpr uint32_t pclk_vclk_2 = 0 << 23;
+    constexpr uint32_t pclk_vclk_1 = 1 << 23;
+  }
+  
+  constexpr uint32_t fb_strip_buf_en = 1 << 22;
+  constexpr uint32_t fb_stripsize(uint32_t num) { return (num & 0x3e) << 16; }
+  constexpr uint32_t fb_chroma_threshold(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t fb_concat(uint32_t num) { return (num & 0x3) << 4; }
+  
+  namespace fb_depth {
+    constexpr uint32_t _0555_rgb_16bit = 0 << 2;
+    constexpr uint32_t _0565_rgb_16bit = 1 << 2;
+    constexpr uint32_t _888_rgb_24bit_packed = 2 << 2;
+    constexpr uint32_t _0888_rgb_32bit = 3 << 2;
+  }
+  
+  constexpr uint32_t fb_line_double = 1 << 1;
+  constexpr uint32_t fb_enable = 1 << 0;
+}
+
+namespace fb_w_ctrl {
+  constexpr uint32_t fb_alpha_threshold(uint32_t num) { return (num & 0xff) << 16; }
+  constexpr uint32_t fb_kval(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t fb_dither = 1 << 3;
+  
+  namespace fb_packmode {
+    constexpr uint32_t _0555_krgb_16bit = 0 << 0;
+    constexpr uint32_t _565_rgb_16bit = 1 << 0;
+    constexpr uint32_t _4444_argb_16bit = 2 << 0;
+    constexpr uint32_t _1555_argb_16bit = 3 << 0;
+    constexpr uint32_t _888_rgb_24bit_packed = 4 << 0;
+    constexpr uint32_t _0888_krgb_32bit = 5 << 0;
+    constexpr uint32_t _8888_argb_32bit = 6 << 0;
+  }
+}
+
+namespace fb_w_linestride {
+  constexpr uint32_t fb_line_stride(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace fb_r_sof1 {
+  constexpr uint32_t frame_buffer_read_address_frame_1(uint32_t num) { return (num & 0xfffffc) << 0; }
+}
+
+namespace fb_r_sof2 {
+  constexpr uint32_t frame_buffer_read_address_frame_2(uint32_t num) { return (num & 0xfffffc) << 0; }
+}
+
+namespace fb_r_size {
+  constexpr uint32_t fb_modulus(uint32_t num) { return (num & 0x3ff) << 20; }
+  constexpr uint32_t fb_y_size(uint32_t num) { return (num & 0x3ff) << 10; }
+  constexpr uint32_t fb_x_size(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace fb_w_sof1 {
+  constexpr uint32_t frame_buffer_write_address_frame_1(uint32_t num) { return (num & 0x1fffffc) << 0; }
+}
+
+namespace fb_w_sof2 {
+  constexpr uint32_t frame_buffer_write_address_frame_2(uint32_t num) { return (num & 0x1fffffc) << 0; }
+}
+
+namespace fb_x_clip {
+  constexpr uint32_t fb_x_clip_max(uint32_t num) { return (num & 0x7ff) << 16; }
+  constexpr uint32_t fb_x_clip_min(uint32_t num) { return (num & 0x7ff) << 0; }
+}
+
+namespace fb_y_clip {
+  constexpr uint32_t fb_y_clip_max(uint32_t num) { return (num & 0x3ff) << 16; }
+  constexpr uint32_t fb_y_clip_min(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace fpu_shad_scale {
+  namespace simple_shadow_enable {
+    constexpr uint32_t parameter_selection_volume_mode = 0 << 8;
+    constexpr uint32_t intensity_volume_mode = 1 << 8;
+  }
+  
+  constexpr uint32_t scale_factor_for_shadows(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace fpu_cull_val {
+  constexpr uint32_t culling_comparison_value(float num) { return _i(__builtin_fabsf(num));; }
+}
+
+namespace fpu_param_cfg {
+  namespace region_header_type {
+    constexpr uint32_t type_1 = 0 << 21;
+    constexpr uint32_t type_2 = 1 << 21;
+  }
+  
+  constexpr uint32_t tsp_parameter_burst_threshold(uint32_t num) { return (num & 0x3f) << 14; }
+  constexpr uint32_t isp_parameter_burst_threshold(uint32_t num) { return (num & 0x3f) << 8; }
+  constexpr uint32_t pointer_burst_size(uint32_t num) { return (num & 0xf) << 4; }
+  constexpr uint32_t pointer_first_burst_size(uint32_t num) { return (num & 0xf) << 0; }
+}
+
+namespace half_offset {
+  namespace tsp_texel_sampling_position {
+    constexpr uint32_t top_left(uint32_t reg) { return (reg >> 2) & 0x1; }
+    constexpr uint32_t center(uint32_t reg) { return (reg >> 2) & 0x1; }
+  }
+  
+  namespace tsp_pixel_sampling_position {
+    constexpr uint32_t top_left(uint32_t reg) { return (reg >> 1) & 0x1; }
+    constexpr uint32_t center(uint32_t reg) { return (reg >> 1) & 0x1; }
+  }
+  
+  namespace fpu_pixel_sampling_position {
+    constexpr uint32_t top_left(uint32_t reg) { return (reg >> 0) & 0x1; }
+    constexpr uint32_t center(uint32_t reg) { return (reg >> 0) & 0x1; }
+  }
+}
+
+namespace fpu_perp_val {
+  constexpr uint32_t perpendicular_triangle_compare(float num) { return _i(__builtin_fabsf(num));; }
+}
+
+namespace isp_backgnd_d {
+  constexpr uint32_t background_plane_depth(float num) { return _i(num) & 0xfffffff0; }
+}
+
+namespace isp_backgnd_t {
+  constexpr uint32_t cache_bypass = 1 << 28;
+  constexpr uint32_t shadow = 1 << 27;
+  constexpr uint32_t skip(uint32_t num) { return (num & 0x7) << 24; }
+  constexpr uint32_t tag_address(uint32_t num) { return (num & 0x1fffff) << 3; }
+  constexpr uint32_t tag_offset(uint32_t num) { return (num & 0x7) << 0; }
+}
+
+namespace isp_feed_cfg {
+  constexpr uint32_t cache_size_for_translucency(uint32_t num) { return (num & 0x3ff) << 14; }
+  constexpr uint32_t punch_through_chunk_size(uint32_t num) { return (num & 0x3ff) << 4; }
+  constexpr uint32_t discard_mode = 1 << 3;
+  constexpr uint32_t pre_sort_mode = 1 << 0;
+}
+
+namespace sdram_refresh {
+  constexpr uint32_t refresh_counter_value(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace sdram_arb_cfg {
+  namespace override_value {
+    constexpr uint32_t priority_only = 0x0 << 18;
+    constexpr uint32_t rendered_data = 0x1 << 18;
+    constexpr uint32_t texture_vq_index = 0x2 << 18;
+    constexpr uint32_t texture_normal_data_and_vq_codebook = 0x3 << 18;
+    constexpr uint32_t tile_accelerator_isp_tsp_data = 0x4 << 18;
+    constexpr uint32_t tile_accelerator_pointers = 0x5 << 18;
+    constexpr uint32_t sh4 = 0x6 << 18;
+    constexpr uint32_t tsp_parameters = 0x7 << 18;
+    constexpr uint32_t tsp_region_data = 0x8 << 18;
+    constexpr uint32_t isp_pointer_data = 0x9 << 18;
+    constexpr uint32_t isp_parameters = 0xa << 18;
+    constexpr uint32_t crt_controller = 0xb << 18;
+  }
+  
+  namespace arbiter_priority_control {
+    constexpr uint32_t priority_arbitration_only = 0x0 << 16;
+    constexpr uint32_t override_value_field = 0x1 << 16;
+    constexpr uint32_t round_robin_counter = 0x2 << 16;
+  }
+  
+  constexpr uint32_t arbiter_crt_page_break_latency_count_value(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t arbiter_page_break_latency_count_value(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace sdram_cfg {
+  constexpr uint32_t read_command_to_returned_data_delay(uint32_t num) { return (num & 0x7) << 26; }
+  constexpr uint32_t cas_latency_value(uint32_t num) { return (num & 0x7) << 23; }
+  constexpr uint32_t activate_to_activate_period(uint32_t num) { return (num & 0x3) << 21; }
+  constexpr uint32_t read_to_write_period(uint32_t num) { return (num & 0x7) << 18; }
+  constexpr uint32_t refresh_to_activate_period(uint32_t num) { return (num & 0xf) << 14; }
+  constexpr uint32_t pre_charge_to_activate_period(uint32_t num) { return (num & 0x3) << 10; }
+  constexpr uint32_t activate_to_pre_charge_period(uint32_t num) { return (num & 0xf) << 6; }
+  constexpr uint32_t activate_to_read_write_command_period(uint32_t num) { return (num & 0x3) << 4; }
+  constexpr uint32_t write_to_pre_charge_period(uint32_t num) { return (num & 0x3) << 2; }
+  constexpr uint32_t read_to_pre_charge_period(uint32_t num) { return (num & 0x3) << 0; }
+}
+
+namespace fog_col_ram {
+  constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+  constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace fog_col_vert {
+  constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+  constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace fog_density {
+  constexpr uint32_t fog_scale_mantissa(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t fog_scale_exponent(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace fog_clamp_max {
+  constexpr uint32_t alpha(uint32_t num) { return (num & 0xff) << 24; }
+  constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+  constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace fog_clamp_min {
+  constexpr uint32_t alpha(uint32_t num) { return (num & 0xff) << 24; }
+  constexpr uint32_t red(uint32_t num) { return (num & 0xff) << 16; }
+  constexpr uint32_t green(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t blue(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace spg_trigger_pos {
+  constexpr uint32_t trigger_v_count(uint32_t reg) { return (reg >> 16) & 0x3ff; }
+  constexpr uint32_t trigger_h_count(uint32_t reg) { return (reg >> 0) & 0x3ff; }
+}
+
+namespace spg_hblank_int {
+  constexpr uint32_t hblank_in_interrupt(uint32_t reg) { return (reg >> 16) & 0x3ff; }
+  
+  namespace hblank_int_mode {
+    constexpr uint32_t output_equal_line_comp_val = 0x0 << 12;
+    constexpr uint32_t output_every_line_comp_val = 0x1 << 12;
+    constexpr uint32_t output_every_line = 0x2 << 12;
+  }
+  
+  constexpr uint32_t line_comp_val(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace spg_vblank_int {
+  constexpr uint32_t vblank_out_interrupt_line_number(uint32_t num) { return (num & 0x3ff) << 16; }
+  constexpr uint32_t vblank_in_interrupt_line_number(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace spg_control {
+  namespace csync_on_h {
+    constexpr uint32_t hsync = 0 << 9;
+    constexpr uint32_t csync = 1 << 9;
+  }
+  
+  namespace sync_direction {
+    constexpr uint32_t input = 0 << 8;
+    constexpr uint32_t output = 1 << 8;
+  }
+  
+  constexpr uint32_t pal = 1 << 7;
+  constexpr uint32_t ntsc = 1 << 6;
+  constexpr uint32_t force_field2 = 1 << 5;
+  constexpr uint32_t interlace = 1 << 4;
+  constexpr uint32_t spg_lock = 1 << 3;
+  
+  namespace mcsync_pol {
+    constexpr uint32_t active_low = 0 << 2;
+    constexpr uint32_t active_high = 1 << 2;
+  }
+  
+  namespace mvsync_pol {
+    constexpr uint32_t active_low = 0 << 1;
+    constexpr uint32_t active_high = 1 << 1;
+  }
+  
+  namespace mhsync_pol {
+    constexpr uint32_t active_low = 0 << 0;
+    constexpr uint32_t active_high = 1 << 0;
+  }
+}
+
+namespace spg_hblank {
+  constexpr uint32_t hbend(uint32_t num) { return (num & 0x3ff) << 16; }
+  constexpr uint32_t hbstart(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace spg_load {
+  constexpr uint32_t vcount(uint32_t num) { return (num & 0x3ff) << 16; }
+  constexpr uint32_t hcount(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace spg_vblank {
+  constexpr uint32_t vbend(uint32_t num) { return (num & 0x3ff) << 16; }
+  constexpr uint32_t vbstart(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace spg_width {
+  constexpr uint32_t eqwidth(uint32_t num) { return (num & 0x3ff) << 22; }
+  constexpr uint32_t bpwidth(uint32_t num) { return (num & 0x3ff) << 12; }
+  constexpr uint32_t vswidth(uint32_t num) { return (num & 0xf) << 8; }
+  constexpr uint32_t hswidth(uint32_t num) { return (num & 0x7f) << 0; }
+}
+
+namespace text_control {
+  namespace code_book_endian {
+    constexpr uint32_t little_endian = 0 << 17;
+    constexpr uint32_t big_endian = 1 << 17;
+  }
+  
+  namespace index_endian {
+    constexpr uint32_t little_endian = 0 << 16;
+    constexpr uint32_t big_endian = 1 << 16;
+  }
+  
+  constexpr uint32_t bank_bit(uint32_t num) { return (num & 0x1f) << 8; }
+  constexpr uint32_t stride(uint32_t num) { return (num & 0x1f) << 0; }
+}
+
+namespace vo_control {
+  constexpr uint32_t pclk_delay_reset = 1 << 21;
+  constexpr uint32_t pclk_delay(uint32_t num) { return (num & 0xf) << 16; }
+  constexpr uint32_t pixel_double = 1 << 8;
+  
+  namespace field_mode {
+    constexpr uint32_t use_field_flag_from_spg = 0x0 << 4;
+    constexpr uint32_t use_inverse_of_field_flag_from_spg = 0x1 << 4;
+    constexpr uint32_t field_1_fixed = 0x2 << 4;
+    constexpr uint32_t field_2_fixed = 0x3 << 4;
+    constexpr uint32_t field_1_when_the_active_edges_of_hsync_and_vsync_match = 0x4 << 4;
+    constexpr uint32_t field_2_when_the_active_edges_of_hsync_and_vsync_match = 0x5 << 4;
+    constexpr uint32_t field_1_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge = 0x6 << 4;
+    constexpr uint32_t field_2_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge = 0x7 << 4;
+    constexpr uint32_t inverted_at_the_active_edge_of_vsync = 0x8 << 4;
+  }
+  
+  constexpr uint32_t blank_video = 1 << 3;
+  
+  namespace blank_pol {
+    constexpr uint32_t active_low = 0 << 2;
+    constexpr uint32_t active_high = 1 << 2;
+  }
+  
+  namespace vsync_pol {
+    constexpr uint32_t active_low = 0 << 1;
+    constexpr uint32_t active_high = 1 << 1;
+  }
+  
+  namespace hsync_pol {
+    constexpr uint32_t active_low = 0 << 0;
+    constexpr uint32_t active_high = 1 << 0;
+  }
+}
+
+namespace vo_startx {
+  constexpr uint32_t horizontal_start_position(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace vo_starty {
+  constexpr uint32_t vertical_start_position_on_field_2(uint32_t num) { return (num & 0x3ff) << 16; }
+  constexpr uint32_t vertical_start_position_on_field_1(uint32_t num) { return (num & 0x3ff) << 0; }
+}
+
+namespace scaler_ctl {
+  namespace field_select {
+    constexpr uint32_t field_1 = 0 << 18;
+    constexpr uint32_t field_2 = 1 << 18;
+  }
+  
+  constexpr uint32_t interlace = 1 << 17;
+  constexpr uint32_t horizontal_scaling_enable = 1 << 16;
+  constexpr uint32_t vertical_scale_factor(uint32_t num) { return (num & 0xffff) << 0; }
+}
+
+namespace pal_ram_ctl {
+  namespace pixel_format {
+    constexpr uint32_t argb1555 = 0 << 0;
+    constexpr uint32_t rgb565 = 1 << 0;
+    constexpr uint32_t argb4444 = 2 << 0;
+    constexpr uint32_t argb8888 = 3 << 0;
+  }
+}
+
+namespace spg_status {
+  constexpr uint32_t vsync(uint32_t reg) { return (reg >> 13) & 0x1; }
+  constexpr uint32_t hsync(uint32_t reg) { return (reg >> 12) & 0x1; }
+  constexpr uint32_t blank(uint32_t reg) { return (reg >> 11) & 0x1; }
+  constexpr uint32_t fieldnum(uint32_t reg) { return (reg >> 10) & 0x1; }
+  constexpr uint32_t scanline(uint32_t reg) { return (reg >> 0) & 0x3ff; }
+}
+
+namespace fb_burstctrl {
+  constexpr uint32_t wr_burst(uint32_t num) { return (num & 0xf) << 16; }
+  constexpr uint32_t vid_lat(uint32_t num) { return (num & 0x7f) << 8; }
+  constexpr uint32_t vid_burst(uint32_t num) { return (num & 0x3f) << 0; }
+}
+
+namespace fb_c_sof {
+  constexpr uint32_t frame_buffer_current_read_address(uint32_t reg) { return (reg >> 0) & 0xffffff; }
+}
+
+namespace y_coeff {
+  constexpr uint32_t coefficient_1(uint32_t num) { return (num & 0xff) << 8; }
+  constexpr uint32_t coefficient_0_2(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace pt_alpha_ref {
+  constexpr uint32_t alpha_reference_for_punch_through(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace fog_table {
+  constexpr uint32_t fog_table_data(uint32_t num) { return (num & 0xffff) << 0; }
+}
+
+namespace palette_ram {
+  constexpr uint32_t palette_data(uint32_t num) { return (num & 0xffffffff) << 0; }
+}
+
diff --git a/holly/ta_bits.h b/holly/ta_bits.h
new file mode 100644
index 0000000..04b2917
--- /dev/null
+++ b/holly/ta_bits.h
@@ -0,0 +1,120 @@
+#include <cstdint>
+
+#include "float_uint32.h"
+
+namespace ta_ol_base {
+  constexpr uint32_t base_address(uint32_t num) { return (num & 0xffffe0) << 0; }
+}
+
+namespace ta_isp_base {
+  constexpr uint32_t base_address(uint32_t num) { return (num & 0xfffffc) << 0; }
+}
+
+namespace ta_ol_limit {
+  constexpr uint32_t limit_address(uint32_t num) { return (num & 0xffffe0) << 0; }
+}
+
+namespace ta_isp_limit {
+  constexpr uint32_t limit_address(uint32_t num) { return (num & 0xfffffc) << 0; }
+}
+
+namespace ta_next_opb {
+  constexpr uint32_t address(uint32_t num) { return (num & 0xffffe0) << 0; }
+}
+
+namespace ta_itp_current {
+  constexpr uint32_t address(uint32_t reg) { return (reg >> 0) & 0xffffff; }
+}
+
+namespace ta_glob_tile_clip {
+  constexpr uint32_t tile_y_num(uint32_t num) { return (num & 0xf) << 16; }
+  constexpr uint32_t tile_x_num(uint32_t num) { return (num & 0x1f) << 0; }
+}
+
+namespace ta_alloc_ctrl {
+  namespace opb_mode {
+    constexpr uint32_t decreasing_addresses = 0 << 20;
+    constexpr uint32_t increasing_addresses = 1 << 20;
+  }
+  
+  namespace pt_opb {
+    constexpr uint32_t no_list = 0 << 16;
+    constexpr uint32_t _8x4byte = 1 << 16;
+    constexpr uint32_t _16x4byte = 2 << 16;
+    constexpr uint32_t _32x4byte = 3 << 16;
+  }
+  
+  namespace tm_opb {
+    constexpr uint32_t no_list = 0 << 12;
+    constexpr uint32_t _8x4byte = 1 << 12;
+    constexpr uint32_t _16x4byte = 2 << 12;
+    constexpr uint32_t _32x4byte = 3 << 12;
+  }
+  
+  namespace t_opb {
+    constexpr uint32_t no_list = 0 << 8;
+    constexpr uint32_t _8x4byte = 1 << 8;
+    constexpr uint32_t _16x4byte = 2 << 8;
+    constexpr uint32_t _32x4byte = 3 << 8;
+  }
+  
+  namespace om_opb {
+    constexpr uint32_t no_list = 0 << 4;
+    constexpr uint32_t _8x4byte = 1 << 4;
+    constexpr uint32_t _16x4byte = 2 << 4;
+    constexpr uint32_t _32x4byte = 3 << 4;
+  }
+  
+  namespace o_opb {
+    constexpr uint32_t no_list = 0 << 0;
+    constexpr uint32_t _8x4byte = 1 << 0;
+    constexpr uint32_t _16x4byte = 2 << 0;
+    constexpr uint32_t _32x4byte = 3 << 0;
+  }
+}
+
+namespace ta_list_init {
+  constexpr uint32_t list_init = 1 << 31;
+}
+
+namespace ta_yuv_tex_base {
+  constexpr uint32_t base_address(uint32_t num) { return (num & 0xfffff8) << 0; }
+}
+
+namespace ta_yuv_tex_ctrl {
+  namespace yuv_form {
+    constexpr uint32_t yuv420 = 0 << 24;
+    constexpr uint32_t yuv422 = 1 << 24;
+  }
+  
+  namespace yuv_tex {
+    constexpr uint32_t one_texture = 0 << 16;
+    constexpr uint32_t multiple_textures = 1 << 16;
+  }
+  
+  constexpr uint32_t yuv_v_size(uint32_t num) { return (num & 0x3f) << 8; }
+  constexpr uint32_t yuv_u_size(uint32_t num) { return (num & 0x3f) << 0; }
+}
+
+namespace ta_yuv_tex_cnt {
+  constexpr uint32_t yuv_num(uint32_t reg) { return (reg >> 0) & 0x1fff; }
+}
+
+namespace ta_list_cont {
+  constexpr uint32_t list_cont = 1 << 31;
+}
+
+namespace ta_next_opb_init {
+  constexpr uint32_t address(uint32_t num) { return (num & 0xffffe0) << 0; }
+}
+
+namespace ta_ol_pointers {
+  constexpr uint32_t entry(uint32_t reg) { return (reg >> 31) & 0x1; }
+  constexpr uint32_t sprite(uint32_t reg) { return (reg >> 30) & 0x1; }
+  constexpr uint32_t triangle(uint32_t reg) { return (reg >> 29) & 0x1; }
+  constexpr uint32_t number_of_triangles_quads(uint32_t reg) { return (reg >> 25) & 0xf; }
+  constexpr uint32_t shadow(uint32_t reg) { return (reg >> 24) & 0x1; }
+  constexpr uint32_t pointer_address(uint32_t reg) { return (reg >> 2) & 0x3fffff; }
+  constexpr uint32_t skip(uint32_t reg) { return (reg >> 0) & 0x3; }
+}
+
diff --git a/maple-notes.txt b/maple-notes.txt
new file mode 100644
index 0000000..debb191
--- /dev/null
+++ b/maple-notes.txt
@@ -0,0 +1,52 @@
+KAEDE/Mpglobal.h
+KAEDE/MPDRV_.C
+KAEDE/MPAPI_.C
+
+MAPLE82E.pdf Chapter 6 "COMMAND REFERENCE"
+
+jargon:
+
+AP - Absolute Position ; MAPLE82E.pdf page 13
+
+(Address)    (Data)
+0x0C700000 → 0x00000000 Port 0, 4-byte data transmission (instruction to Maple-Host)
+0x0C700004 → 0x0C800000 Port 0, reception data storage address (instruction to Maple-Host)
+0x0C700008 → 0x01200000 [Device Request], transfer destination AP: 0x20, transfer source AP: 0x00
+0x0C70000C → 0x00010000 Port 1, 4-byte data transmission
+0x0C700010 → 0x0C800100 Port 1, reception data storage address
+0x0C700014 → 0x01604000 [Device Request], transfer destination AP: 0x60, transfer source AP: 0x40
+0x0C700018 → 0x00020000 Port 2, 4-byte data transmission
+0x0C70001C → 0x0C800200 Port 2, reception data storage address
+0x0C700020 → 0x01A08000 [Device Request], transfer destination AP: 0xA0, transfer source AP: 0x80
+0x0C700024 → 0x80030000 Port 3, 4-byte data transmission
+0x0C700028 → 0x0C800300 Port 3, reception data storage address 
+0x0C70002C → 0x01E0C000 [Device Request], transfer destination AP: 0xE0, transfer source AP: 0xC0
+
+---
+
+(Specified reception data storage address: 0x0C800000)
+0x0C800000 → 0x0500201C [Device Status], transfer destination AP:00, transfer source AP:20
+0x0C800004 → 0x00000001 112 bytes of fixed data follows � �
+0x0C800070 → 0x00000000
+0x0C800000 → 0xFFFFFFFF No connection
+0x0C800000 → 0xFFFFFF00 Reception data error
+
+----
+
+(Address)    (Data)
+0x0C700000 → 0x00000001 Port 0, 8-byte data transmission (instruction to Maple-Host)
+0x0C700004 → 0x0C800000 Port 0, reception data storage address (instruction to Maple-Host)
+0x0C700008 → 0x09200001 [Get Condition], transfer destination AP: 0x20, transfer source AP: 0x00
+0x0C70000C → 0x00000001 Function type
+0x0C700010 → 0x00010001 Port 2, 8-byte data transmission
+0x0C700014 → 0x0C800100 Port1, reception data storage address
+0x0C700018 → 0x09604001 [Get Condition], transfer destination AP:0x60, transfer source AP:0x40
+0x0C70001C → 0x00000001 Function Type
+0x0C700020 → 0x00020001 Port 2, 8-byte data transmission
+0x0C700024 → 0x0C800200 Port 2, reception data storage address
+0x0C700028 → 0x09A08001 [Get Condition], transfer destination AP: 0x80, transfer source AP: 0xA0
+0x0C70002C → 0x00000001 Function type
+0x0C700030 → 0x80030001 command list end Port 3, 8-byte data transmission,
+0x0C700034 → 0x0C800300 Port 3, reception data storage address
+0x0C700038 → 0x09E0C001 [Get Condition], transfer destination AP: 0xC0, transfer source AP: 0xE0
+0x0C70003C → 0x00000001 Function Type
diff --git a/regs/core_bits.csv b/regs/core_bits.csv
index aafec82..d70f83b 100644
--- a/regs/core_bits.csv
+++ b/regs/core_bits.csv
@@ -1,265 +1,264 @@
-"register_name","enum_name","bits","bit_name","value","mask","description"
-"ID",,"31-16","device_id",,,
-"ID",,"15-0","vendor_id",,,
-,,,,,,
-"REVISION",,"15-0","chip_revision",,,
-,,,,,,
-"SOFTRESET",,2,"sdram_if_soft_reset",1,,
-"SOFTRESET",,1,"pipeline_soft_reset",1,,
-"SOFTRESET",,0,"ta_soft_reset",1,,
-,,,,,,
-"STARTRENDER",,0,"start_render",1,,
-,,,,,,
-"TEST_SELECT",,"9-5","diagdb_data",,,
-"TEST_SELECT",,"4-0","diagda_data",,,
-,,,,,,
-"PARAM_BASE",,"23-0","base_address",,"0xf00000",
-,,,,,,
-"REGION_BASE",,"23-0","base_address",,"0xfffffc",
-,,,,,,
-"SPAN_SORT_CFG",,16,"cache_bypass",1,,
-"SPAN_SORT_CFG",,8,"offset_sort_enable",1,,
-"SPAN_SORT_CFG",,0,"span_sort_enable",1,,
-,,,,,,
-"VO_BORDER_COL",,24,"chroma",,"0b1",
-"VO_BORDER_COL",,"23-16","red",,"0xff",
-"VO_BORDER_COL",,"15-8","green",,"0xff",
-"VO_BORDER_COL",,"7-0","blue",,"0xff",
-,,,,,,
-"FB_R_CTRL","vclk_div",23,"pclk_vclk_2",0,,
-"FB_R_CTRL","vclk_div",23,"pclk_vclk_1",1,,
-"FB_R_CTRL",,22,"fb_strip_buf_en",1,,
-"FB_R_CTRL",,"21-16","fb_stripsize",,"0b111_110","In units of 16 lines, in multiples of 32 lines. 0x02 is 32 lines, 0x04 is 64 lines, 0x03 is an illegal value"
-"FB_R_CTRL",,"15-8","fb_chroma_threshold",,"0xff",
-"FB_R_CTRL",,"6-4","fb_concat",,"0b11",
-"FB_R_CTRL","fb_depth","3-2","0555_RGB_16BIT",0,,
-"FB_R_CTRL","fb_depth","3-2","0565_RGB_16BIT",1,,
-"FB_R_CTRL","fb_depth","3-2","888_RGB_24BIT_PACKED",2,,
-"FB_R_CTRL","fb_depth","3-2","0888_RGB_32BIT",3,,
-"FB_R_CTRL",,1,"fb_line_double",1,,
-"FB_R_CTRL",,0,"fb_enable",1,,
-,,,,,,
-"FB_W_CTRL",,"23-16","fb_alpha_threshold",,"0xff",
-"FB_W_CTRL",,"15-8","fb_kval",,"0xff",
-"FB_W_CTRL",,3,"fb_dither",1,,
-"FB_W_CTRL","fb_packmode","2-0","0555_krgb_16bit",0,,
-"FB_W_CTRL","fb_packmode","2-0","565_rgb_16bit",1,,
-"FB_W_CTRL","fb_packmode","2-0","4444_argb_16bit",2,,
-"FB_W_CTRL","fb_packmode","2-0","1555_argb_16bit",3,,
-"FB_W_CTRL","fb_packmode","2-0","888_rgb_24bit_packed",4,,
-"FB_W_CTRL","fb_packmode","2-0","0888_krgb_32bit",5,,
-"FB_W_CTRL","fb_packmode","2-0","8888_argb_32bit",6,,
-,,,,,,
-"FB_W_LINESTRIDE",,"8-0","fb_line_stride",,"0xff","In 8-byte units"
-,,,,,,
-"FB_R_SOF1",,"23-0","frame_buffer_read_address_frame_1",,"0xfffffc",
-,,,,,,
-"FB_R_SOF2",,"23-0","frame_buffer_read_address_frame_2",,"0xfffffc",
-,,,,,,
-"FB_R_SIZE",,"29-20","fb_modulus",,"0x3ff","In 4-byte units"
-"FB_R_SIZE",,"19-10","fb_y_size",,"0x3ff",
-"FB_R_SIZE",,"9-0","fb_x_size",,"0x3ff",
-,,,,,,
-"FB_W_SOF1",,"24-0","frame_buffer_write_address_frame_1",,"0x1fffffc",
-,,,,,,
-"FB_W_SOF2",,"24-0","frame_buffer_write_address_frame_2",,"0x1fffffc",
-,,,,,,
-"FB_X_CLIP",,"26-16","fb_x_clip_max",,"0x7ff",
-"FB_X_CLIP",,"10-0","fb_x_clip_min",,"0x7ff",
-,,,,,,
-"FB_Y_CLIP",,"25-16","fb_y_clip_max",,"0x3ff",
-"FB_Y_CLIP",,"9-0","fb_y_clip_min",,"0x3ff",
-,,,,,,
-"FPU_SHAD_SCALE","simple_shadow_enable",8,"parameter_selection_volume_mode",0,,
-"FPU_SHAD_SCALE","simple_shadow_enable",8,"intensity_volume_mode",1,,
-"FPU_SHAD_SCALE",,"7-0","scale_factor_for_shadows",,"0xff",
-,,,,,,
-"FPU_CULL_VAL",,"30-0","culling_comparison_value",,"float_0_8_23",
-,,,,,,
-"FPU_PARAM_CFG","region_header_type",21,"type_1",0,,
-"FPU_PARAM_CFG","region_header_type",21,"type_2",1,,
-"FPU_PARAM_CFG",,"19-14","tsp_parameter_burst_threshold",,"0x3f",
-"FPU_PARAM_CFG",,"13-8","isp_parameter_burst_threshold",,"0x3f",
-"FPU_PARAM_CFG",,"7-4","pointer_burst_size",,"0xf",
-"FPU_PARAM_CFG",,"3-0","pointer_first_burst_size",,"0xf",
-,,,,,,
-"HALF_OFFSET","tsp_texel_sampling_position",2,"top_left",,,
-"HALF_OFFSET","tsp_texel_sampling_position",2,"center",,,
-"HALF_OFFSET","tsp_pixel_sampling_position",1,"top_left",,,
-"HALF_OFFSET","tsp_pixel_sampling_position",1,"center",,,
-"HALF_OFFSET","fpu_pixel_sampling_position",0,"top_left",,,
-"HALF_OFFSET","fpu_pixel_sampling_position",0,"center",,,
-,,,,,,
-"FPU_PERP_VAL",,"30-0","perpendicular_triangle_compare",,"float_0_8_23",
-,,,,,,
-"ISP_BACKGND_D",,"31-4","background_plane_depth",,"float_1_8_19",
-,,,,,,
-"ISP_BACKGND_T",,28,"cache_bypass",1,,
-"ISP_BACKGND_T",,27,"shadow",1,,
-"ISP_BACKGND_T",,"26-24","skip",,"0b111",
-"ISP_BACKGND_T",,"23-3","tag_address",,"0x1fffff","In 32-bit units"
-"ISP_BACKGND_T",,"2-0","tag_offset",,"0b111",
-,,,,,,
-"ISP_FEED_CFG",,"23-14","cache_size_for_translucency",,"0x3ff","Must be between 0x020 and 0x200"
-"ISP_FEED_CFG",,"13-4","punch_through_chunk_size",,"0x3ff","Must be between 0x020 and 0x200, must be larger than cache_size_for_translucency"
-"ISP_FEED_CFG",,3,"discard_mode",1,,
-"ISP_FEED_CFG",,0,"pre_sort_mode",1,,
-,,,,,,
-"SDRAM_REFRESH",,"7-0","refresh_counter_value",,"0xff",
-,,,,,,
-"SDRAM_ARB_CFG","override_value","21-18","priority_only","0x0",,
-"SDRAM_ARB_CFG","override_value","21-18","rendered_data","0x1",,
-"SDRAM_ARB_CFG","override_value","21-18","texture_vq_index","0x2",,
-"SDRAM_ARB_CFG","override_value","21-18","texture_normal_data_and_vq_codebook","0x3",,
-"SDRAM_ARB_CFG","override_value","21-18","tile_accelerator_isp_tsp_data","0x4",,
-"SDRAM_ARB_CFG","override_value","21-18","tile_accelerator_pointers","0x5",,
-"SDRAM_ARB_CFG","override_value","21-18","sh4","0x6",,
-"SDRAM_ARB_CFG","override_value","21-18","tsp_parameters","0x7",,
-"SDRAM_ARB_CFG","override_value","21-18","tsp_region_data","0x8",,
-"SDRAM_ARB_CFG","override_value","21-18","isp_pointer_data","0x9",,
-"SDRAM_ARB_CFG","override_value","21-18","isp_parameters","0xa",,
-"SDRAM_ARB_CFG","override_value","21-18","crt_controller","0xb",,
-"SDRAM_ARB_CFG","arbiter_priority_control","17-16","priority_arbitration_only","0x0",,
-"SDRAM_ARB_CFG","arbiter_priority_control","17-16","override_value_field","0x1",,
-"SDRAM_ARB_CFG","arbiter_priority_control","17-16","round_robin_counter","0x2",,
-"SDRAM_ARB_CFG",,"15-8","arbiter_crt_page_break_latency_count_value",,"0xff",
-"SDRAM_ARB_CFG",,"7-0","arbiter_page_break_latency_count_value",,"0xff",
-,,,,,,
-"SDRAM_CFG",,"28-26","read_command_to_returned_data_delay",,"0b111",
-"SDRAM_CFG",,"25-23","cas_latency_value",,"0b111",
-"SDRAM_CFG",,"22-21","activate_to_activate_period",,"0b11",
-"SDRAM_CFG",,"20-18","read_to_write_period",,"0b111",
-"SDRAM_CFG",,"17-14","refresh_to_activate_period",,"0b1111",
-"SDRAM_CFG",,"11-10","pre_charge_to_activate_period",,"0b11",
-"SDRAM_CFG",,"9-6","activate_to_pre_charge_period",,"0b1111",
-"SDRAM_CFG",,"5-4","activate_to_read_write_command_period",,"0b11",
-"SDRAM_CFG",,"3-2","write_to_pre_charge_period",,"0b11",
-"SDRAM_CFG",,"1-0","read_to_pre_charge_period",,"0b11",
-,,,,,,
-"FOG_COL_RAM",,"23-16","red",,"0xff",
-"FOG_COL_RAM",,"15-8","green",,"0xff",
-"FOG_COL_RAM",,"7-0","blue",,"0xff",
-,,,,,,
-"FOG_COL_VERT",,"23-16","red",,"0xff",
-"FOG_COL_VERT",,"15-8","green",,"0xff",
-"FOG_COL_VERT",,"7-0","blue",,"0xff",
-,,,,,,
-"FOG_DENSITY",,"15-8","fog_scale_mantissa",,"0xff",
-"FOG_DENSITY",,"7-0","fog_scale_exponent",,"0xff",
-,,,,,,
-"FOG_CLAMP_MAX",,"31-24","alpha",,"0xff",
-"FOG_CLAMP_MAX",,"23-16","red",,"0xff",
-"FOG_CLAMP_MAX",,"15-8","green",,"0xff",
-"FOG_CLAMP_MAX",,"7-0","blue",,"0xff",
-,,,,,,
-"FOG_CLAMP_MIN",,"31-24","alpha",,"0xff",
-"FOG_CLAMP_MIN",,"23-16","red",,"0xff",
-"FOG_CLAMP_MIN",,"15-8","green",,"0xff",
-"FOG_CLAMP_MIN",,"7-0","blue",,"0xff",
-,,,,,,
-"SPG_TRIGGER_POS",,"25-16","trigger_v_count",,,
-"SPG_TRIGGER_POS",,"9-0","trigger_h_count",,,
-,,,,,,
-"SPG_HBLANK_INT",,"25-16","hblank_in_interrupt",,,
-"SPG_HBLANK_INT","hblank_int_mode","13-12","output_equal_line_comp_val","0x0",,
-"SPG_HBLANK_INT","hblank_int_mode","13-12","output_every_line_comp_val","0x1",,
-"SPG_HBLANK_INT","hblank_int_mode","13-12","output_every_line","0x2",,
-"SPG_HBLANK_INT",,"9-0","line_comp_val",,"0x3ff",
-,,,,,,
-"SPG_VBLANK_INT",,"25-16","vblank_out_interrupt_line_number",,"0x3ff",
-"SPG_VBLANK_INT",,"9-0","vblank_in_interrupt_line_number",,"0x3ff",
-,,,,,,
-"SPG_CONTROL","csync_on_h",9,"hsync",0,,
-"SPG_CONTROL","cysnc_on_h",9,"csync",1,,
-"SPG_CONTROL","sync_direction",8,"input",0,,
-"SPG_CONTROL","sync_direction",8,"output",1,,
-"SPG_CONTROL",,7,"pal",1,,
-"SPG_CONTROL",,6,"ntsc",1,,
-"SPG_CONTROL",,5,"force_field2",1,,
-"SPG_CONTROL",,4,"interlace",1,,
-"SPG_CONTROL",,3,"spg_lock",1,,
-"SPG_CONTROL","mcsync_pol",2,"active_low",0,,
-"SPG_CONTROL","mcsync_pol",2,"active_high",1,,
-"SPG_CONTROL","mvsync_pol",1,"active_low",0,,
-"SPG_CONTROL","mvsync_pol",1,"active_high",1,,
-"SPG_CONTROL","mhsync_pol",0,"active_low",0,,
-"SPG_CONTROL","mhsync_pol",0,"active_high",1,,
-,,,,,,
-"SPG_HBLANK",,"25-16","hbend",,"0x3ff",
-"SPG_HBLANK",,"9-0","hbstart",,"0x3ff",
-,,,,,,
-"SPG_LOAD",,"25-16","vcount",,"0x3ff",
-"SPG_LOAD",,"9-0","hcount",,"0x3ff",
-,,,,,,
-"SPG_VBLANK",,"25-16","vbend",,"0x3ff",
-"SPG_VBLANK",,"9-0","vbstart",,"0x3ff",
-,,,,,,
-"SPG_WIDTH",,"31-22","eqwidth",,"0x3ff",
-"SPG_WIDTH",,"21-12","bpwidth",,"0x3ff",
-"SPG_WIDTH",,"11-8","vswidth",,"0b1111",
-"SPG_WIDTH",,"6-0","hswidth",,"0x7f",
-,,,,,,
-"TEXT_CONTROL","code_book_endian",17,"little_endian",0,,
-"TEXT_CONTROL","code_book_endian",17,"big_endian",1,,
-"TEXT_CONTROL","index_endian",16,"little_endian",0,,
-"TEXT_CONTROL","index_endian",16,"big_endian",1,,
-"TEXT_CONTROL",,"12-8","bank_bit",,"0x1f",
-"TEXT_CONTROL",,"4-0","stride",,"0x1f",
-,,,,,,
-"VO_CONTROL",,21,"pclk_delay_reset",1,,
-"VO_CONTROL",,"20-16","pclk_delay",,"0b1111",
-"VO_CONTROL",,8,"pixel_double",1,,
-"VO_CONTROL","field_mode","7-4","use_field_flag_from_spg","0x0",,
-"VO_CONTROL","field_mode","7-4","use_inverse_of_field_flag_from_spg","0x1",,
-"VO_CONTROL","field_mode","7-4","field_1_fixed","0x2",,
-"VO_CONTROL","field_mode","7-4","field_2_fixed","0x3",,
-"VO_CONTROL","field_mode","7-4","field_1_when_the_active_edges_of_hsync_and_vsync_match","0x4",,
-"VO_CONTROL","field_mode","7-4","field_2_when_the_active_edges_of_hsync_and_vsync_match","0x5",,
-"VO_CONTROL","field_mode","7-4","field_1_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge","0x6",,
-"VO_CONTROL","field_mode","7-4","field_2_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge","0x7",,
-"VO_CONTROL","field_mode","7-4","inverted_at_the_active_edge_of_vsync","0x8",,
-"VO_CONTROL","blank_video",3,"display_the_screen",0,,
-"VO_CONTROL","blank_video",3,"do_not_display_the_screen",1,,
-"VO_CONTROL","blank_pol",2,"active_low",0,,
-"VO_CONTROL","blank_pol",2,"active_high",1,,
-"VO_CONTROL","vsync_pol",1,"active_low",0,,
-"VO_CONTROL","vsync_pol",1,"active_high",1,,
-"VO_CONTROL","hsync_pol",0,"active_low",0,,
-"VO_CONTROL","hsync_pol",0,"active_high",1,,
-,,,,,,
-"VO_STARTX",,"9-0","horizontal_start_position",,"0x3ff",
-,,,,,,
-"VO_STARTY",,"25-16","vertical_start_position_on_field_2",,"0x3ff",
-"VO_STARTY",,"9-0","vertical_start_position_on_field_1",,"0x3ff",
-,,,,,,
-"SCALER_CTL","field_select",18,"field_1",0,,
-"SCALER_CTL","field_select",18,"field_2",1,,
-"SCALER_CTL",,17,"interlace",1,,
-"SCALER_CTL",,16,"horizontal_scaling_enable",1,,
-"SCALER_CTL",,"15-0","vertical_scale_factor",,"0xffff",
-,,,,,,
-"PAL_RAM_CTL","pixel_format","1-0","argb1555",0,,
-"PAL_RAM_CTL","pixel_format","1-0","rgb565",1,,
-"PAL_RAM_CTL","pixel_format","1-0","argb4444",2,,
-"PAL_RAM_CTL","pixel_format","1-0","argb8888",3,,
-,,,,,,
-"SPG_STATUS",,13,"vsync",,,
-"SPG_STATUS",,12,"hsync",,,
-"SPG_STATUS",,11,"blank",,,
-"SPG_STATUS",,10,"fieldnum",,,
-"SPG_STATUS",,"9-0","scanline",,,
-,,,,,,
-"FB_BURSTCTRL",,"19-16","wr_burst",,"0b1111",
-"FB_BURSTCTRL",,"14-8","vid_lat",,"0x7f",
-"FB_BURSTCTRL",,"5-0","vid_burst",,"0x3f",
-,,,,,,
-"FB_C_SOF",,"23-2","frame_buffer_current_read_address",,,
-,,,,,,
-"Y_COEFF",,"15-8","coefficient_1",,"0xff",
-"Y_COEFF",,"7-0","coefficient_0_2",,"0xff",
-,,,,,,
-"PT_ALPHA_REF",,"7-0","alpha_reference_for_punch_through",,"0xff",
-,,,,,,
-"FOG_TABLE",,"15-0","fog_table_data",,"0xffff",
-,,,,,,
-"PALETTE_RAM",,"31-0","palette_data",,"0xffff_ffff",
+"register_name","enum_name","bits","bit_name","value","mask","description",,,,,
+"ID",,"31-16","device_id",,,,,,,,
+"ID",,"15-0","vendor_id",,,,,,,,
+,,,,,,,,,,,
+"REVISION",,"15-0","chip_revision",,,,,,,,
+,,,,,,,,,,,
+"SOFTRESET",,2,"sdram_if_soft_reset",1,,,,,,,
+"SOFTRESET",,1,"pipeline_soft_reset",1,,,,,,,
+"SOFTRESET",,0,"ta_soft_reset",1,,,,,,,
+,,,,,,,,,,,
+"STARTRENDER",,0,"start_render",1,,,,,,,
+,,,,,,,,,,,
+"TEST_SELECT",,"9-5","diagdb_data",,,,,,,,
+"TEST_SELECT",,"4-0","diagda_data",,,,,,,,
+,,,,,,,,,,,
+"PARAM_BASE",,"23-0","base_address",,"0xf00000",,,,,,
+,,,,,,,,,,,
+"REGION_BASE",,"23-0","base_address",,"0xfffffc",,,,,,
+,,,,,,,,,,,
+"SPAN_SORT_CFG",,16,"cache_bypass",1,,,,,,,
+"SPAN_SORT_CFG",,8,"offset_sort_enable",1,,,,,,,
+"SPAN_SORT_CFG",,0,"span_sort_enable",1,,,,,,,
+,,,,,,,,,,,
+"VO_BORDER_COL",,24,"chroma",,"0b1",,,,,,
+"VO_BORDER_COL",,"23-16","red",,"0xff",,,,,,
+"VO_BORDER_COL",,"15-8","green",,"0xff",,,,,,
+"VO_BORDER_COL",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"FB_R_CTRL","vclk_div",23,"pclk_vclk_2",0,,,,,,,
+"FB_R_CTRL","vclk_div",23,"pclk_vclk_1",1,,,,,,,
+"FB_R_CTRL",,22,"fb_strip_buf_en",1,,,,,,,
+"FB_R_CTRL",,"21-16","fb_stripsize",,"0b111_110","In units of 16 lines, in multiples of 32 lines. 0x02 is 32 lines, 0x04 is 64 lines, 0x03 is an illegal value",,,,,
+"FB_R_CTRL",,"15-8","fb_chroma_threshold",,"0xff",,,,,,
+"FB_R_CTRL",,"6-4","fb_concat",,"0b11",,,,,,
+"FB_R_CTRL","fb_depth","3-2","_0555_rgb_16bit",0,,,,,,,
+"FB_R_CTRL","fb_depth","3-2","_0565_rgb_16bit",1,,,,,,,
+"FB_R_CTRL","fb_depth","3-2","_888_rgb_24bit_packed",2,,,,,,,
+"FB_R_CTRL","fb_depth","3-2","_0888_rgb_32bit",3,,,,,,,
+"FB_R_CTRL",,1,"fb_line_double",1,,,,,,,
+"FB_R_CTRL",,0,"fb_enable",1,,,,,,,
+,,,,,,,,,,,
+"FB_W_CTRL",,"23-16","fb_alpha_threshold",,"0xff",,,,,,
+"FB_W_CTRL",,"15-8","fb_kval",,"0xff",,,,,,
+"FB_W_CTRL",,3,"fb_dither",1,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","_0555_krgb_16bit",0,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","_565_rgb_16bit",1,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","_4444_argb_16bit",2,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","_1555_argb_16bit",3,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","_888_rgb_24bit_packed",4,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","_0888_krgb_32bit",5,,,,,,,
+"FB_W_CTRL","fb_packmode","2-0","_8888_argb_32bit",6,,,,,,,
+,,,,,,,,,,,
+"FB_W_LINESTRIDE",,"8-0","fb_line_stride",,"0xff","In 8-byte units",,,,,
+,,,,,,,,,,,
+"FB_R_SOF1",,"23-0","frame_buffer_read_address_frame_1",,"0xfffffc",,,,,,
+,,,,,,,,,,,
+"FB_R_SOF2",,"23-0","frame_buffer_read_address_frame_2",,"0xfffffc",,,,,,
+,,,,,,,,,,,
+"FB_R_SIZE",,"29-20","fb_modulus",,"0x3ff","In 4-byte units",,,,,
+"FB_R_SIZE",,"19-10","fb_y_size",,"0x3ff",,,,,,
+"FB_R_SIZE",,"9-0","fb_x_size",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"FB_W_SOF1",,"24-0","frame_buffer_write_address_frame_1",,"0x1fffffc",,,,,,
+,,,,,,,,,,,
+"FB_W_SOF2",,"24-0","frame_buffer_write_address_frame_2",,"0x1fffffc",,,,,,
+,,,,,,,,,,,
+"FB_X_CLIP",,"26-16","fb_x_clip_max",,"0x7ff",,,,,,
+"FB_X_CLIP",,"10-0","fb_x_clip_min",,"0x7ff",,,,,,
+,,,,,,,,,,,
+"FB_Y_CLIP",,"25-16","fb_y_clip_max",,"0x3ff",,,,,,
+"FB_Y_CLIP",,"9-0","fb_y_clip_min",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"FPU_SHAD_SCALE","simple_shadow_enable",8,"parameter_selection_volume_mode",0,,,,,,,
+"FPU_SHAD_SCALE","simple_shadow_enable",8,"intensity_volume_mode",1,,,,,,,
+"FPU_SHAD_SCALE",,"7-0","scale_factor_for_shadows",,"0xff",,,,,,
+,,,,,,,,,,,
+"FPU_CULL_VAL",,"30-0","culling_comparison_value",,"float_0_8_23",,,,,,
+,,,,,,,,,,,
+"FPU_PARAM_CFG","region_header_type",21,"type_1",0,,,,,,,
+"FPU_PARAM_CFG","region_header_type",21,"type_2",1,,,,,,,
+"FPU_PARAM_CFG",,"19-14","tsp_parameter_burst_threshold",,"0x3f",,,,,,
+"FPU_PARAM_CFG",,"13-8","isp_parameter_burst_threshold",,"0x3f",,,,,,
+"FPU_PARAM_CFG",,"7-4","pointer_burst_size",,"0xf",,,,,,
+"FPU_PARAM_CFG",,"3-0","pointer_first_burst_size",,"0xf",,,,,,
+,,,,,,,,,,,
+"HALF_OFFSET","tsp_texel_sampling_position",2,"top_left",,,,,,,,
+"HALF_OFFSET","tsp_texel_sampling_position",2,"center",,,,,,,,
+"HALF_OFFSET","tsp_pixel_sampling_position",1,"top_left",,,,,,,,
+"HALF_OFFSET","tsp_pixel_sampling_position",1,"center",,,,,,,,
+"HALF_OFFSET","fpu_pixel_sampling_position",0,"top_left",,,,,,,,
+"HALF_OFFSET","fpu_pixel_sampling_position",0,"center",,,,,,,,
+,,,,,,,,,,,
+"FPU_PERP_VAL",,"30-0","perpendicular_triangle_compare",,"float_0_8_23",,,,,,
+,,,,,,,,,,,
+"ISP_BACKGND_D",,"31-4","background_plane_depth",,"float_1_8_19",,,,,,
+,,,,,,,,,,,
+"ISP_BACKGND_T",,28,"cache_bypass",1,,,,,,,
+"ISP_BACKGND_T",,27,"shadow",1,,,,,,,
+"ISP_BACKGND_T",,"26-24","skip",,"0b111",,,,,,
+"ISP_BACKGND_T",,"23-3","tag_address",,"0x1fffff","In 32-bit units",,,,,
+"ISP_BACKGND_T",,"2-0","tag_offset",,"0b111",,,,,,
+,,,,,,,,,,,
+"ISP_FEED_CFG",,"23-14","cache_size_for_translucency",,"0x3ff","Must be between 0x020 and 0x200",,,,,
+"ISP_FEED_CFG",,"13-4","punch_through_chunk_size",,"0x3ff","Must be between 0x020 and 0x200, must be larger than cache_size_for_translucency",,,,,
+"ISP_FEED_CFG",,3,"discard_mode",1,,,,,,,
+"ISP_FEED_CFG",,0,"pre_sort_mode",1,,,,,,,
+,,,,,,,,,,,
+"SDRAM_REFRESH",,"7-0","refresh_counter_value",,"0xff",,,,,,
+,,,,,,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","priority_only","0x0",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","rendered_data","0x1",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","texture_vq_index","0x2",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","texture_normal_data_and_vq_codebook","0x3",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","tile_accelerator_isp_tsp_data","0x4",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","tile_accelerator_pointers","0x5",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","sh4","0x6",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","tsp_parameters","0x7",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","tsp_region_data","0x8",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","isp_pointer_data","0x9",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","isp_parameters","0xa",,,,,,,
+"SDRAM_ARB_CFG","override_value","21-18","crt_controller","0xb",,,,,,,
+"SDRAM_ARB_CFG","arbiter_priority_control","17-16","priority_arbitration_only","0x0",,,,,,,
+"SDRAM_ARB_CFG","arbiter_priority_control","17-16","override_value_field","0x1",,,,,,,
+"SDRAM_ARB_CFG","arbiter_priority_control","17-16","round_robin_counter","0x2",,,,,,,
+"SDRAM_ARB_CFG",,"15-8","arbiter_crt_page_break_latency_count_value",,"0xff",,,,,,
+"SDRAM_ARB_CFG",,"7-0","arbiter_page_break_latency_count_value",,"0xff",,,,,,
+,,,,,,,,,,,
+"SDRAM_CFG",,"28-26","read_command_to_returned_data_delay",,"0b111",,,,,,
+"SDRAM_CFG",,"25-23","cas_latency_value",,"0b111",,,,,,
+"SDRAM_CFG",,"22-21","activate_to_activate_period",,"0b11",,,,,,
+"SDRAM_CFG",,"20-18","read_to_write_period",,"0b111",,,,,,
+"SDRAM_CFG",,"17-14","refresh_to_activate_period",,"0b1111",,,,,,
+"SDRAM_CFG",,"11-10","pre_charge_to_activate_period",,"0b11",,,,,,
+"SDRAM_CFG",,"9-6","activate_to_pre_charge_period",,"0b1111",,,,,,
+"SDRAM_CFG",,"5-4","activate_to_read_write_command_period",,"0b11",,,,,,
+"SDRAM_CFG",,"3-2","write_to_pre_charge_period",,"0b11",,,,,,
+"SDRAM_CFG",,"1-0","read_to_pre_charge_period",,"0b11",,,,,,
+,,,,,,,,,,,
+"FOG_COL_RAM",,"23-16","red",,"0xff",,,,,,
+"FOG_COL_RAM",,"15-8","green",,"0xff",,,,,,
+"FOG_COL_RAM",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_COL_VERT",,"23-16","red",,"0xff",,,,,,
+"FOG_COL_VERT",,"15-8","green",,"0xff",,,,,,
+"FOG_COL_VERT",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_DENSITY",,"15-8","fog_scale_mantissa",,"0xff",,,,,,
+"FOG_DENSITY",,"7-0","fog_scale_exponent",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_CLAMP_MAX",,"31-24","alpha",,"0xff",,,,,,
+"FOG_CLAMP_MAX",,"23-16","red",,"0xff",,,,,,
+"FOG_CLAMP_MAX",,"15-8","green",,"0xff",,,,,,
+"FOG_CLAMP_MAX",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_CLAMP_MIN",,"31-24","alpha",,"0xff",,,,,,
+"FOG_CLAMP_MIN",,"23-16","red",,"0xff",,,,,,
+"FOG_CLAMP_MIN",,"15-8","green",,"0xff",,,,,,
+"FOG_CLAMP_MIN",,"7-0","blue",,"0xff",,,,,,
+,,,,,,,,,,,
+"SPG_TRIGGER_POS",,"25-16","trigger_v_count",,,,,,,,
+"SPG_TRIGGER_POS",,"9-0","trigger_h_count",,,,,,,,
+,,,,,,,,,,,
+"SPG_HBLANK_INT",,"25-16","hblank_in_interrupt",,,,,,,,
+"SPG_HBLANK_INT","hblank_int_mode","13-12","output_equal_line_comp_val","0x0",,,,,,,
+"SPG_HBLANK_INT","hblank_int_mode","13-12","output_every_line_comp_val","0x1",,,,,,,
+"SPG_HBLANK_INT","hblank_int_mode","13-12","output_every_line","0x2",,,,,,,
+"SPG_HBLANK_INT",,"9-0","line_comp_val",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_VBLANK_INT",,"25-16","vblank_out_interrupt_line_number",,"0x3ff",,,,,,
+"SPG_VBLANK_INT",,"9-0","vblank_in_interrupt_line_number",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_CONTROL","csync_on_h",9,"hsync",0,,,,,,,
+"SPG_CONTROL","csync_on_h",9,"csync",1,,,,,,,
+"SPG_CONTROL","sync_direction",8,"input",0,,,,,,,
+"SPG_CONTROL","sync_direction",8,"output",1,,,,,,,
+"SPG_CONTROL",,7,"pal",1,,,,,,,
+"SPG_CONTROL",,6,"ntsc",1,,,,,,,
+"SPG_CONTROL",,5,"force_field2",1,,,,,,,
+"SPG_CONTROL",,4,"interlace",1,,,,,,,
+"SPG_CONTROL",,3,"spg_lock",1,,,,,,,
+"SPG_CONTROL","mcsync_pol",2,"active_low",0,,,,,,,
+"SPG_CONTROL","mcsync_pol",2,"active_high",1,,,,,,,
+"SPG_CONTROL","mvsync_pol",1,"active_low",0,,,,,,,
+"SPG_CONTROL","mvsync_pol",1,"active_high",1,,,,,,,
+"SPG_CONTROL","mhsync_pol",0,"active_low",0,,,,,,,
+"SPG_CONTROL","mhsync_pol",0,"active_high",1,,,,,,,
+,,,,,,,,,,,
+"SPG_HBLANK",,"25-16","hbend",,"0x3ff",,,,,,
+"SPG_HBLANK",,"9-0","hbstart",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_LOAD",,"25-16","vcount",,"0x3ff",,,,,,
+"SPG_LOAD",,"9-0","hcount",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_VBLANK",,"25-16","vbend",,"0x3ff",,,,,,
+"SPG_VBLANK",,"9-0","vbstart",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SPG_WIDTH",,"31-22","eqwidth",,"0x3ff",,,,,,
+"SPG_WIDTH",,"21-12","bpwidth",,"0x3ff",,,,,,
+"SPG_WIDTH",,"11-8","vswidth",,"0b1111",,,,,,
+"SPG_WIDTH",,"6-0","hswidth",,"0x7f",,,,,,
+,,,,,,,,,,,
+"TEXT_CONTROL","code_book_endian",17,"little_endian",0,,,,,,,
+"TEXT_CONTROL","code_book_endian",17,"big_endian",1,,,,,,,
+"TEXT_CONTROL","index_endian",16,"little_endian",0,,,,,,,
+"TEXT_CONTROL","index_endian",16,"big_endian",1,,,,,,,
+"TEXT_CONTROL",,"12-8","bank_bit",,"0x1f",,,,,,
+"TEXT_CONTROL",,"4-0","stride",,"0x1f",,,,,,
+,,,,,,,,,,,
+"VO_CONTROL",,21,"pclk_delay_reset",1,,,,,,,
+"VO_CONTROL",,"20-16","pclk_delay",,"0b1111",,,,,,
+"VO_CONTROL",,8,"pixel_double",1,,,,,,,
+"VO_CONTROL","field_mode","7-4","use_field_flag_from_spg","0x0",,,,,,,
+"VO_CONTROL","field_mode","7-4","use_inverse_of_field_flag_from_spg","0x1",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_1_fixed","0x2",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_2_fixed","0x3",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_1_when_the_active_edges_of_hsync_and_vsync_match","0x4",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_2_when_the_active_edges_of_hsync_and_vsync_match","0x5",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_1_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge","0x6",,,,,,,
+"VO_CONTROL","field_mode","7-4","field_2_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge","0x7",,,,,,,
+"VO_CONTROL","field_mode","7-4","inverted_at_the_active_edge_of_vsync","0x8",,,,,,,
+"VO_CONTROL",,3,"blank_video",1,,,,,,,
+"VO_CONTROL","blank_pol",2,"active_low",0,,,,,,,
+"VO_CONTROL","blank_pol",2,"active_high",1,,,,,,,
+"VO_CONTROL","vsync_pol",1,"active_low",0,,,,,,,
+"VO_CONTROL","vsync_pol",1,"active_high",1,,,,,,,
+"VO_CONTROL","hsync_pol",0,"active_low",0,,,,,,,
+"VO_CONTROL","hsync_pol",0,"active_high",1,,,,,,,
+,,,,,,,,,,,
+"VO_STARTX",,"9-0","horizontal_start_position",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"VO_STARTY",,"25-16","vertical_start_position_on_field_2",,"0x3ff",,,,,,
+"VO_STARTY",,"9-0","vertical_start_position_on_field_1",,"0x3ff",,,,,,
+,,,,,,,,,,,
+"SCALER_CTL","field_select",18,"field_1",0,,,,,,,
+"SCALER_CTL","field_select",18,"field_2",1,,,,,,,
+"SCALER_CTL",,17,"interlace",1,,,,,,,
+"SCALER_CTL",,16,"horizontal_scaling_enable",1,,,,,,,
+"SCALER_CTL",,"15-0","vertical_scale_factor",,"0xffff",,,,,,
+,,,,,,,,,,,
+"PAL_RAM_CTL","pixel_format","1-0","argb1555",0,,,,,,,
+"PAL_RAM_CTL","pixel_format","1-0","rgb565",1,,,,,,,
+"PAL_RAM_CTL","pixel_format","1-0","argb4444",2,,,,,,,
+"PAL_RAM_CTL","pixel_format","1-0","argb8888",3,,,,,,,
+,,,,,,,,,,,
+"SPG_STATUS",,13,"vsync",,,,,,,,
+"SPG_STATUS",,12,"hsync",,,,,,,,
+"SPG_STATUS",,11,"blank",,,,,,,,
+"SPG_STATUS",,10,"fieldnum",,,,,,,,
+"SPG_STATUS",,"9-0","scanline",,,,,,,,
+,,,,,,,,,,,
+"FB_BURSTCTRL",,"19-16","wr_burst",,"0b1111",,,,,,
+"FB_BURSTCTRL",,"14-8","vid_lat",,"0x7f",,,,,,
+"FB_BURSTCTRL",,"5-0","vid_burst",,"0x3f",,,,,," >"
+,,,,,,,,,,,
+"FB_C_SOF",,"23-0","frame_buffer_current_read_address",,,,,,,,
+,,,,,,,,,,,
+"Y_COEFF",,"15-8","coefficient_1",,"0xff",,,,,,
+"Y_COEFF",,"7-0","coefficient_0_2",,"0xff",,,,,,
+,,,,,,,,,,,
+"PT_ALPHA_REF",,"7-0","alpha_reference_for_punch_through",,"0xff",,,,,,
+,,,,,,,,,,,
+"FOG_TABLE",,"15-0","fog_table_data",,"0xffff",,,,,,
+,,,,,,,,,,,
+"PALETTE_RAM",,"31-0","palette_data",,"0xffff_ffff",,,,,,
diff --git a/regs/core_bits.ods b/regs/core_bits.ods
index e377ef5..21a62de 100644
Binary files a/regs/core_bits.ods and b/regs/core_bits.ods differ
diff --git a/regs/gen/core_bits.py b/regs/gen/core_bits.py
new file mode 100644
index 0000000..9706524
--- /dev/null
+++ b/regs/gen/core_bits.py
@@ -0,0 +1,219 @@
+import sys
+from collections import defaultdict
+from pprint import pprint
+from dataclasses import dataclass
+from typing import Union
+
+from sh7091 import read_input
+from generate import renderer
+
+def aggregate_registers(d):
+    aggregated = defaultdict(list)
+    for row in d:
+        assert row["register_name"] != ""
+        aggregated[row["register_name"]].append(row)
+    return dict(aggregated)
+
+def parse_bit_number(s):
+    assert '-' not in s
+    return int(s, 10)
+
+def parse_bit_range(s):
+    if '-' in s:
+        left, right = map(parse_bit_number, s.split('-', maxsplit=1))
+        assert left > right, (left, right)
+        return set(range(right, left+1))
+    else:
+        num = parse_bit_number(s)
+        return set([num])
+
+def aggregate_enums(aggregated_rows):
+    non_enum = []
+    enum_aggregated = defaultdict(list)
+    all_bits = set()
+    enum_bits = dict()
+
+    def assert_unique_ordered(bits):
+        nonlocal all_bits
+        assert all(bit not in all_bits for bit in bits), bits
+        assert max(all_bits, default=32) > max(bits)
+        all_bits |= bits
+
+    for row in aggregated_rows:
+        bits = parse_bit_range(row["bits"])
+        assert row["bit_name"] != ""
+        if row["enum_name"] == "":
+            assert_unique_ordered(bits)
+            non_enum.append(row)
+        else:
+            if row["enum_name"] not in enum_bits:
+                assert_unique_ordered(bits)
+                non_enum.append(row["enum_name"])
+            else:
+                assert enum_bits[row["enum_name"]] == bits
+
+            enum_bits[row["enum_name"]] = bits
+            enum_aggregated[row["enum_name"]].append(row)
+
+    return non_enum, dict(enum_aggregated)
+
+@dataclass
+class enum:
+    name: str
+    defs: list[dict]
+
+@dataclass
+class register:
+    name: str
+    defs: list[Union[dict, enum]]
+
+def aggregate_all_enums(aggregated):
+    out = []
+    for register_name, rows in aggregated.items():
+        non_enum, enum_aggregated = aggregate_enums(rows)
+        def resolve(row_or_string):
+            if type(row_or_string) == str:
+                return enum(row_or_string,
+                            enum_aggregated[row_or_string])
+            elif type(row_or_string) == dict:
+                return row_or_string
+            else:
+                assert False, (row_or_string, type(row_or_string))
+        out.append(
+            register(register_name,
+                     [resolve(aggregate) for aggregate in non_enum]))
+    return out
+
+'''
+ register(name='SCALER_CTL',
+          defs=[enum(name='field_select',
+                     defs=[{'bit_name': 'field_1',
+                            'bits': '18',
+                            'description': '',
+                            'enum_name': 'field_select',
+                            'mask': '',
+                            'register_name': 'SCALER_CTL',
+                            'value': '0'},
+                           {...}]),
+                {'bit_name': 'interlace',
+                 'bits': '17',
+                 'description': '',
+                 'enum_name': '',
+                 'mask': '',
+                 'register_name': 'SCALER_CTL',
+                 'value': '1'},
+                {...},
+                ...]),
+'''
+
+def mask_from_bits(bits):
+    mask = 2 ** len(bits) - 1
+    return mask
+
+def parse_value(value):
+    return eval(value)
+
+def render_read_only(bit_def):
+    assert bit_def["value"] == ""
+    assert bit_def["mask"] == ""
+    bits = parse_bit_range(bit_def["bits"])
+    mask_value = mask_from_bits(bits)
+    yield (
+        f"constexpr uint32_t {bit_def['bit_name']}(uint32_t reg) {{ "
+        f"return (reg >> {min(bits)}) & {hex(mask_value)};"
+        " }"
+    )
+
+def render_float_mask(mask):
+    if mask == "float_0_8_23":
+        return "_i(__builtin_fabsf(num));"
+    elif mask == "float_1_8_23":
+        return "_i(num)"
+    else:
+        assert mask.startswith("float_")
+        mask = mask.removeprefix("float_")
+        sign, exponent, fraction = map(int, mask.split('_'))
+        assert exponent == 8, exponent
+        assert sign == 1
+        bit_length = (sign + exponent + fraction)
+        mask = (2 ** bit_length - 1) << (32 - bit_length)
+        return f"_i(num) & {hex(mask)}"
+
+def render_mask(bit_def):
+    assert bit_def["value"] == ""
+    mask = bit_def["mask"]
+    bits = parse_bit_range(bit_def["bits"])
+    if mask.startswith("float_"):
+        yield (
+            f"constexpr uint32_t {bit_def['bit_name']}(float num) {{ "
+            f"return {render_float_mask(mask)};"
+            " }"
+        )
+    else:
+        assert mask.startswith("0x") or mask.startswith("0b") or mask[0] in set(range(0, 9+1)), mask
+        mask_value = eval(mask)
+        assert mask_value & mask_from_bits(bits) == mask_value, (mask_value, mask_from_bits(bits))
+
+        yield (
+            f"constexpr uint32_t {bit_def['bit_name']}(uint32_t num) {{ "
+            f"return (num & {hex(mask_value)}) << {min(bits)};"
+            " }"
+        )
+
+def render_value(bit_def):
+    assert bit_def["mask"] == ""
+    bits = parse_bit_range(bit_def["bits"])
+    assert parse_value(bit_def["value"]) <= mask_from_bits(bits), bit_def["value"]
+    bit_ix = min(bits)
+    yield f"constexpr uint32_t {bit_def['bit_name']} = {bit_def['value']} << {bit_ix};"
+
+def render_defs(bit_def):
+    if bit_def["value"] != "":
+        yield from render_value(bit_def)
+    elif bit_def["mask"] != "":
+        yield from render_mask(bit_def)
+    else:
+        yield from render_read_only(bit_def)
+
+def render_enum(enum_def):
+    yield f"namespace {enum_def.name.lower()} {{"
+    for bit_def in enum_def.defs:
+        yield from render_defs(bit_def)
+    yield "}"
+
+def render_register(register):
+    yield f"namespace {register.name.lower()} {{"
+
+    last = None
+    for ix, bit_def in enumerate(register.defs):
+        if type(bit_def) is enum:
+            if ix != 0:
+                yield ""
+            yield from render_enum(bit_def)
+        else:
+            if ix != 0 and type(last) is enum:
+                yield ""
+            yield from render_defs(bit_def)
+        last = bit_def
+
+    yield "}"
+    yield ""
+
+def render_registers(registers):
+    for register in registers:
+        yield from render_register(register)
+
+def header():
+    yield "#include <cstdint>"
+    yield ""
+    yield '#include "float_uint32.h"'
+    yield ""
+
+if __name__ == "__main__":
+    d = read_input(sys.argv[1])
+    aggregated = aggregate_registers(d)
+    registers = aggregate_all_enums(aggregated)
+    render, out = renderer()
+    render(header())
+    render(render_registers(registers))
+    sys.stdout.write(out.getvalue())
diff --git a/regs/gen/sh7091.py b/regs/gen/sh7091.py
index d6b0722..d24390b 100644
--- a/regs/gen/sh7091.py
+++ b/regs/gen/sh7091.py
@@ -5,7 +5,8 @@ from pprint import pprint
 
 from generate import renderer
 
-def as_dict(header, row):
+def as_dict(header, row0):
+    row = [s.strip() for s in row0]
     return dict(zip(header, row))
 
 def read_input(filename):
diff --git a/regs/memorymap.ods b/regs/memorymap.ods
index 373544a..dd874ac 100644
Binary files a/regs/memorymap.ods and b/regs/memorymap.ods differ
diff --git a/regs/ta_bits.csv b/regs/ta_bits.csv
new file mode 100644
index 0000000..6b9bf4d
--- /dev/null
+++ b/regs/ta_bits.csv
@@ -0,0 +1,63 @@
+"register_name","enum_name","bits","bit_name","value","mask","description"
+"TA_OL_BASE",,"23-0","base_address",,"0xffffe0","in 32-byte units"
+,,,,,,
+"TA_ISP_BASE",,"23-0","base_address",,"0xfffffc","in 4-byte units"
+,,,,,,
+"TA_OL_LIMIT",,"23-0","limit_address",,"0xffffe0","in 32-byte units"
+,,,,,,
+"TA_ISP_LIMIT",,"23-0","limit_address",,"0xfffffc","in 4-byte units"
+,,,,,,
+"TA_NEXT_OPB",,"23-0","address",,"0xffffe0","in 32-byte units"
+,,,,,,
+"TA_ITP_CURRENT",,"23-0","address",,,
+,,,,,,
+"TA_GLOB_TILE_CLIP",,"19-16","tile_y_num",,"0xf",
+"TA_GLOB_TILE_CLIP",,"5-0","tile_x_num",,"0x1f",
+,,,,,,
+"TA_ALLOC_CTRL","opb_mode",20,"decreasing_addresses",0,,
+"TA_ALLOC_CTRL","opb_mode",20,"increasing_addresses",1,,
+"TA_ALLOC_CTRL","pt_opb","17-16","no_list",0,,
+"TA_ALLOC_CTRL","pt_opb","17-16","_8x4byte",1,,
+"TA_ALLOC_CTRL","pt_opb","17-16","_16x4byte",2,,
+"TA_ALLOC_CTRL","pt_opb","17-16","_32x4byte",3,,
+"TA_ALLOC_CTRL","tm_opb","13-12","no_list",0,,
+"TA_ALLOC_CTRL","tm_opb","13-12","_8x4byte",1,,
+"TA_ALLOC_CTRL","tm_opb","13-12","_16x4byte",2,,
+"TA_ALLOC_CTRL","tm_opb","13-12","_32x4byte",3,,
+"TA_ALLOC_CTRL","t_opb","9-8","no_list",0,,
+"TA_ALLOC_CTRL","t_opb","9-8","_8x4byte",1,,
+"TA_ALLOC_CTRL","t_opb","9-8","_16x4byte",2,,
+"TA_ALLOC_CTRL","t_opb","9-8","_32x4byte",3,,
+"TA_ALLOC_CTRL","om_opb","5-4","no_list",0,,
+"TA_ALLOC_CTRL","om_opb","5-4","_8x4byte",1,,
+"TA_ALLOC_CTRL","om_opb","5-4","_16x4byte",2,,
+"TA_ALLOC_CTRL","om_opb","5-4","_32x4byte",3,,
+"TA_ALLOC_CTRL","o_opb","1-0","no_list",0,,
+"TA_ALLOC_CTRL","o_opb","1-0","_8x4byte",1,,
+"TA_ALLOC_CTRL","o_opb","1-0","_16x4byte",2,,
+"TA_ALLOC_CTRL","o_opb","1-0","_32x4byte",3,,
+,,,,,,
+"TA_LIST_INIT",,31,"list_init",1,,
+,,,,,,
+"TA_YUV_TEX_BASE",,"23-0","base_address",,"0xfffff8","in 8-byte units"
+,,,,,,
+"TA_YUV_TEX_CTRL","yuv_form",24,"yuv420",0,,
+"TA_YUV_TEX_CTRL","yuv_form",24,"yuv422",1,,
+"TA_YUV_TEX_CTRL","yuv_tex",16,"one_texture",0,,
+"TA_YUV_TEX_CTRL","yuv_tex",16,"multiple_textures",1,,
+"TA_YUV_TEX_CTRL",,"13-8","yuv_v_size",,"0x3f",
+"TA_YUV_TEX_CTRL",,"5-0","yuv_u_size",,"0x3f",
+,,,,,,
+"TA_YUV_TEX_CNT",,"12-0","yuv_num",,,
+,,,,,,
+"TA_LIST_CONT",,31,"list_cont",1,,
+,,,,,,
+"TA_NEXT_OPB_INIT",,"23-0","address",,"0xffffe0","in 32-byte units"
+,,,,,,
+"TA_OL_POINTERS",,31,"entry",,,
+"TA_OL_POINTERS",,30,"sprite",,,
+"TA_OL_POINTERS",,29,"triangle",,,
+"TA_OL_POINTERS",,"28-25","number_of_triangles_quads",,,
+"TA_OL_POINTERS",,24,"shadow",,,
+"TA_OL_POINTERS",,"23-2","pointer_address",,,
+"TA_OL_POINTERS",,"1-0","skip",,,
diff --git a/regs/ta_bits.ods b/regs/ta_bits.ods
index 0e14568..6c5dcf4 100644
Binary files a/regs/ta_bits.ods and b/regs/ta_bits.ods differ
diff --git a/ta.h b/ta.h
index 43a6662..6dd6715 100644
--- a/ta.h
+++ b/ta.h
@@ -3,10 +3,6 @@
 #define FPU_SHAD_SCALE__INTENSITY_SHADOW_ENABLE (1 << 8)
 #define FPU_SHAD_SCALE__SCALE_FACTOR(n) (((n) & 0xff) << 0)
 
-#define FPU_CULL_VAL__COMPARISON_VALUE(n) (_u32(__builtin_fabsf(n)))
-
-#define FPU_PERP_VAL__COMPARISON_VALUE(n) (_u32(__builtin_fabsf(n)))
-
 #define SPAN_SORT_CFG__CACHE_BYPASS (1 << 16)
 #define SPAN_SORT_CFG__OFFSET_SORT_ENABLE (1 << 8)
 #define SPAN_SORT_CFG__SPAN_SORT_ENABLE (1 << 0)
diff --git a/vga.cpp b/vga.cpp
index 8974135..4720a30 100644
--- a/vga.cpp
+++ b/vga.cpp
@@ -3,6 +3,9 @@
 #include "sh7091.h"
 #include "sh7091_bits.h"
 #include "holly.h"
+#include "holly/core_bits.h"
+#include "aica.h"
+#include "memorymap.h"
 
 #include "vga.h"
 #include "rgb.h"
@@ -18,112 +21,78 @@ uint32_t get_cable_type()
 
 void vga1()
 {
-  uint32_t fb_r_ctrl = holly.FB_R_CTRL;
-  holly.FB_R_CTRL = fb_r_ctrl & ~(1 << 0); // fb_enable = 0
-  uint32_t blank_video = 1;
-  holly.VO_CONTROL |= (blank_video << 3); // blank_video
+  holly.FB_R_CTRL = holly.FB_R_CTRL & ~fb_r_ctrl::fb_enable;
+  holly.VO_CONTROL |= vo_control::blank_video;
 
   holly.FB_R_SIZE = 0;
 
-  uint32_t vblank_in = 0x0208;
-  uint32_t vblank_out = 0x0015;
-  holly.SPG_VBLANK_INT = (vblank_out << 16) | (vblank_in << 0);
+  holly.SPG_VBLANK_INT = spg_vblank_int::vblank_out_interrupt_line_number(0x0015)
+                       | spg_vblank_int::vblank_in_interrupt_line_number(0x0208);
 
-  uint32_t sync_direction = 1;
-  holly.SPG_CONTROL = (sync_direction << 8);
+  holly.SPG_CONTROL = spg_control::sync_direction::output;
 
-  uint32_t hbstart = 0x0345; // default
-  uint32_t hbend   = 0x007e; // default
-  holly.SPG_HBLANK = (hbend << 16) | (hbstart << 0);
+  constexpr uint32_t hbstart = 0x0345;
+  holly.SPG_HBLANK = spg_hblank::hbend(0x007e) // default
+                   | spg_hblank::hbstart(hbstart); // default
 
-  uint32_t hcount = 0x0359; // default
-  uint32_t vcount = 0x020c; // non-default
-  holly.SPG_LOAD = (vcount << 16) | (hcount << 0);
+  holly.SPG_LOAD = spg_load::vcount(0x020c)  // default
+                 | spg_load::hcount(0x0359); // non-default
 
-  uint32_t vbstart = 0x0208; // non-default
-  uint32_t vbend = 0x0028; // non-default
-  holly.SPG_VBLANK = (vbend << 16) | (vbstart << 0);
+  holly.SPG_VBLANK = spg_vblank::vbend(0x0028) // non-default
+                   | spg_vblank::vbstart(0x0208); // non-default
 
-  uint32_t hswidth = 0x003f;
-  uint32_t vswidth = 0x0003;
-  uint32_t bpwidth = 0x0319;
-  uint32_t eqwidth = 0x000f;
-  holly.SPG_WIDTH =
-    (hswidth << 0)
-    | (vswidth << 8)
-    | (bpwidth << 12)
-    | (eqwidth << 22);
+  holly.SPG_WIDTH = spg_width::eqwidth(0x000f)
+		  | spg_width::bpwidth(0x0319)
+		  | spg_width::vswidth(0x0003)
+                  | spg_width::hswidth(0x003f);
 
-  uint32_t startx = 0x0a8;
-  uint32_t starty = 0x028;
-  holly.VO_STARTX = startx;
-  holly.VO_STARTY = (starty << 16) | (starty << 0);
+  constexpr uint32_t starty = 0x028;
+  holly.VO_STARTX = vo_startx::horizontal_start_position(0x0a8);
+  holly.VO_STARTY = vo_starty::vertical_start_position_on_field_2(starty)
+                  | vo_starty::vertical_start_position_on_field_1(starty);
 
-  holly.SPG_HBLANK_INT = hbstart << 16;
+  holly.SPG_HBLANK_INT = spg_hblank_int::line_comp_val(hbstart);
 }
 
 void vga2()
 {
-  holly.FB_BURSTCTRL = 0x00093f39;
+  holly.FB_BURSTCTRL = fb_burstctrl::wr_burst(0x09)
+                     | fb_burstctrl::vid_lat(0x3f)
+                     | fb_burstctrl::vid_burst(0x39);
 
-  uint32_t xsize = 640;
-  uint32_t ysize = 480;
+  constexpr uint32_t x_size = 640;
+  constexpr uint32_t y_size = 480;
 
-  uint32_t fb_xclip_min = 0;
-  uint32_t fb_xclip_max = xsize-1;
-  holly.FB_X_CLIP = (fb_xclip_max << 16) | (fb_xclip_min << 0);
-  uint32_t fb_yclip_min = 0;
-  uint32_t fb_yclip_max = ysize-1;
-  holly.FB_Y_CLIP = (fb_yclip_max << 16) | (fb_yclip_min << 0);
+  holly.FB_X_CLIP = fb_x_clip::fb_x_clip_max(x_size - 1)
+                  | fb_x_clip::fb_x_clip_min(0);
 
-  uint32_t fb_xsize = (xsize * 16)/(32) - 1;
-  uint32_t fb_ysize = ysize - 3;
-  uint32_t fb_mod = 1;
-  holly.FB_R_SIZE = 0
-    | (fb_xsize << 0)
-    | (fb_ysize << 10)
-    | (fb_mod << 20);
+  holly.FB_Y_CLIP = fb_y_clip::fb_y_clip_max(y_size - 1)
+                  | fb_y_clip::fb_y_clip_min(0);
 
-  uint32_t coeff0 = 0x40;
-  uint32_t coeff1 = 0x80;
-  holly.Y_COEFF = (coeff1 << 8) | (coeff0 << 0);
+  holly.FB_R_SIZE = fb_r_size::fb_modulus(1)
+                  | fb_r_size::fb_y_size(y_size - 3)
+                  | fb_r_size::fb_x_size((x_size * 16) / 32 - 1);
 
-  uint32_t vscale_factor = 0x0400;
-  holly.SCALER_CTL = (vscale_factor << 0);
+  holly.Y_COEFF = y_coeff::coefficient_1(0x80)
+                | y_coeff::coefficient_0_2(0x40);
 
-  holly.FB_W_SOF1 = 0;
-  holly.FB_W_SOF2 = 0;
-  holly.FB_R_SOF1 = 0;
-  holly.FB_R_SOF2 = 0;
+  // in 6.10 fixed point; 0x0400 is 1x vertical scale
+  holly.SCALER_CTL = scaler_ctl::vertical_scale_factor(0x0400);
 
-  holly.FB_R_CTRL = 0
-    | 1 << 23 // vclk_div
-    | 0 << 22 // fb_strip_buf_en
-    | 0 << 16 // fb_strip_size
-    | 0 << 8 // fb_chroma_threshold
-    | 0 << 4 // fb_concat
-    | 1 << 2 // fb_depth
-    | 0 << 1 // fb_line_double
-    | 1 << 0 // fb_enable
-    ;
+  holly.FB_W_SOF1 = fb_w_sof1::frame_buffer_write_address_frame_1(0);
+  holly.FB_W_SOF2 = fb_w_sof2::frame_buffer_write_address_frame_2(0);
+  holly.FB_R_SOF1 = fb_r_sof1::frame_buffer_read_address_frame_1(0);
+  holly.FB_R_SOF2 = fb_r_sof2::frame_buffer_read_address_frame_2(0);
 
-  uint32_t hsync_pol    = 0;
-  uint32_t vsync_pol    = 0;
-  uint32_t blank_pol    = 0;
-  uint32_t blank_video  = 0;
-  uint32_t field_mode   = 0;
-  uint32_t pixel_double = 0;
-  uint32_t pclk_delay   = 0x16;
-  holly.VO_CONTROL = 0
-    | (( pclk_delay   & 0x3f) << 16 )
-    | (( pixel_double & 0x01) <<  8 )
-    | (( field_mode   & 0x0f) <<  4 )
-    | (( blank_video  & 0x01) <<  3 )
-    | (( blank_pol    & 0x01) <<  2 )
-    | (( vsync_pol    & 0x01) <<  1 )
-    | (( hsync_pol    & 0x01) <<  0 );
+  holly.FB_R_CTRL = fb_r_ctrl::vclk_div::pclk_vclk_1
+                  | fb_r_ctrl::fb_depth::_0565_rgb_16bit
+                  | fb_r_ctrl::fb_enable;
 
-  *((reg32 *)0xa0702c00) = 0;
+#define DVE_OUTPUT_MODE (&aica[0x2c00])
+#define DVE_OUTPUT_MODE__VGA (0b00 << 0)
+  *DVE_OUTPUT_MODE = DVE_OUTPUT_MODE__VGA;
+#undef DVE_OUTPUT_MODE
+#undef DVE_OUTPUT_MODE__VGA
 }
 
 void v_sync_in()
@@ -154,41 +123,27 @@ void vga()
 {
   get_cable_type();
 
-  holly.SOFTRESET = 0b111;
-  holly.TEXT_CONTROL = 3;
-  holly.FB_W_CTRL = 9;
+  holly.SOFTRESET = softreset::sdram_if_soft_reset
+		  | softreset::pipeline_soft_reset
+		  | softreset::ta_soft_reset;
+  holly.TEXT_CONTROL = text_control::stride(3);
 
-  /*
-   */
   vga1();
   vga2();
 
+  holly.VO_BORDER_COL = vo_border_col::red(0x00)
+                      | vo_border_col::green(0xff)
+                      | vo_border_col::blue(0x00);
+  holly.VO_CONTROL = vo_control::pclk_delay(0x16);
+
   v_sync_in();
 
-  holly.VO_BORDER_COL = (63 << 5) | (31 << 0);
-  //holly.VO_CONTROL = 0x0016;
-  uint32_t hsync_pol    = 0;
-  uint32_t vsync_pol    = 0;
-  uint32_t blank_pol    = 0;
-  uint32_t blank_video  = 0;
-  uint32_t field_mode   = 0;
-  uint32_t pixel_double = 0;
-  uint32_t pclk_delay   = 0x16;
-  HOLLY.VO_CONTROL = 0
-    | (( pclk_delay   & 0x3f) << 16 )
-    | (( pixel_double & 0x01) <<  8 )
-    | (( field_mode   & 0x0f) <<  4 )
-    | (( blank_video  & 0x01) <<  3 )
-    | (( blank_pol    & 0x01) <<  2 )
-    | (( vsync_pol    & 0x01) <<  1 )
-    | (( hsync_pol    & 0x01) <<  0 );
-
-  holly.SOFTRESET = 0b000;
+  holly.SOFTRESET = 0;
 }
 
 void fill_framebuffer()
 {
-  reg16 * vram = (reg16 *)0xa5000000;
+  volatile uint16_t * vram = reinterpret_cast<volatile uint16_t *>(texture_memory);
   for (int y = 0; y < 480; y++) {
     for (int x = 0; x < 640; x++) {
       struct hsv hsv = {(y * 255) / 480, 255, 255};